vrgiu.c revision 1.13
1 /* $NetBSD: vrgiu.c,v 1.13 2000/09/25 01:56:57 sato Exp $ */ 2 /*- 3 * Copyright (c) 1999 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/boot_flag.h> 41 #include <sys/queue.h> 42 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 43 44 #include <mips/cpuregs.h> 45 #include <machine/bus.h> 46 47 #include <hpcmips/vr/vripreg.h> 48 #include <hpcmips/vr/vripvar.h> 49 #include <hpcmips/vr/vrgiureg.h> 50 51 #include "locators.h" 52 53 #define VRGIUDEBUG 54 #ifdef VRGIUDEBUG 55 #define DEBUG_IO 1 56 #define DEBUG_INTR 2 57 #ifndef VRGIUDEBUG_CONF 58 #define VRGIUDEBUG_CONF 0 59 #endif /* VRGIUDEBUG_CONF */ 60 int vrgiu_debug = VRGIUDEBUG_CONF; 61 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 62 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 63 #define DDUMP_IOSETTING(flag, sc) \ 64 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 65 #define VPRINTF(flag, arg) \ 66 if (bootverbose || vrgiu_debug & flag) printf arg; 67 #define VDUMP_IO(flag, sc) \ 68 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 69 #define VDUMP_IOSETTING(flag, sc) \ 70 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 71 #else 72 #define DPRINTF(flag, arg) 73 #define DDUMP_IO(flag, sc) 74 #define DDUMP_IOSETTING(flag, sc) 75 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 76 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 77 #define VDUMP_IOSETTING(flag, sc) \ 78 if (bootverbose) vrgiu_dump_iosetting(sc); 79 #endif 80 81 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 82 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 83 84 int vrgiu_match __P((struct device*, struct cfdata*, void*)); 85 void vrgiu_attach __P((struct device*, struct device*, void*)); 86 int vrgiu_intr __P((void*)); 87 int vrgiu_print __P((void*, const char*)); 88 void vrgiu_callback __P((struct device*)); 89 90 void vrgiu_dump_regs(struct vrgiu_softc *sc); 91 void vrgiu_dump_io(struct vrgiu_softc *sc); 92 void vrgiu_dump_iosetting(struct vrgiu_softc *sc); 93 u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t)); 94 u_int16_t vrgiu_regread __P((vrgiu_chipset_tag_t, bus_addr_t)); 95 void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t)); 96 void vrgiu_regwrite __P((vrgiu_chipset_tag_t, bus_addr_t, u_int16_t)); 97 98 int vrgiu_port_read __P((vrgiu_chipset_tag_t, int)); 99 int vrgiu_port_write __P((vrgiu_chipset_tag_t, int, int)); 100 101 void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*)); 102 void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*)); 103 104 struct vrgiu_function_tag vrgiu_functions = { 105 vrgiu_port_read, 106 vrgiu_port_write, 107 vrgiu_regread_4, 108 vrgiu_regwrite_4, 109 vrgiu_intr_establish, 110 vrgiu_intr_disestablish 111 }; 112 113 struct cfattach vrgiu_ca = { 114 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 115 }; 116 117 int 118 vrgiu_match(parent, cf, aux) 119 struct device *parent; 120 struct cfdata *cf; 121 void *aux; 122 { 123 return 2; /* 1st attach group of vrip */ 124 } 125 126 void 127 vrgiu_attach(parent, self, aux) 128 struct device *parent; 129 struct device *self; 130 void *aux; 131 { 132 struct vrip_attach_args *va = aux; 133 struct vrgiu_softc *sc = (void*)self; 134 struct gpbus_attach_args gpa; 135 int i; 136 137 sc->sc_vc = va->va_vc; 138 sc->sc_iot = va->va_iot; 139 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 140 0 /* no cache */, &sc->sc_ioh); 141 /* 142 * Disable all interrupts. 143 */ 144 sc->sc_intr_mask = 0; 145 printf("\n"); 146 #ifdef WINCE_DEFAULT_SETTING 147 #warning WINCE_DEFAULT_SETTING 148 #else 149 VPRINTF(DEBUG_IO, ("WIN setting: ")); 150 VDUMP_IOSETTING(DEBUG_IO, sc); 151 VPRINTF(DEBUG_IO, ("\n")); 152 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 153 #endif 154 155 for (i = 0; i < MAX_GPIO_INOUT; i++) 156 TAILQ_INIT(&sc->sc_intr_head[i]); 157 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 158 vrgiu_intr, sc))) { 159 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 160 return; 161 } 162 vrgiu_functions.gf_intr_establish = vrgiu_intr_establish; 163 vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish; 164 /* 165 * Register functions to upper interface. 166 */ 167 vrip_giu_function_register(va->va_vc, &vrgiu_functions, self); 168 169 /* Display port status (Input/Output) for debugging */ 170 VPRINTF(DEBUG_IO, ("I/O setting: ")); 171 DDUMP_IOSETTING(DEBUG_IO, sc); 172 VPRINTF(DEBUG_IO, ("\n")); 173 VPRINTF(DEBUG_IO, (" data:")); 174 VDUMP_IO(DEBUG_IO, sc); 175 176 /* 177 * General purpose bus 178 */ 179 gpa.gpa_busname = "gpbus"; 180 gpa.gpa_gc = sc; 181 gpa.gpa_gf = &vrgiu_functions; 182 while (config_found(self, &gpa, vrgiu_print)) ; 183 /* 184 * GIU-ISA bridge 185 */ 186 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 187 config_defer(self, vrgiu_callback); 188 #else 189 vrgiu_callback(self); 190 #endif 191 } 192 193 void 194 vrgiu_callback(self) 195 struct device *self; 196 { 197 struct vrgiu_softc *sc = (void*)self; 198 struct gpbus_attach_args gpa; 199 200 gpa.gpa_busname = "vrisab"; 201 gpa.gpa_gc = sc; 202 gpa.gpa_gf = &vrgiu_functions; 203 config_found(self, &gpa, vrgiu_print); 204 } 205 206 int 207 vrgiu_print(aux, pnp) 208 void *aux; 209 const char *pnp; 210 { 211 if (pnp) 212 return (QUIET); 213 return (UNCONF); 214 } 215 216 void 217 vrgiu_dump_iosetting(sc) 218 struct vrgiu_softc *sc; 219 { 220 long iosel, inten, useupdn, termupdn; 221 u_int32_t m; 222 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 223 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 224 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 225 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 226 for (m = 0x80000000; m; m >>=1) 227 printf ("%c" , (useupdn&m) ? 228 ((termupdn&m) ? 'U' : 'D') : 229 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 230 } 231 232 void 233 vrgiu_dump_io(sc) 234 struct vrgiu_softc *sc; 235 { 236 u_int32_t preg[2]; 237 238 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 239 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 240 241 bitdisp64(preg); 242 } 243 244 void 245 vrgiu_dump_regs(sc) 246 struct vrgiu_softc *sc; 247 { 248 if (sc == NULL) { 249 panic("%s(%d): VRGIU device not initialized\n", 250 __FILE__, __LINE__); 251 } 252 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 253 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 254 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 255 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 256 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 257 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 258 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 259 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 260 } 261 /* 262 * GIU regster access method. 263 */ 264 u_int32_t 265 vrgiu_regread_4(vc, offs) 266 vrgiu_chipset_tag_t vc; 267 bus_addr_t offs; 268 { 269 struct vrgiu_softc *sc = (void*)vc; 270 u_int16_t reg[2]; 271 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 272 return reg[0]|(reg[1]<<16); 273 } 274 275 u_int16_t 276 vrgiu_regread(vc, off) 277 vrgiu_chipset_tag_t vc; 278 bus_addr_t off; 279 { 280 struct vrgiu_softc *sc = (void*)vc; 281 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 282 } 283 284 void 285 vrgiu_regwrite_4(vc, offs, data) 286 vrgiu_chipset_tag_t vc; 287 bus_addr_t offs; 288 u_int32_t data; 289 { 290 struct vrgiu_softc *sc = (void*)vc; 291 292 u_int16_t reg[2]; 293 reg[0] = data & 0xffff; 294 reg[1] = (data>>16)&0xffff; 295 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 296 } 297 298 void 299 vrgiu_regwrite(vc, off, data) 300 vrgiu_chipset_tag_t vc; 301 bus_addr_t off; 302 u_int16_t data; 303 { 304 struct vrgiu_softc *sc = (void*)vc; 305 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 306 } 307 308 /* 309 * PORT 310 */ 311 int 312 vrgiu_port_read(vc, port) 313 vrgiu_chipset_tag_t vc; 314 int port; 315 { 316 int on; 317 318 if (!LEGAL_OUT_PORT(port)) 319 panic("vrgiu_port_read: illegal gpio port"); 320 321 if (port < 32) 322 on = (vrgiu_regread_4(vc, GIUPIOD_REG) & (1 << port)); 323 else 324 on = (vrgiu_regread_4(vc, GIUPODAT_REG) & (1 << (port - 32))); 325 326 return (on ? 1 : 0); 327 } 328 329 int 330 vrgiu_port_write(vc, port, onoff) 331 vrgiu_chipset_tag_t vc; 332 int port; 333 int onoff; 334 { 335 u_int32_t reg[2]; 336 int bank; 337 338 if (!LEGAL_OUT_PORT(port)) 339 panic("vrgiu_port_write: illegal gpio port"); 340 341 reg[0] = vrgiu_regread_4(vc, GIUPIOD_REG); 342 reg[1] = vrgiu_regread_4(vc, GIUPODAT_REG); 343 bank = port < 32 ? 0 : 1; 344 if (bank == 1) 345 port -= 32; 346 347 if (onoff) 348 reg[bank] |= (1<<port); 349 else 350 reg[bank] &= ~(1<<port); 351 vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]); 352 vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]); 353 354 return 0; 355 } 356 /* 357 * For before autoconfiguration. 358 */ 359 void 360 __vrgiu_out(port, data) 361 int port; 362 int data; 363 { 364 u_int16_t reg; 365 u_int32_t addr; 366 int offs; 367 368 if (!LEGAL_OUT_PORT(port)) 369 panic("__vrgiu_out: illegal gpio port"); 370 if (port < 16) { 371 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 372 offs = port; 373 } else if (port < 32) { 374 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 375 offs = port - 16; 376 } else if (port < 48) { 377 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 378 offs = port - 32; 379 } else { 380 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 381 offs = port - 48; 382 panic ("__vrgiu_out: not coded yet."); 383 } 384 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 385 386 wbflush(); 387 reg = *((volatile u_int16_t*)addr); 388 if (data) { 389 reg |= (1 << offs); 390 } else { 391 reg &= ~(1 << offs); 392 } 393 *((volatile u_int16_t*)addr) = reg; 394 wbflush(); 395 } 396 /* 397 * Interrupt staff 398 */ 399 void * 400 vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg) 401 vrgiu_chipset_tag_t ic; 402 int port; /* GPIO pin # */ 403 int mode; /* GIU trigger setting */ 404 int level; /* XXX not yet */ 405 int (*ih_fun) __P((void*)); 406 void *ih_arg; 407 { 408 struct vrgiu_softc *sc = (void*)ic; 409 int s; 410 u_int32_t reg, mask; 411 struct vrgiu_intr_entry *ih; 412 413 if (!LEGAL_INTR_PORT(port)) 414 panic ("vrgiu_intr_establish: bogus interrupt line."); 415 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 416 panic ("vrgiu_intr_establish: bogus interrupt type."); 417 else 418 sc->sc_intr_mode[port] = mode; 419 mask = (1 << port); 420 421 s = splhigh(); 422 423 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 424 panic ("vrgiu_intr_establish: no memory."); 425 426 ih->ih_port = port; 427 ih->ih_fun = ih_fun; 428 ih->ih_arg = ih_arg; 429 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 430 #ifdef WINCE_DEFAULT_SETTING 431 #warning WINCE_DEFAULT_SETTING 432 #else 433 /* 434 * Setup registers 435 */ 436 /* Input mode */ 437 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 438 reg &= ~mask; 439 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 440 441 /* interrupt type */ 442 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 443 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 444 if (mode & VRGIU_INTR_EDGE) { 445 DPRINTF(DEBUG_INTR, ("edge]")); 446 reg |= mask; /* edge */ 447 } else { 448 DPRINTF(DEBUG_INTR, ("level]")); 449 reg &= ~mask; /* level */ 450 } 451 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 452 453 /* interrupt level */ 454 if (!(mode & VRGIU_INTR_EDGE)) { 455 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 456 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 457 if (mode & VRGIU_INTR_HIGH) { 458 DPRINTF(DEBUG_INTR, ("high]")); 459 reg |= mask; /* high */ 460 } else { 461 DPRINTF(DEBUG_INTR, ("low]")); 462 reg &= ~mask; /* low */ 463 } 464 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 465 } 466 /* hold or through */ 467 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 468 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 469 if (mode & VRGIU_INTR_HOLD) { 470 DPRINTF(DEBUG_INTR, ("hold]")); 471 reg |= mask; /* hold */ 472 } else { 473 DPRINTF(DEBUG_INTR, ("through]")); 474 reg &= ~mask; /* through */ 475 } 476 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 477 #endif 478 /* 479 * clear interrupt status 480 */ 481 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 482 reg &= ~mask; 483 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 484 /* 485 * enable interrupt 486 */ 487 #ifdef WINCE_DEFAULT_SETTING 488 #warning WINCE_DEFAULT_SETTING 489 #else 490 sc->sc_intr_mask |= mask; 491 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 492 /* Unmask GIU level 2 mask register */ 493 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 494 #endif 495 splx(s); 496 497 DPRINTF(DEBUG_INTR, ("\n")); 498 499 return ih; 500 } 501 502 void 503 vrgiu_intr_disestablish(ic, arg) 504 vrgiu_chipset_tag_t ic; 505 void *arg; 506 { 507 struct vrgiu_intr_entry *ihe = arg; 508 struct vrgiu_softc *sc = (void*)ic; 509 int port = ihe->ih_port; 510 struct vrgiu_intr_entry *ih; 511 int s; 512 513 s = splhigh(); 514 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 515 if (ih == ihe) { 516 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 517 free(ih, M_DEVBUF); 518 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 519 /* Disable interrupt */ 520 #ifdef WINCE_DEFAULT_SETTING 521 #warning WINCE_DEFAULT_SETTING 522 #else 523 sc->sc_intr_mask &= ~(1<<port); 524 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 525 #endif 526 } 527 splx(s); 528 return; 529 } 530 } 531 panic("vrgiu_intr_disetablish: no such a handle."); 532 /* NOTREACHED */ 533 } 534 535 int 536 vrgiu_intr(arg) 537 void *arg; 538 { 539 #ifdef DUMP_GIU_LEVEL2_INTR 540 #warning DUMP_GIU_LEVEL2_INTR 541 static u_int32_t oreg; 542 #endif 543 struct vrgiu_softc *sc = arg; 544 int i; 545 u_int32_t reg; 546 /* Get Level 2 interrupt status */ 547 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 548 #ifdef DUMP_GIU_LEVEL2_INTR 549 #warning DUMP_GIU_LEVEL2_INTR 550 { 551 u_int32_t uedge, dedge, j; 552 for (j = 0x80000000; j > 0; j >>=1) 553 printf ("%c" , reg&j ? '|' : '.'); 554 uedge = (reg ^ oreg) & reg; 555 dedge = (reg ^ oreg) & ~reg; 556 if (uedge || dedge) { 557 for (j = 0; j < 32; j++) { 558 if (uedge & (1 << j)) 559 printf ("+%d", j); 560 else if (dedge & (1 << j)) 561 printf ("-%d", j); 562 } 563 } 564 oreg = reg; 565 printf ("\n"); 566 } 567 #endif 568 /* Clear interrupt */ 569 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 570 571 /* Dispatch handler */ 572 for (i = 0; i < MAX_GPIO_INOUT; i++) { 573 if (reg & (1 << i)) { 574 register struct vrgiu_intr_entry *ih; 575 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 576 ih->ih_fun(ih->ih_arg); 577 } 578 } 579 } 580 581 return 0; 582 } 583
Indexes created Fri Sep 26 20:09:58 GMT 2025