vrgiu.c revision 1.14
1 /* $NetBSD: vrgiu.c,v 1.14 2000/09/25 03:47:37 sato Exp $ */ 2 /*- 3 * Copyright (c) 1999 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/boot_flag.h> 42 43 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 44 45 #include <mips/cpuregs.h> 46 #include <machine/bus.h> 47 48 #include <hpcmips/vr/vripreg.h> 49 #include <hpcmips/vr/vripvar.h> 50 #include <hpcmips/vr/vrgiureg.h> 51 52 #include "locators.h" 53 54 #define VRGIUDEBUG 55 #ifdef VRGIUDEBUG 56 #define DEBUG_IO 1 57 #define DEBUG_INTR 2 58 #ifndef VRGIUDEBUG_CONF 59 #define VRGIUDEBUG_CONF 0 60 #endif /* VRGIUDEBUG_CONF */ 61 int vrgiu_debug = VRGIUDEBUG_CONF; 62 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 63 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 64 #define DDUMP_IOSETTING(flag, sc) \ 65 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 66 #define VPRINTF(flag, arg) \ 67 if (bootverbose || vrgiu_debug & flag) printf arg; 68 #define VDUMP_IO(flag, sc) \ 69 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 70 #define VDUMP_IOSETTING(flag, sc) \ 71 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 72 #else 73 #define DPRINTF(flag, arg) 74 #define DDUMP_IO(flag, sc) 75 #define DDUMP_IOSETTING(flag, sc) 76 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 77 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 78 #define VDUMP_IOSETTING(flag, sc) \ 79 if (bootverbose) vrgiu_dump_iosetting(sc); 80 #endif 81 82 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 83 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 84 85 int vrgiu_match __P((struct device*, struct cfdata*, void*)); 86 void vrgiu_attach __P((struct device*, struct device*, void*)); 87 int vrgiu_intr __P((void*)); 88 int vrgiu_print __P((void*, const char*)); 89 void vrgiu_callback __P((struct device*)); 90 91 void vrgiu_dump_regs __P((struct vrgiu_softc *sc)); 92 void vrgiu_dump_io __P((struct vrgiu_softc *sc)); 93 void vrgiu_diff_io __P((void)); 94 void vrgiu_dump_iosetting __P((struct vrgiu_softc *sc)); 95 void vrgiu_diff_iosetting __P((void)); 96 u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t)); 97 u_int16_t vrgiu_regread __P((vrgiu_chipset_tag_t, bus_addr_t)); 98 void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t)); 99 void vrgiu_regwrite __P((vrgiu_chipset_tag_t, bus_addr_t, u_int16_t)); 100 101 int vrgiu_port_read __P((vrgiu_chipset_tag_t, int)); 102 int vrgiu_port_write __P((vrgiu_chipset_tag_t, int, int)); 103 104 void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*)); 105 void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*)); 106 107 struct vrgiu_function_tag vrgiu_functions = { 108 vrgiu_port_read, 109 vrgiu_port_write, 110 vrgiu_regread_4, 111 vrgiu_regwrite_4, 112 vrgiu_intr_establish, 113 vrgiu_intr_disestablish 114 }; 115 116 struct cfattach vrgiu_ca = { 117 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 118 }; 119 120 struct vrgiu_softc *this_giu; 121 122 int 123 vrgiu_match(parent, cf, aux) 124 struct device *parent; 125 struct cfdata *cf; 126 void *aux; 127 { 128 return 2; /* 1st attach group of vrip */ 129 } 130 131 void 132 vrgiu_attach(parent, self, aux) 133 struct device *parent; 134 struct device *self; 135 void *aux; 136 { 137 struct vrip_attach_args *va = aux; 138 struct vrgiu_softc *sc = (void*)self; 139 struct gpbus_attach_args gpa; 140 int i; 141 142 this_giu = sc; 143 sc->sc_vc = va->va_vc; 144 sc->sc_iot = va->va_iot; 145 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 146 0 /* no cache */, &sc->sc_ioh); 147 /* 148 * Disable all interrupts. 149 */ 150 sc->sc_intr_mask = 0; 151 printf("\n"); 152 #ifdef WINCE_DEFAULT_SETTING 153 #warning WINCE_DEFAULT_SETTING 154 #else 155 VPRINTF(DEBUG_IO, ("WIN setting: ")); 156 VDUMP_IOSETTING(DEBUG_IO, sc); 157 VPRINTF(DEBUG_IO, ("\n")); 158 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 159 #endif 160 161 for (i = 0; i < MAX_GPIO_INOUT; i++) 162 TAILQ_INIT(&sc->sc_intr_head[i]); 163 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 164 vrgiu_intr, sc))) { 165 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 166 return; 167 } 168 vrgiu_functions.gf_intr_establish = vrgiu_intr_establish; 169 vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish; 170 /* 171 * Register functions to upper interface. 172 */ 173 vrip_giu_function_register(va->va_vc, &vrgiu_functions, self); 174 175 /* Display port status (Input/Output) for debugging */ 176 VPRINTF(DEBUG_IO, ("I/O setting: ")); 177 DDUMP_IOSETTING(DEBUG_IO, sc); 178 VPRINTF(DEBUG_IO, ("\n")); 179 VPRINTF(DEBUG_IO, (" data:")); 180 VDUMP_IO(DEBUG_IO, sc); 181 182 /* 183 * General purpose bus 184 */ 185 gpa.gpa_busname = "gpbus"; 186 gpa.gpa_gc = sc; 187 gpa.gpa_gf = &vrgiu_functions; 188 while (config_found(self, &gpa, vrgiu_print)) ; 189 /* 190 * GIU-ISA bridge 191 */ 192 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 193 config_defer(self, vrgiu_callback); 194 #else 195 vrgiu_callback(self); 196 #endif 197 } 198 199 void 200 vrgiu_callback(self) 201 struct device *self; 202 { 203 struct vrgiu_softc *sc = (void*)self; 204 struct gpbus_attach_args gpa; 205 206 gpa.gpa_busname = "vrisab"; 207 gpa.gpa_gc = sc; 208 gpa.gpa_gf = &vrgiu_functions; 209 config_found(self, &gpa, vrgiu_print); 210 } 211 212 int 213 vrgiu_print(aux, pnp) 214 void *aux; 215 const char *pnp; 216 { 217 if (pnp) 218 return (QUIET); 219 return (UNCONF); 220 } 221 222 void 223 vrgiu_dump_iosetting(sc) 224 struct vrgiu_softc *sc; 225 { 226 long iosel, inten, useupdn, termupdn; 227 u_int32_t m; 228 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 229 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 230 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 231 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 232 for (m = 0x80000000; m; m >>=1) 233 printf ("%c" , (useupdn&m) ? 234 ((termupdn&m) ? 'U' : 'D') : 235 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 236 } 237 238 void 239 vrgiu_diff_iosetting() 240 { 241 struct vrgiu_softc *sc = this_giu; 242 static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0; 243 long iosel, inten, useupdn, termupdn; 244 u_int32_t m; 245 246 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 247 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 248 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 249 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 250 if (oiosel != iosel || ointen != inten || 251 ouseupdn != useupdn || otermupdn != termupdn) { 252 for (m = 0x80000000; m; m >>=1) 253 printf ("%c" , (useupdn&m) ? 254 ((termupdn&m) ? 'U' : 'D') : 255 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 256 } 257 oiosel = iosel; 258 ointen = inten; 259 ouseupdn = useupdn; 260 otermupdn = termupdn; 261 } 262 263 void 264 vrgiu_dump_io(sc) 265 struct vrgiu_softc *sc; 266 { 267 u_int32_t preg[2]; 268 269 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 270 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 271 272 bitdisp64(preg); 273 } 274 275 void 276 vrgiu_diff_io() 277 { 278 struct vrgiu_softc *sc = this_giu; 279 static u_int32_t opreg[2] = {0, 0}; 280 u_int32_t preg[2]; 281 282 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 283 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 284 285 if (opreg[0] != preg[0] || opreg[1] != preg[1]) { 286 printf("giu data: "); 287 bitdisp64(preg); 288 } 289 opreg[0] = preg[0]; 290 opreg[1] = preg[1]; 291 } 292 293 void 294 vrgiu_dump_regs(sc) 295 struct vrgiu_softc *sc; 296 { 297 if (sc == NULL) { 298 panic("%s(%d): VRGIU device not initialized\n", 299 __FILE__, __LINE__); 300 } 301 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 302 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 303 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 304 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 305 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 306 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 307 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 308 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 309 } 310 /* 311 * GIU regster access method. 312 */ 313 u_int32_t 314 vrgiu_regread_4(vc, offs) 315 vrgiu_chipset_tag_t vc; 316 bus_addr_t offs; 317 { 318 struct vrgiu_softc *sc = (void*)vc; 319 u_int16_t reg[2]; 320 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 321 return reg[0]|(reg[1]<<16); 322 } 323 324 u_int16_t 325 vrgiu_regread(vc, off) 326 vrgiu_chipset_tag_t vc; 327 bus_addr_t off; 328 { 329 struct vrgiu_softc *sc = (void*)vc; 330 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 331 } 332 333 void 334 vrgiu_regwrite_4(vc, offs, data) 335 vrgiu_chipset_tag_t vc; 336 bus_addr_t offs; 337 u_int32_t data; 338 { 339 struct vrgiu_softc *sc = (void*)vc; 340 341 u_int16_t reg[2]; 342 reg[0] = data & 0xffff; 343 reg[1] = (data>>16)&0xffff; 344 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 345 } 346 347 void 348 vrgiu_regwrite(vc, off, data) 349 vrgiu_chipset_tag_t vc; 350 bus_addr_t off; 351 u_int16_t data; 352 { 353 struct vrgiu_softc *sc = (void*)vc; 354 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 355 } 356 357 /* 358 * PORT 359 */ 360 int 361 vrgiu_port_read(vc, port) 362 vrgiu_chipset_tag_t vc; 363 int port; 364 { 365 int on; 366 367 if (!LEGAL_OUT_PORT(port)) 368 panic("vrgiu_port_read: illegal gpio port"); 369 370 if (port < 32) 371 on = (vrgiu_regread_4(vc, GIUPIOD_REG) & (1 << port)); 372 else 373 on = (vrgiu_regread_4(vc, GIUPODAT_REG) & (1 << (port - 32))); 374 375 return (on ? 1 : 0); 376 } 377 378 int 379 vrgiu_port_write(vc, port, onoff) 380 vrgiu_chipset_tag_t vc; 381 int port; 382 int onoff; 383 { 384 u_int32_t reg[2]; 385 int bank; 386 387 if (!LEGAL_OUT_PORT(port)) 388 panic("vrgiu_port_write: illegal gpio port"); 389 390 reg[0] = vrgiu_regread_4(vc, GIUPIOD_REG); 391 reg[1] = vrgiu_regread_4(vc, GIUPODAT_REG); 392 bank = port < 32 ? 0 : 1; 393 if (bank == 1) 394 port -= 32; 395 396 if (onoff) 397 reg[bank] |= (1<<port); 398 else 399 reg[bank] &= ~(1<<port); 400 vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]); 401 vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]); 402 403 return 0; 404 } 405 /* 406 * For before autoconfiguration. 407 */ 408 void 409 __vrgiu_out(port, data) 410 int port; 411 int data; 412 { 413 u_int16_t reg; 414 u_int32_t addr; 415 int offs; 416 417 if (!LEGAL_OUT_PORT(port)) 418 panic("__vrgiu_out: illegal gpio port"); 419 if (port < 16) { 420 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 421 offs = port; 422 } else if (port < 32) { 423 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 424 offs = port - 16; 425 } else if (port < 48) { 426 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 427 offs = port - 32; 428 } else { 429 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 430 offs = port - 48; 431 panic ("__vrgiu_out: not coded yet."); 432 } 433 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 434 435 wbflush(); 436 reg = *((volatile u_int16_t*)addr); 437 if (data) { 438 reg |= (1 << offs); 439 } else { 440 reg &= ~(1 << offs); 441 } 442 *((volatile u_int16_t*)addr) = reg; 443 wbflush(); 444 } 445 /* 446 * Interrupt staff 447 */ 448 void * 449 vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg) 450 vrgiu_chipset_tag_t ic; 451 int port; /* GPIO pin # */ 452 int mode; /* GIU trigger setting */ 453 int level; /* XXX not yet */ 454 int (*ih_fun) __P((void*)); 455 void *ih_arg; 456 { 457 struct vrgiu_softc *sc = (void*)ic; 458 int s; 459 u_int32_t reg, mask; 460 struct vrgiu_intr_entry *ih; 461 462 if (!LEGAL_INTR_PORT(port)) 463 panic ("vrgiu_intr_establish: bogus interrupt line."); 464 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 465 panic ("vrgiu_intr_establish: bogus interrupt type."); 466 else 467 sc->sc_intr_mode[port] = mode; 468 mask = (1 << port); 469 470 s = splhigh(); 471 472 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 473 panic ("vrgiu_intr_establish: no memory."); 474 475 ih->ih_port = port; 476 ih->ih_fun = ih_fun; 477 ih->ih_arg = ih_arg; 478 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 479 #ifdef WINCE_DEFAULT_SETTING 480 #warning WINCE_DEFAULT_SETTING 481 #else 482 /* 483 * Setup registers 484 */ 485 /* Input mode */ 486 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 487 reg &= ~mask; 488 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 489 490 /* interrupt type */ 491 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 492 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 493 if (mode & VRGIU_INTR_EDGE) { 494 DPRINTF(DEBUG_INTR, ("edge]")); 495 reg |= mask; /* edge */ 496 } else { 497 DPRINTF(DEBUG_INTR, ("level]")); 498 reg &= ~mask; /* level */ 499 } 500 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 501 502 /* interrupt level */ 503 if (!(mode & VRGIU_INTR_EDGE)) { 504 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 505 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 506 if (mode & VRGIU_INTR_HIGH) { 507 DPRINTF(DEBUG_INTR, ("high]")); 508 reg |= mask; /* high */ 509 } else { 510 DPRINTF(DEBUG_INTR, ("low]")); 511 reg &= ~mask; /* low */ 512 } 513 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 514 } 515 /* hold or through */ 516 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 517 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 518 if (mode & VRGIU_INTR_HOLD) { 519 DPRINTF(DEBUG_INTR, ("hold]")); 520 reg |= mask; /* hold */ 521 } else { 522 DPRINTF(DEBUG_INTR, ("through]")); 523 reg &= ~mask; /* through */ 524 } 525 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 526 #endif 527 /* 528 * clear interrupt status 529 */ 530 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 531 reg &= ~mask; 532 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 533 /* 534 * enable interrupt 535 */ 536 #ifdef WINCE_DEFAULT_SETTING 537 #warning WINCE_DEFAULT_SETTING 538 #else 539 sc->sc_intr_mask |= mask; 540 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 541 /* Unmask GIU level 2 mask register */ 542 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 543 #endif 544 splx(s); 545 546 DPRINTF(DEBUG_INTR, ("\n")); 547 548 return ih; 549 } 550 551 void 552 vrgiu_intr_disestablish(ic, arg) 553 vrgiu_chipset_tag_t ic; 554 void *arg; 555 { 556 struct vrgiu_intr_entry *ihe = arg; 557 struct vrgiu_softc *sc = (void*)ic; 558 int port = ihe->ih_port; 559 struct vrgiu_intr_entry *ih; 560 int s; 561 562 s = splhigh(); 563 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 564 if (ih == ihe) { 565 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 566 free(ih, M_DEVBUF); 567 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 568 /* Disable interrupt */ 569 #ifdef WINCE_DEFAULT_SETTING 570 #warning WINCE_DEFAULT_SETTING 571 #else 572 sc->sc_intr_mask &= ~(1<<port); 573 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 574 #endif 575 } 576 splx(s); 577 return; 578 } 579 } 580 panic("vrgiu_intr_disetablish: no such a handle."); 581 /* NOTREACHED */ 582 } 583 584 int 585 vrgiu_intr(arg) 586 void *arg; 587 { 588 #ifdef DUMP_GIU_LEVEL2_INTR 589 #warning DUMP_GIU_LEVEL2_INTR 590 static u_int32_t oreg; 591 #endif 592 struct vrgiu_softc *sc = arg; 593 int i; 594 u_int32_t reg; 595 /* Get Level 2 interrupt status */ 596 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 597 #ifdef DUMP_GIU_LEVEL2_INTR 598 #warning DUMP_GIU_LEVEL2_INTR 599 { 600 u_int32_t uedge, dedge, j; 601 for (j = 0x80000000; j > 0; j >>=1) 602 printf ("%c" , reg&j ? '|' : '.'); 603 uedge = (reg ^ oreg) & reg; 604 dedge = (reg ^ oreg) & ~reg; 605 if (uedge || dedge) { 606 for (j = 0; j < 32; j++) { 607 if (uedge & (1 << j)) 608 printf ("+%d", j); 609 else if (dedge & (1 << j)) 610 printf ("-%d", j); 611 } 612 } 613 oreg = reg; 614 printf ("\n"); 615 } 616 #endif 617 /* Clear interrupt */ 618 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 619 620 /* Dispatch handler */ 621 for (i = 0; i < MAX_GPIO_INOUT; i++) { 622 if (reg & (1 << i)) { 623 register struct vrgiu_intr_entry *ih; 624 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 625 ih->ih_fun(ih->ih_arg); 626 } 627 } 628 } 629 630 return 0; 631 } 632
Indexes created Sun Sep 28 07:09:56 GMT 2025