vrgiu.c revision 1.16
1 /* $NetBSD: vrgiu.c,v 1.16 2000/10/03 03:16:16 sato Exp $ */ 2 /*- 3 * Copyright (c) 1999 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/reboot.h> 42 43 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 44 45 #include <mips/cpuregs.h> 46 #include <machine/bus.h> 47 #include <machine/config_hook.h> 48 49 #include <hpcmips/vr/vripreg.h> 50 #include <hpcmips/vr/vripvar.h> 51 #include <hpcmips/vr/vrgiureg.h> 52 53 #include "locators.h" 54 55 #define VRGIUDEBUG 56 #ifdef VRGIUDEBUG 57 #define DEBUG_IO 1 58 #define DEBUG_INTR 2 59 #ifndef VRGIUDEBUG_CONF 60 #define VRGIUDEBUG_CONF 0 61 #endif /* VRGIUDEBUG_CONF */ 62 int vrgiu_debug = VRGIUDEBUG_CONF; 63 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 64 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 65 #define DDUMP_IOSETTING(flag, sc) \ 66 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 67 #define VPRINTF(flag, arg) \ 68 if (bootverbose || vrgiu_debug & flag) printf arg; 69 #define VDUMP_IO(flag, sc) \ 70 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 71 #define VDUMP_IOSETTING(flag, sc) \ 72 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 73 #else 74 #define DPRINTF(flag, arg) 75 #define DDUMP_IO(flag, sc) 76 #define DDUMP_IOSETTING(flag, sc) 77 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 78 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 79 #define VDUMP_IOSETTING(flag, sc) \ 80 if (bootverbose) vrgiu_dump_iosetting(sc); 81 #endif 82 83 #ifdef VRGIU_INTR_NOLED 84 int vrgiu_intr_led = 0; 85 #else /* VRGIU_INTR_NOLED */ 86 int vrgiu_intr_led = 1; 87 #endif /* VRGIU_INTR_NOLED */ 88 89 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 90 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 91 92 int vrgiu_match __P((struct device*, struct cfdata*, void*)); 93 void vrgiu_attach __P((struct device*, struct device*, void*)); 94 int vrgiu_intr __P((void*)); 95 int vrgiu_print __P((void*, const char*)); 96 void vrgiu_callback __P((struct device*)); 97 98 void vrgiu_dump_regs __P((struct vrgiu_softc *sc)); 99 void vrgiu_dump_io __P((struct vrgiu_softc *sc)); 100 void vrgiu_diff_io __P((void)); 101 void vrgiu_dump_iosetting __P((struct vrgiu_softc *sc)); 102 void vrgiu_diff_iosetting __P((void)); 103 u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t)); 104 u_int16_t vrgiu_regread __P((vrgiu_chipset_tag_t, bus_addr_t)); 105 void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t)); 106 void vrgiu_regwrite __P((vrgiu_chipset_tag_t, bus_addr_t, u_int16_t)); 107 108 int vrgiu_port_read __P((vrgiu_chipset_tag_t, int)); 109 int vrgiu_port_write __P((vrgiu_chipset_tag_t, int, int)); 110 111 void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*)); 112 void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*)); 113 114 struct vrgiu_function_tag vrgiu_functions = { 115 vrgiu_port_read, 116 vrgiu_port_write, 117 vrgiu_regread_4, 118 vrgiu_regwrite_4, 119 vrgiu_intr_establish, 120 vrgiu_intr_disestablish 121 }; 122 123 struct cfattach vrgiu_ca = { 124 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 125 }; 126 127 struct vrgiu_softc *this_giu; 128 129 int 130 vrgiu_match(parent, cf, aux) 131 struct device *parent; 132 struct cfdata *cf; 133 void *aux; 134 { 135 return 2; /* 1st attach group of vrip */ 136 } 137 138 void 139 vrgiu_attach(parent, self, aux) 140 struct device *parent; 141 struct device *self; 142 void *aux; 143 { 144 struct vrip_attach_args *va = aux; 145 struct vrgiu_softc *sc = (void*)self; 146 struct gpbus_attach_args gpa; 147 int i; 148 149 this_giu = sc; 150 sc->sc_vc = va->va_vc; 151 sc->sc_iot = va->va_iot; 152 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 153 0 /* no cache */, &sc->sc_ioh); 154 /* 155 * Disable all interrupts. 156 */ 157 sc->sc_intr_mask = 0; 158 printf("\n"); 159 #ifdef WINCE_DEFAULT_SETTING 160 #warning WINCE_DEFAULT_SETTING 161 #else 162 VPRINTF(DEBUG_IO, ("WIN setting: ")); 163 VDUMP_IOSETTING(DEBUG_IO, sc); 164 VPRINTF(DEBUG_IO, ("\n")); 165 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 166 #endif 167 168 for (i = 0; i < MAX_GPIO_INOUT; i++) 169 TAILQ_INIT(&sc->sc_intr_head[i]); 170 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 171 vrgiu_intr, sc))) { 172 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 173 return; 174 } 175 vrgiu_functions.gf_intr_establish = vrgiu_intr_establish; 176 vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish; 177 /* 178 * Register functions to upper interface. 179 */ 180 vrip_giu_function_register(va->va_vc, &vrgiu_functions, self); 181 182 /* Display port status (Input/Output) for debugging */ 183 VPRINTF(DEBUG_IO, ("I/O setting: ")); 184 DDUMP_IOSETTING(DEBUG_IO, sc); 185 VPRINTF(DEBUG_IO, ("\n")); 186 VPRINTF(DEBUG_IO, (" data:")); 187 VDUMP_IO(DEBUG_IO, sc); 188 189 /* 190 * General purpose bus 191 */ 192 gpa.gpa_busname = "gpbus"; 193 gpa.gpa_gc = sc; 194 gpa.gpa_gf = &vrgiu_functions; 195 while (config_found(self, &gpa, vrgiu_print)) ; 196 /* 197 * GIU-ISA bridge 198 */ 199 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 200 config_defer(self, vrgiu_callback); 201 #else 202 vrgiu_callback(self); 203 #endif 204 } 205 206 void 207 vrgiu_callback(self) 208 struct device *self; 209 { 210 struct vrgiu_softc *sc = (void*)self; 211 struct gpbus_attach_args gpa; 212 213 gpa.gpa_busname = "vrisab"; 214 gpa.gpa_gc = sc; 215 gpa.gpa_gf = &vrgiu_functions; 216 config_found(self, &gpa, vrgiu_print); 217 } 218 219 int 220 vrgiu_print(aux, pnp) 221 void *aux; 222 const char *pnp; 223 { 224 if (pnp) 225 return (QUIET); 226 return (UNCONF); 227 } 228 229 void 230 vrgiu_dump_iosetting(sc) 231 struct vrgiu_softc *sc; 232 { 233 long iosel, inten, useupdn, termupdn; 234 u_int32_t m; 235 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 236 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 237 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 238 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 239 for (m = 0x80000000; m; m >>=1) 240 printf ("%c" , (useupdn&m) ? 241 ((termupdn&m) ? 'U' : 'D') : 242 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 243 } 244 245 void 246 vrgiu_diff_iosetting() 247 { 248 struct vrgiu_softc *sc = this_giu; 249 static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0; 250 long iosel, inten, useupdn, termupdn; 251 u_int32_t m; 252 253 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 254 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 255 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 256 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 257 if (oiosel != iosel || ointen != inten || 258 ouseupdn != useupdn || otermupdn != termupdn) { 259 for (m = 0x80000000; m; m >>=1) 260 printf ("%c" , (useupdn&m) ? 261 ((termupdn&m) ? 'U' : 'D') : 262 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 263 } 264 oiosel = iosel; 265 ointen = inten; 266 ouseupdn = useupdn; 267 otermupdn = termupdn; 268 } 269 270 void 271 vrgiu_dump_io(sc) 272 struct vrgiu_softc *sc; 273 { 274 u_int32_t preg[2]; 275 276 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 277 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 278 279 bitdisp64(preg); 280 } 281 282 void 283 vrgiu_diff_io() 284 { 285 struct vrgiu_softc *sc = this_giu; 286 static u_int32_t opreg[2] = {0, 0}; 287 u_int32_t preg[2]; 288 289 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 290 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 291 292 if (opreg[0] != preg[0] || opreg[1] != preg[1]) { 293 printf("giu data: "); 294 bitdisp64(preg); 295 } 296 opreg[0] = preg[0]; 297 opreg[1] = preg[1]; 298 } 299 300 void 301 vrgiu_dump_regs(sc) 302 struct vrgiu_softc *sc; 303 { 304 if (sc == NULL) { 305 panic("%s(%d): VRGIU device not initialized\n", 306 __FILE__, __LINE__); 307 } 308 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 309 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 310 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 311 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 312 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 313 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 314 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 315 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 316 } 317 /* 318 * GIU regster access method. 319 */ 320 u_int32_t 321 vrgiu_regread_4(vc, offs) 322 vrgiu_chipset_tag_t vc; 323 bus_addr_t offs; 324 { 325 struct vrgiu_softc *sc = (void*)vc; 326 u_int16_t reg[2]; 327 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 328 return reg[0]|(reg[1]<<16); 329 } 330 331 u_int16_t 332 vrgiu_regread(vc, off) 333 vrgiu_chipset_tag_t vc; 334 bus_addr_t off; 335 { 336 struct vrgiu_softc *sc = (void*)vc; 337 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 338 } 339 340 void 341 vrgiu_regwrite_4(vc, offs, data) 342 vrgiu_chipset_tag_t vc; 343 bus_addr_t offs; 344 u_int32_t data; 345 { 346 struct vrgiu_softc *sc = (void*)vc; 347 348 u_int16_t reg[2]; 349 reg[0] = data & 0xffff; 350 reg[1] = (data>>16)&0xffff; 351 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 352 } 353 354 void 355 vrgiu_regwrite(vc, off, data) 356 vrgiu_chipset_tag_t vc; 357 bus_addr_t off; 358 u_int16_t data; 359 { 360 struct vrgiu_softc *sc = (void*)vc; 361 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 362 } 363 364 /* 365 * PORT 366 */ 367 int 368 vrgiu_port_read(vc, port) 369 vrgiu_chipset_tag_t vc; 370 int port; 371 { 372 int on; 373 374 if (!LEGAL_OUT_PORT(port)) 375 panic("vrgiu_port_read: illegal gpio port"); 376 377 if (port < 32) 378 on = (vrgiu_regread_4(vc, GIUPIOD_REG) & (1 << port)); 379 else 380 on = (vrgiu_regread_4(vc, GIUPODAT_REG) & (1 << (port - 32))); 381 382 return (on ? 1 : 0); 383 } 384 385 int 386 vrgiu_port_write(vc, port, onoff) 387 vrgiu_chipset_tag_t vc; 388 int port; 389 int onoff; 390 { 391 u_int32_t reg[2]; 392 int bank; 393 394 if (!LEGAL_OUT_PORT(port)) 395 panic("vrgiu_port_write: illegal gpio port"); 396 397 reg[0] = vrgiu_regread_4(vc, GIUPIOD_REG); 398 reg[1] = vrgiu_regread_4(vc, GIUPODAT_REG); 399 bank = port < 32 ? 0 : 1; 400 if (bank == 1) 401 port -= 32; 402 403 if (onoff) 404 reg[bank] |= (1<<port); 405 else 406 reg[bank] &= ~(1<<port); 407 vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]); 408 vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]); 409 410 return 0; 411 } 412 /* 413 * For before autoconfiguration. 414 */ 415 void 416 __vrgiu_out(port, data) 417 int port; 418 int data; 419 { 420 u_int16_t reg; 421 u_int32_t addr; 422 int offs; 423 424 if (!LEGAL_OUT_PORT(port)) 425 panic("__vrgiu_out: illegal gpio port"); 426 if (port < 16) { 427 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 428 offs = port; 429 } else if (port < 32) { 430 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 431 offs = port - 16; 432 } else if (port < 48) { 433 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 434 offs = port - 32; 435 } else { 436 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 437 offs = port - 48; 438 panic ("__vrgiu_out: not coded yet."); 439 } 440 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 441 442 wbflush(); 443 reg = *((volatile u_int16_t*)addr); 444 if (data) { 445 reg |= (1 << offs); 446 } else { 447 reg &= ~(1 << offs); 448 } 449 *((volatile u_int16_t*)addr) = reg; 450 wbflush(); 451 } 452 /* 453 * Interrupt staff 454 */ 455 void * 456 vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg) 457 vrgiu_chipset_tag_t ic; 458 int port; /* GPIO pin # */ 459 int mode; /* GIU trigger setting */ 460 int level; /* XXX not yet */ 461 int (*ih_fun) __P((void*)); 462 void *ih_arg; 463 { 464 struct vrgiu_softc *sc = (void*)ic; 465 int s; 466 u_int32_t reg, mask; 467 struct vrgiu_intr_entry *ih; 468 469 if (!LEGAL_INTR_PORT(port)) 470 panic ("vrgiu_intr_establish: bogus interrupt line."); 471 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 472 panic ("vrgiu_intr_establish: bogus interrupt type."); 473 else 474 sc->sc_intr_mode[port] = mode; 475 mask = (1 << port); 476 477 s = splhigh(); 478 479 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 480 panic ("vrgiu_intr_establish: no memory."); 481 482 ih->ih_port = port; 483 ih->ih_fun = ih_fun; 484 ih->ih_arg = ih_arg; 485 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 486 #ifdef WINCE_DEFAULT_SETTING 487 #warning WINCE_DEFAULT_SETTING 488 #else 489 /* 490 * Setup registers 491 */ 492 /* Input mode */ 493 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 494 reg &= ~mask; 495 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 496 497 /* interrupt type */ 498 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 499 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 500 if (mode & VRGIU_INTR_EDGE) { 501 DPRINTF(DEBUG_INTR, ("edge]")); 502 reg |= mask; /* edge */ 503 } else { 504 DPRINTF(DEBUG_INTR, ("level]")); 505 reg &= ~mask; /* level */ 506 } 507 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 508 509 /* interrupt level */ 510 if (!(mode & VRGIU_INTR_EDGE)) { 511 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 512 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 513 if (mode & VRGIU_INTR_HIGH) { 514 DPRINTF(DEBUG_INTR, ("high]")); 515 reg |= mask; /* high */ 516 } else { 517 DPRINTF(DEBUG_INTR, ("low]")); 518 reg &= ~mask; /* low */ 519 } 520 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 521 } 522 /* hold or through */ 523 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 524 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 525 if (mode & VRGIU_INTR_HOLD) { 526 DPRINTF(DEBUG_INTR, ("hold]")); 527 reg |= mask; /* hold */ 528 } else { 529 DPRINTF(DEBUG_INTR, ("through]")); 530 reg &= ~mask; /* through */ 531 } 532 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 533 #endif 534 /* 535 * clear interrupt status 536 */ 537 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 538 reg &= ~mask; 539 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 540 /* 541 * enable interrupt 542 */ 543 #ifdef WINCE_DEFAULT_SETTING 544 #warning WINCE_DEFAULT_SETTING 545 #else 546 sc->sc_intr_mask |= mask; 547 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 548 /* Unmask GIU level 2 mask register */ 549 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 550 #endif 551 splx(s); 552 553 DPRINTF(DEBUG_INTR, ("\n")); 554 555 return ih; 556 } 557 558 void 559 vrgiu_intr_disestablish(ic, arg) 560 vrgiu_chipset_tag_t ic; 561 void *arg; 562 { 563 struct vrgiu_intr_entry *ihe = arg; 564 struct vrgiu_softc *sc = (void*)ic; 565 int port = ihe->ih_port; 566 struct vrgiu_intr_entry *ih; 567 int s; 568 569 s = splhigh(); 570 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 571 if (ih == ihe) { 572 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 573 free(ih, M_DEVBUF); 574 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 575 /* Disable interrupt */ 576 #ifdef WINCE_DEFAULT_SETTING 577 #warning WINCE_DEFAULT_SETTING 578 #else 579 sc->sc_intr_mask &= ~(1<<port); 580 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 581 #endif 582 } 583 splx(s); 584 return; 585 } 586 } 587 panic("vrgiu_intr_disetablish: no such a handle."); 588 /* NOTREACHED */ 589 } 590 591 int 592 vrgiu_intr(arg) 593 void *arg; 594 { 595 #ifdef DUMP_GIU_LEVEL2_INTR 596 #warning DUMP_GIU_LEVEL2_INTR 597 static u_int32_t oreg; 598 #endif 599 struct vrgiu_softc *sc = arg; 600 int i; 601 u_int32_t reg; 602 /* Get Level 2 interrupt status */ 603 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 604 #ifdef DUMP_GIU_LEVEL2_INTR 605 #warning DUMP_GIU_LEVEL2_INTR 606 { 607 u_int32_t uedge, dedge, j; 608 for (j = 0x80000000; j > 0; j >>=1) 609 printf ("%c" , reg&j ? '|' : '.'); 610 uedge = (reg ^ oreg) & reg; 611 dedge = (reg ^ oreg) & ~reg; 612 if (uedge || dedge) { 613 for (j = 0; j < 32; j++) { 614 if (uedge & (1 << j)) 615 printf ("+%d", j); 616 else if (dedge & (1 << j)) 617 printf ("-%d", j); 618 } 619 } 620 oreg = reg; 621 printf ("\n"); 622 } 623 #endif 624 /* Clear interrupt */ 625 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 626 627 /* Dispatch handler */ 628 for (i = 0; i < MAX_GPIO_INOUT; i++) { 629 if (reg & (1 << i)) { 630 register struct vrgiu_intr_entry *ih; 631 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 632 ih->ih_fun(ih->ih_arg); 633 } 634 } 635 } 636 637 if (vrgiu_intr_led) 638 config_hook_call(CONFIG_HOOK_POWERCONTROL, 639 CONFIG_HOOK_POWERCONTROL_LED, 640 PWCTL_LED_FLASH); 641 return 0; 642 } 643
Indexes created Mon Sep 29 03:10:08 GMT 2025