vrgiu.c revision 1.2
1 /* $NetBSD: vrgiu.c,v 1.2 1999/11/07 14:07:50 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/queue.h> 42 #define TAILQ_FOREACH(var, head, field) \ 43 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 44 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 45 46 #include <mips/cpuregs.h> 47 #include <machine/bus.h> 48 49 #include <hpcmips/vr/vripreg.h> 50 #include <hpcmips/vr/vripvar.h> 51 #include <hpcmips/vr/vrgiureg.h> 52 53 #include "locators.h" 54 55 #ifdef VRGIUDEBUG 56 int vrgiu_debug = 1; 57 #define DPRINTF(arg) if (vrgiu_debug) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #endif 61 62 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 63 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 64 65 int vrgiu_match __P((struct device*, struct cfdata*, void*)); 66 void vrgiu_attach __P((struct device*, struct device*, void*)); 67 int vrgiu_intr __P((void*)); 68 int vrgiu_print __P((void*, const char*)); 69 void vrgiu_callback __P((struct device*)); 70 71 void vrgiu_dump_regs(struct vrgiu_softc *sc); 72 u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t)); 73 void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t)); 74 75 int vrgiu_port_register __P((vrgiu_chipset_tag_t, enum gpio_name, int)); 76 int vrgiu_port_read __P((vrgiu_chipset_tag_t, vrgiu_gpioreg_t*)); 77 int vrgiu_port_write __P((vrgiu_chipset_tag_t, enum gpio_name, int)); 78 79 void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*)); 80 void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*)); 81 82 struct vrgiu_function_tag vrgiu_functions = { 83 vrgiu_port_register, 84 vrgiu_port_read, 85 vrgiu_port_write, 86 vrgiu_regread_4, 87 vrgiu_regwrite_4, 88 vrgiu_intr_establish, 89 vrgiu_intr_disestablish 90 }; 91 92 struct cfattach vrgiu_ca = { 93 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 94 }; 95 96 int 97 vrgiu_match(parent, cf, aux) 98 struct device *parent; 99 struct cfdata *cf; 100 void *aux; 101 { 102 return 2; /* 1st attach group of vrip */ 103 } 104 105 void 106 vrgiu_attach(parent, self, aux) 107 struct device *parent; 108 struct device *self; 109 void *aux; 110 { 111 struct vrip_attach_args *va = aux; 112 struct vrgiu_softc *sc = (void*)self; 113 struct gpbus_attach_args gpa; 114 int i; 115 116 sc->sc_vc = va->va_vc; 117 sc->sc_iot = va->va_iot; 118 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 119 0 /* no cache */, &sc->sc_ioh); 120 /* 121 * Disable all interrupts. 122 */ 123 sc->sc_intr_mask = 0; 124 #ifdef WINCE_DEFAULT_SETTING 125 #warning WINCE_DEFAULT_SETTING 126 #else 127 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 128 #endif 129 130 for (i = 0; i < MAX_GPIO_INOUT; i++) 131 TAILQ_INIT(&sc->sc_intr_head[i]); 132 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 133 vrgiu_intr, sc))) { 134 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 135 return; 136 } 137 vrgiu_functions.gf_intr_establish = vrgiu_intr_establish; 138 vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish; 139 /* 140 * Register functions to upper interface. 141 */ 142 vrip_giu_function_register(va->va_vc, &vrgiu_functions, self); 143 /* Display port status (Input/Output) for debugging */ 144 { 145 vrgiu_gpioreg_t preg; 146 vrgiu_port_read(sc, &preg); 147 printf("Output-port:"); 148 bitdisp64(preg); 149 } 150 /* 151 * General purpose bus 152 */ 153 for (i = 0; i< MAX_GPIO_INOUT; i++) 154 sc->sc_gpio_map[i] = GIUPORT_NOTDEF; 155 gpa.gpa_busname = "gpbus"; 156 gpa.gpa_gc = sc; 157 gpa.gpa_gf = &vrgiu_functions; 158 config_found(self, &gpa, vrgiu_print); 159 /* 160 * GIU-ISA bridge 161 */ 162 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 163 config_defer(self, vrgiu_callback); 164 #else 165 vrgiu_callback(self); 166 #endif 167 } 168 169 void 170 vrgiu_callback(self) 171 struct device *self; 172 { 173 struct vrgiu_softc *sc = (void*)self; 174 struct gpbus_attach_args gpa; 175 176 gpa.gpa_busname = "vrisab"; 177 gpa.gpa_gc = sc; 178 gpa.gpa_gf = &vrgiu_functions; 179 config_found(self, &gpa, vrgiu_print); 180 } 181 182 int 183 vrgiu_print(aux, pnp) 184 void *aux; 185 const char *pnp; 186 { 187 if (pnp) 188 return (QUIET); 189 return (UNCONF); 190 } 191 192 void 193 vrgiu_dump_regs(sc) 194 struct vrgiu_softc *sc; 195 { 196 if (sc == NULL) { 197 panic("%s(%d): VRGIU device not initialized\n", 198 __FILE__, __LINE__); 199 } 200 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 201 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 202 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 203 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 204 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 205 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 206 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 207 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 208 } 209 /* 210 * GIU regster access method. 211 */ 212 u_int32_t 213 vrgiu_regread_4(vc, offs) 214 vrgiu_chipset_tag_t vc; 215 bus_addr_t offs; 216 { 217 struct vrgiu_softc *sc = (void*)vc; 218 u_int16_t reg[2]; 219 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 220 return reg[0]|(reg[1]<<16); 221 } 222 223 void 224 vrgiu_regwrite_4(vc, offs, data) 225 vrgiu_chipset_tag_t vc; 226 bus_addr_t offs; 227 u_int32_t data; 228 { 229 struct vrgiu_softc *sc = (void*)vc; 230 231 u_int16_t reg[2]; 232 reg[0] = data & 0xffff; 233 reg[1] = (data>>16)&0xffff; 234 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 235 } 236 /* 237 * Assign Platform independent port name to GPIO # map. 238 */ 239 int 240 vrgiu_port_register(ic, gpio, port) 241 vrgiu_chipset_tag_t ic; 242 enum gpio_name gpio; 243 int port; 244 { 245 struct vrgiu_softc *sc = (void*)ic; 246 if (sc->sc_gpio_map[gpio] != GIUPORT_NOTDEF) 247 panic("vrgiu_port_register: already defined port."); 248 sc->sc_gpio_map[gpio] = port; 249 return 0; 250 } 251 /* 252 * PORT 253 */ 254 int 255 vrgiu_port_read(vc, reg) 256 vrgiu_chipset_tag_t vc; 257 vrgiu_gpioreg_t *reg; 258 { 259 (*reg)[0] = vrgiu_regread_4(vc, GIUPIOD_REG); 260 (*reg)[1] = vrgiu_regread_4(vc, GIUPODAT_REG); 261 return 0; 262 } 263 264 int 265 vrgiu_port_write(vc, gpio, onoff) 266 vrgiu_chipset_tag_t vc; 267 enum gpio_name gpio; 268 int onoff; 269 { 270 struct vrgiu_softc *sc = (void*)vc; 271 vrgiu_gpioreg_t reg; 272 int port, bank; 273 274 if (!LEGAL_OUT_PORT(gpio)) 275 panic("vrgiu_port_write: illegal gpio name"); 276 if ((port = sc->sc_gpio_map[gpio]) == GIUPORT_NOTDEF) { 277 printf ("vrgiu_port_write: not defined port name%d\n", gpio); 278 return 0; 279 } 280 if (!LEGAL_OUT_PORT(port)) 281 panic("vrgiu_port_write: illegal gpio port"); 282 283 vrgiu_port_read(vc, ®); 284 bank = port < 32 ? 0 : 1; 285 if (bank == 1) 286 port -= 32; 287 288 if (onoff) 289 reg[bank] |= (1<<port); 290 else 291 reg[bank] &= ~(1<<port); 292 vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]); 293 vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]); 294 295 return 0; 296 } 297 /* 298 * For before autoconfiguration. 299 */ 300 void 301 __vrgiu_out(port, data) 302 int port; 303 int data; 304 { 305 u_int16_t reg; 306 u_int32_t addr; 307 int offs; 308 309 if (!LEGAL_OUT_PORT(port)) 310 panic("__vrgiu_out: illegal gpio port"); 311 if (port < 16) { 312 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 313 offs = port; 314 } else if (port < 32) { 315 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 316 offs = port - 16; 317 } else if (port < 48) { 318 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 319 offs = port - 32; 320 } else { 321 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 322 offs = port - 48; 323 panic ("__vrgiu_out: not coded yet."); 324 } 325 printf ("__vrgiu_out: addr %08x bit %d\n", addr, offs); 326 327 wbflush(); 328 reg = *((volatile u_int16_t*)addr); 329 if (data) { 330 reg |= (1 << offs); 331 } else { 332 reg &= ~(1 << offs); 333 } 334 *((volatile u_int16_t*)addr) = reg; 335 wbflush(); 336 } 337 /* 338 * Interrupt staff 339 */ 340 void * 341 vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg) 342 vrgiu_chipset_tag_t ic; 343 int port; /* GPIO pin # */ 344 int mode; /* GIU trigger setting */ 345 int level; /* XXX not yet */ 346 int (*ih_fun) __P((void*)); 347 void *ih_arg; 348 { 349 struct vrgiu_softc *sc = (void*)ic; 350 int s; 351 u_int32_t reg, mask; 352 struct vrgiu_intr_entry *ih; 353 354 if (!LEGAL_INTR_PORT(port)) 355 panic ("vrgiu_intr_establish: bogus interrupt line."); 356 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 357 panic ("vrgiu_intr_establish: bogus interrupt type."); 358 else 359 sc->sc_intr_mode[port] = mode; 360 mask = (1 << port); 361 362 s = splhigh(); 363 364 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 365 panic ("vrgiu_intr_establish: no memory."); 366 367 ih->ih_port = port; 368 ih->ih_fun = ih_fun; 369 ih->ih_arg = ih_arg; 370 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 371 #ifdef WINCE_DEFAULT_SETTING 372 #warning WINCE_DEFAULT_SETTING 373 #else 374 /* 375 * Setup registers 376 */ 377 /* Input mode */ 378 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 379 reg &= ~mask; 380 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 381 382 /* interrupt type */ 383 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 384 DPRINTF(("[%s->",reg & mask ? "edge" : "level")); 385 if (mode & VRGIU_INTR_EDGE) { 386 DPRINTF(("edge]")); 387 reg |= mask; /* edge */ 388 } else { 389 DPRINTF(("level]")); 390 reg &= ~mask; /* level */ 391 } 392 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 393 394 /* interrupt level */ 395 if (!(mode & VRGIU_INTR_EDGE)) { 396 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 397 DPRINTF(("[%s->",reg & mask ? "high" : "low")); 398 if (mode & VRGIU_INTR_HIGH) { 399 DPRINTF(("high]")); 400 reg |= mask; /* high */ 401 } else { 402 DPRINTF(("low]")); 403 reg &= ~mask; /* low */ 404 } 405 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 406 } 407 /* hold or through */ 408 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 409 DPRINTF(("[%s->",reg & mask ? "hold" : "through")); 410 if (mode & VRGIU_INTR_HOLD) { 411 DPRINTF(("hold]")); 412 reg |= mask; /* hold */ 413 } else { 414 DPRINTF(("through]")); 415 reg &= ~mask; /* through */ 416 } 417 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 418 #endif 419 /* 420 * clear interrupt status 421 */ 422 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 423 reg &= ~mask; 424 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 425 /* 426 * enable interrupt 427 */ 428 #ifdef WINCE_DEFAULT_SETTING 429 #warning WINCE_DEFAULT_SETTING 430 #else 431 sc->sc_intr_mask |= mask; 432 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 433 /* Unmask GIU level 2 mask register */ 434 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 435 #endif 436 splx(s); 437 438 DPRINTF(("\n")); 439 #if 0 && defined VRGIUDEBUG 440 vrgiu_dump_regs(sc); 441 #endif 442 443 return ih; 444 } 445 446 void 447 vrgiu_intr_disestablish(ic, arg) 448 vrgiu_chipset_tag_t ic; 449 void *arg; 450 { 451 struct vrgiu_intr_entry *ihe = arg; 452 struct vrgiu_softc *sc = (void*)ic; 453 int port = ihe->ih_port; 454 struct vrgiu_intr_entry *ih; 455 int s; 456 457 s = splhigh(); 458 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 459 if (ih == ihe) { 460 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 461 free(ih, M_DEVBUF); 462 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 463 /* Disable interrupt */ 464 #ifdef WINCE_DEFAULT_SETTING 465 #warning WINCE_DEFAULT_SETTING 466 #else 467 sc->sc_intr_mask &= ~(1<<port); 468 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 469 #endif 470 } 471 splx(s); 472 return; 473 } 474 } 475 panic("vrgiu_intr_disetablish: no such a handle."); 476 /* NOTREACHED */ 477 } 478 479 int 480 vrgiu_intr(arg) 481 void *arg; 482 { 483 #ifdef DUMP_GIU_LEVEL2_INTR 484 #warning DUMP_GIU_LEVEL2_INTR 485 static u_int32_t oreg; 486 #endif 487 struct vrgiu_softc *sc = arg; 488 int i; 489 u_int32_t reg; 490 /* Get Level 2 interrupt status */ 491 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 492 #ifdef DUMP_GIU_LEVEL2_INTR 493 #warning DUMP_GIU_LEVEL2_INTR 494 { 495 u_int32_t uedge, dedge, j; 496 for (j = 0x80000000; j > 0; j >>=1) 497 printf ("%c" , reg&j ? '|' : '.'); 498 uedge = (reg ^ oreg) & reg; 499 dedge = (reg ^ oreg) & ~reg; 500 if (uedge || dedge) { 501 for (j = 0; j < 32; j++) { 502 if (uedge & (1 << j)) 503 printf ("+%d", j); 504 else if (dedge & (1 << j)) 505 printf ("-%d", j); 506 } 507 } 508 oreg = reg; 509 printf ("\n"); 510 } 511 #endif 512 /* Clear interrupt */ 513 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 514 515 /* Dispatch handler */ 516 for (i = 0; i < MAX_GPIO_INOUT; i++) { 517 if (reg & (1 << i)) { 518 register struct vrgiu_intr_entry *ih; 519 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 520 ih->ih_fun(ih->ih_arg); 521 } 522 } 523 } 524 525 return 0; 526 } 527
Indexes created Fri Sep 26 20:09:58 GMT 2025