vrgiu.c revision 1.23
1 /* $NetBSD: vrgiu.c,v 1.23 2001/05/09 12:00:58 shin Exp $ */ 2 /*- 3 * Copyright (c) 1999-2001 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/reboot.h> 42 43 #include <mips/cpuregs.h> 44 #include <machine/bus.h> 45 #include <machine/config_hook.h> 46 47 #include <dev/hpc/hpciovar.h> 48 49 #include "opt_vr41xx.h" 50 #include <hpcmips/vr/vrcpudef.h> 51 #include <hpcmips/vr/vripreg.h> 52 #include <hpcmips/vr/vripvar.h> 53 #include <hpcmips/vr/vrgiureg.h> 54 #include <hpcmips/vr/vrgiuvar.h> 55 56 #include "locators.h" 57 58 #define VRGIUDEBUG 59 #ifdef VRGIUDEBUG 60 #define DEBUG_IO 1 61 #define DEBUG_INTR 2 62 #ifndef VRGIUDEBUG_CONF 63 #define VRGIUDEBUG_CONF 0 64 #endif /* VRGIUDEBUG_CONF */ 65 int vrgiu_debug = VRGIUDEBUG_CONF; 66 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 67 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 68 #define DDUMP_IOSETTING(flag, sc) \ 69 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 70 #define VPRINTF(flag, arg) \ 71 if (bootverbose || vrgiu_debug & flag) printf arg; 72 #define VDUMP_IO(flag, sc) \ 73 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 74 #define VDUMP_IOSETTING(flag, sc) \ 75 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 76 #else 77 #define DPRINTF(flag, arg) 78 #define DDUMP_IO(flag, sc) 79 #define DDUMP_IOSETTING(flag, sc) 80 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 81 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 82 #define VDUMP_IOSETTING(flag, sc) \ 83 if (bootverbose) vrgiu_dump_iosetting(sc); 84 #endif 85 86 #ifdef VRGIU_INTR_NOLED 87 int vrgiu_intr_led = 0; 88 #else /* VRGIU_INTR_NOLED */ 89 int vrgiu_intr_led = 1; 90 #endif /* VRGIU_INTR_NOLED */ 91 92 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 93 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 94 95 int vrgiu_match(struct device*, struct cfdata*, void*); 96 void vrgiu_attach(struct device*, struct device*, void*); 97 int vrgiu_intr(void*); 98 int vrgiu_print(void*, const char*); 99 void vrgiu_callback(struct device*); 100 101 void vrgiu_dump_regs(struct vrgiu_softc *); 102 void vrgiu_dump_io(struct vrgiu_softc *); 103 void vrgiu_diff_io(void); 104 void vrgiu_dump_iosetting(struct vrgiu_softc *); 105 void vrgiu_diff_iosetting(void); 106 u_int32_t vrgiu_regread_4(struct vrgiu_softc *, bus_addr_t); 107 u_int16_t vrgiu_regread(struct vrgiu_softc *, bus_addr_t); 108 void vrgiu_regwrite_4(struct vrgiu_softc *, bus_addr_t, u_int32_t); 109 void vrgiu_regwrite(struct vrgiu_softc *, bus_addr_t, u_int16_t); 110 111 static int vrgiu_port_read(hpcio_chip_t, int); 112 static void vrgiu_port_write(hpcio_chip_t, int, int); 113 static void *vrgiu_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 114 static void vrgiu_intr_disestablish(hpcio_chip_t, void*); 115 static void vrgiu_intr_clear(hpcio_chip_t, void*); 116 static void vrgiu_register_iochip(hpcio_chip_t, hpcio_chip_t); 117 static void vrgiu_update(hpcio_chip_t); 118 static void vrgiu_dump(hpcio_chip_t); 119 static hpcio_chip_t vrgiu_getchip(void*, int); 120 121 static struct hpcio_chip vrgiu_iochip = { 122 .hc_portread = vrgiu_port_read, 123 .hc_portwrite = vrgiu_port_write, 124 .hc_intr_establish = vrgiu_intr_establish, 125 .hc_intr_disestablish = vrgiu_intr_disestablish, 126 .hc_intr_clear = vrgiu_intr_clear, 127 .hc_register_iochip = vrgiu_register_iochip, 128 .hc_update = vrgiu_update, 129 .hc_dump = vrgiu_dump, 130 }; 131 132 struct cfattach vrgiu_ca = { 133 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 134 }; 135 136 struct vrgiu_softc *this_giu; 137 138 int 139 vrgiu_match(parent, cf, aux) 140 struct device *parent; 141 struct cfdata *cf; 142 void *aux; 143 { 144 return 2; /* 1st attach group of vrip */ 145 } 146 147 void 148 vrgiu_attach(parent, self, aux) 149 struct device *parent; 150 struct device *self; 151 void *aux; 152 { 153 struct vrip_attach_args *va = aux; 154 struct vrgiu_softc *sc = (void*)self; 155 struct hpcio_attach_args haa; 156 int i; 157 158 this_giu = sc; 159 sc->sc_vc = va->va_vc; 160 sc->sc_iot = va->va_iot; 161 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 162 0 /* no cache */, &sc->sc_ioh); 163 /* 164 * Disable all interrupts. 165 */ 166 sc->sc_intr_mask = 0; 167 printf("\n"); 168 #ifdef WINCE_DEFAULT_SETTING 169 #warning WINCE_DEFAULT_SETTING 170 #else 171 VPRINTF(DEBUG_IO, ("WIN setting: ")); 172 VDUMP_IOSETTING(DEBUG_IO, sc); 173 VPRINTF(DEBUG_IO, ("\n")); 174 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 175 #endif 176 177 for (i = 0; i < MAX_GPIO_INOUT; i++) 178 TAILQ_INIT(&sc->sc_intr_head[i]); 179 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 180 vrgiu_intr, sc))) { 181 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 182 return; 183 } 184 /* 185 * fill hpcio_chip structure 186 */ 187 sc->sc_iochip = vrgiu_iochip; /* structure copy */ 188 sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRGIU; 189 sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 190 sc->sc_iochip.hc_sc = sc; 191 /* Register functions to upper interface */ 192 vrip_gpio_register(va->va_vc, &sc->sc_iochip); 193 194 /* Display port status (Input/Output) for debugging */ 195 VPRINTF(DEBUG_IO, ("I/O setting: ")); 196 VDUMP_IOSETTING(DEBUG_IO, sc); 197 VPRINTF(DEBUG_IO, ("\n")); 198 VPRINTF(DEBUG_IO, (" data:")); 199 VDUMP_IO(DEBUG_IO, sc); 200 201 /* 202 * hpcio I/F 203 */ 204 haa.haa_busname = HPCIO_BUSNAME; 205 haa.haa_sc = sc; 206 haa.haa_getchip = vrgiu_getchip; 207 haa.haa_iot = sc->sc_iot; 208 while (config_found(self, &haa, vrgiu_print)) ; 209 /* 210 * GIU-ISA bridge 211 */ 212 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 213 config_defer(self, vrgiu_callback); 214 #else 215 vrgiu_callback(self); 216 #endif 217 } 218 219 void 220 vrgiu_callback(self) 221 struct device *self; 222 { 223 struct vrgiu_softc *sc = (void*)self; 224 struct hpcio_attach_args haa; 225 226 haa.haa_busname = "vrisab"; 227 haa.haa_sc = sc; 228 haa.haa_getchip = vrgiu_getchip; 229 haa.haa_iot = sc->sc_iot; 230 config_found(self, &haa, vrgiu_print); 231 } 232 233 int 234 vrgiu_print(aux, pnp) 235 void *aux; 236 const char *pnp; 237 { 238 if (pnp) 239 return (QUIET); 240 return (UNCONF); 241 } 242 243 void 244 vrgiu_dump_iosetting(sc) 245 struct vrgiu_softc *sc; 246 { 247 long iosel, inten, useupdn, termupdn; 248 u_int32_t m; 249 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 250 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 251 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 252 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 253 for (m = 0x80000000; m; m >>=1) 254 printf ("%c" , (useupdn&m) ? 255 ((termupdn&m) ? 'U' : 'D') : 256 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 257 } 258 259 void 260 vrgiu_diff_iosetting() 261 { 262 struct vrgiu_softc *sc = this_giu; 263 static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0; 264 long iosel, inten, useupdn, termupdn; 265 u_int32_t m; 266 267 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 268 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 269 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 270 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 271 if (oiosel != iosel || ointen != inten || 272 ouseupdn != useupdn || otermupdn != termupdn) { 273 for (m = 0x80000000; m; m >>=1) 274 printf ("%c" , (useupdn&m) ? 275 ((termupdn&m) ? 'U' : 'D') : 276 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 277 } 278 oiosel = iosel; 279 ointen = inten; 280 ouseupdn = useupdn; 281 otermupdn = termupdn; 282 } 283 284 void 285 vrgiu_dump_io(sc) 286 struct vrgiu_softc *sc; 287 { 288 u_int32_t preg[2]; 289 290 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 291 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 292 293 bitdisp64(preg); 294 } 295 296 void 297 vrgiu_diff_io() 298 { 299 struct vrgiu_softc *sc = this_giu; 300 static u_int32_t opreg[2] = {0, 0}; 301 u_int32_t preg[2]; 302 303 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 304 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 305 306 if (opreg[0] != preg[0] || opreg[1] != preg[1]) { 307 printf("giu data: "); 308 bitdisp64(preg); 309 } 310 opreg[0] = preg[0]; 311 opreg[1] = preg[1]; 312 } 313 314 void 315 vrgiu_dump_regs(sc) 316 struct vrgiu_softc *sc; 317 { 318 if (sc == NULL) { 319 panic("%s(%d): VRGIU device not initialized\n", 320 __FILE__, __LINE__); 321 } 322 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 323 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 324 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 325 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 326 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 327 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 328 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 329 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 330 } 331 /* 332 * GIU regster access method. 333 */ 334 u_int32_t 335 vrgiu_regread_4(sc, offs) 336 struct vrgiu_softc *sc; 337 bus_addr_t offs; 338 { 339 u_int16_t reg[2]; 340 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 341 return reg[0]|(reg[1]<<16); 342 } 343 344 u_int16_t 345 vrgiu_regread(sc, off) 346 struct vrgiu_softc *sc; 347 bus_addr_t off; 348 { 349 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 350 } 351 352 void 353 vrgiu_regwrite_4(sc, offs, data) 354 struct vrgiu_softc *sc; 355 bus_addr_t offs; 356 u_int32_t data; 357 { 358 u_int16_t reg[2]; 359 reg[0] = data & 0xffff; 360 reg[1] = (data>>16)&0xffff; 361 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 362 } 363 364 void 365 vrgiu_regwrite(sc, off, data) 366 struct vrgiu_softc *sc; 367 bus_addr_t off; 368 u_int16_t data; 369 { 370 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 371 } 372 373 /* 374 * PORT 375 */ 376 int 377 vrgiu_port_read(hc, port) 378 hpcio_chip_t hc; 379 int port; 380 { 381 struct vrgiu_softc *sc = hc->hc_sc; 382 int on; 383 384 if (!LEGAL_OUT_PORT(port)) 385 panic("vrgiu_port_read: illegal gpio port"); 386 387 if (port < 32) 388 on = (vrgiu_regread_4(sc, GIUPIOD_REG) & (1 << port)); 389 else 390 on = (vrgiu_regread_4(sc, GIUPODAT_REG) & (1 << (port - 32))); 391 392 return (on ? 1 : 0); 393 } 394 395 void 396 vrgiu_port_write(hc, port, onoff) 397 hpcio_chip_t hc; 398 int port; 399 int onoff; 400 { 401 struct vrgiu_softc *sc = hc->hc_sc; 402 u_int32_t reg[2]; 403 int bank; 404 405 if (!LEGAL_OUT_PORT(port)) 406 panic("vrgiu_port_write: illegal gpio port"); 407 408 reg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 409 reg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 410 bank = port < 32 ? 0 : 1; 411 if (bank == 1) 412 port -= 32; 413 414 if (onoff) 415 reg[bank] |= (1<<port); 416 else 417 reg[bank] &= ~(1<<port); 418 vrgiu_regwrite_4(sc, GIUPIOD_REG, reg[0]); 419 vrgiu_regwrite_4(sc, GIUPODAT_REG, reg[1]); 420 } 421 422 static void 423 vrgiu_update(hc) 424 hpcio_chip_t hc; 425 { 426 } 427 428 static void 429 vrgiu_dump(hc) 430 hpcio_chip_t hc; 431 { 432 } 433 434 static hpcio_chip_t 435 vrgiu_getchip(scx, chipid) 436 void* scx; 437 int chipid; 438 { 439 struct vrgiu_softc *sc = scx; 440 441 return (&sc->sc_iochip); 442 } 443 444 /* 445 * For before autoconfiguration. 446 */ 447 void 448 __vrgiu_out(port, data) 449 int port; 450 int data; 451 { 452 u_int16_t reg; 453 u_int32_t addr; 454 int offs; 455 456 if (!LEGAL_OUT_PORT(port)) 457 panic("__vrgiu_out: illegal gpio port"); 458 if (port < 16) { 459 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 460 offs = port; 461 } else if (port < 32) { 462 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 463 offs = port - 16; 464 } else if (port < 48) { 465 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 466 offs = port - 32; 467 } else { 468 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 469 offs = port - 48; 470 panic ("__vrgiu_out: not coded yet."); 471 } 472 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 473 474 wbflush(); 475 reg = *((volatile u_int16_t*)addr); 476 if (data) { 477 reg |= (1 << offs); 478 } else { 479 reg &= ~(1 << offs); 480 } 481 *((volatile u_int16_t*)addr) = reg; 482 wbflush(); 483 } 484 /* 485 * Interrupt staff 486 */ 487 void * 488 vrgiu_intr_establish(hc, port, mode, ih_fun, ih_arg) 489 hpcio_chip_t hc; 490 int port; /* GPIO pin # */ 491 int mode; /* GIU trigger setting */ 492 int (*ih_fun) __P((void*)); 493 void *ih_arg; 494 { 495 struct vrgiu_softc *sc = hc->hc_sc; 496 int s; 497 u_int32_t reg, mask; 498 struct vrgiu_intr_entry *ih; 499 500 if (!LEGAL_INTR_PORT(port)) 501 panic ("vrgiu_intr_establish: bogus interrupt line."); 502 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 503 panic ("vrgiu_intr_establish: bogus interrupt type."); 504 else 505 sc->sc_intr_mode[port] = mode; 506 mask = (1 << port); 507 508 s = splhigh(); 509 510 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 511 panic ("vrgiu_intr_establish: no memory."); 512 513 ih->ih_port = port; 514 ih->ih_fun = ih_fun; 515 ih->ih_arg = ih_arg; 516 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 517 #ifdef WINCE_DEFAULT_SETTING 518 #warning WINCE_DEFAULT_SETTING 519 #else 520 /* 521 * Setup registers 522 */ 523 /* Input mode */ 524 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 525 reg &= ~mask; 526 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 527 528 /* interrupt type */ 529 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 530 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 531 if (mode & HPCIO_INTR_EDGE) { 532 DPRINTF(DEBUG_INTR, ("edge]")); 533 reg |= mask; /* edge */ 534 } else { 535 DPRINTF(DEBUG_INTR, ("level]")); 536 reg &= ~mask; /* level */ 537 } 538 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 539 540 /* interrupt level */ 541 if (!(mode & HPCIO_INTR_EDGE)) { 542 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 543 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 544 if (mode & HPCIO_INTR_HIGH) { 545 DPRINTF(DEBUG_INTR, ("high]")); 546 reg |= mask; /* high */ 547 } else { 548 DPRINTF(DEBUG_INTR, ("low]")); 549 reg &= ~mask; /* low */ 550 } 551 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 552 } 553 /* hold or through */ 554 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 555 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 556 if (mode & HPCIO_INTR_HOLD) { 557 DPRINTF(DEBUG_INTR, ("hold]")); 558 reg |= mask; /* hold */ 559 } else { 560 DPRINTF(DEBUG_INTR, ("through]")); 561 reg &= ~mask; /* through */ 562 } 563 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 564 #endif 565 /* 566 * clear interrupt status 567 */ 568 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 569 reg &= ~mask; 570 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 571 /* 572 * enable interrupt 573 */ 574 #ifdef WINCE_DEFAULT_SETTING 575 #warning WINCE_DEFAULT_SETTING 576 #else 577 sc->sc_intr_mask |= mask; 578 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 579 /* Unmask GIU level 2 mask register */ 580 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 581 #endif 582 splx(s); 583 584 DPRINTF(DEBUG_INTR, ("\n")); 585 586 return ih; 587 } 588 589 void 590 vrgiu_intr_disestablish(hc, arg) 591 hpcio_chip_t hc; 592 void *arg; 593 { 594 struct vrgiu_intr_entry *ihe = arg; 595 struct vrgiu_softc *sc = hc->hc_sc; 596 int port = ihe->ih_port; 597 struct vrgiu_intr_entry *ih; 598 int s; 599 600 s = splhigh(); 601 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 602 if (ih == ihe) { 603 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 604 free(ih, M_DEVBUF); 605 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 606 /* Disable interrupt */ 607 #ifdef WINCE_DEFAULT_SETTING 608 #warning WINCE_DEFAULT_SETTING 609 #else 610 sc->sc_intr_mask &= ~(1<<port); 611 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 612 #endif 613 } 614 splx(s); 615 return; 616 } 617 } 618 panic("vrgiu_intr_disetablish: no such a handle."); 619 /* NOTREACHED */ 620 } 621 622 /* Clear interrupt */ 623 void 624 vrgiu_intr_clear(hc, arg) 625 hpcio_chip_t hc; 626 void *arg; 627 { 628 struct vrgiu_softc *sc = hc->hc_sc; 629 struct vrgiu_intr_entry *ihe = arg; 630 u_int32_t reg; 631 632 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 633 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port)); 634 } 635 636 static void 637 vrgiu_register_iochip(hc, iochip) 638 hpcio_chip_t hc; 639 hpcio_chip_t iochip; 640 { 641 struct vrgiu_softc *sc = hc->hc_sc; 642 643 vrip_gpio_register(sc->sc_vc, iochip); 644 } 645 646 /* interrupt handler */ 647 int 648 vrgiu_intr(arg) 649 void *arg; 650 { 651 #ifdef DUMP_GIU_LEVEL2_INTR 652 #warning DUMP_GIU_LEVEL2_INTR 653 static u_int32_t oreg; 654 #endif 655 struct vrgiu_softc *sc = arg; 656 int i; 657 u_int32_t reg; 658 int ledvalue = CONFIG_HOOK_LED_FLASH; 659 660 /* Get Level 2 interrupt status */ 661 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 662 #ifdef DUMP_GIU_LEVEL2_INTR 663 #warning DUMP_GIU_LEVEL2_INTR 664 { 665 u_int32_t uedge, dedge, j; 666 for (j = 0x80000000; j > 0; j >>=1) 667 printf ("%c" , reg&j ? '|' : '.'); 668 uedge = (reg ^ oreg) & reg; 669 dedge = (reg ^ oreg) & ~reg; 670 if (uedge || dedge) { 671 for (j = 0; j < 32; j++) { 672 if (uedge & (1 << j)) 673 printf ("+%d", j); 674 else if (dedge & (1 << j)) 675 printf ("-%d", j); 676 } 677 } 678 oreg = reg; 679 printf ("\n"); 680 } 681 #endif 682 /* Clear interrupt */ 683 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 684 685 /* Dispatch handler */ 686 for (i = 0; i < MAX_GPIO_INOUT; i++) { 687 if (reg & (1 << i)) { 688 register struct vrgiu_intr_entry *ih; 689 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 690 ih->ih_fun(ih->ih_arg); 691 } 692 } 693 } 694 695 if (vrgiu_intr_led) 696 config_hook_call(CONFIG_HOOK_SET, 697 CONFIG_HOOK_LED, 698 (void *)&ledvalue); 699 return 0; 700 } 701
Indexes created Mon Oct 20 11:09:49 GMT 2025