vrgiu.c revision 1.24
1 /* $NetBSD: vrgiu.c,v 1.24 2001/05/18 01:41:39 enami Exp $ */ 2 /*- 3 * Copyright (c) 1999-2001 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/reboot.h> 42 43 #include <mips/cpuregs.h> 44 #include <machine/bus.h> 45 #include <machine/config_hook.h> 46 47 #include <dev/hpc/hpciovar.h> 48 49 #include "opt_vr41xx.h" 50 #include <hpcmips/vr/vrcpudef.h> 51 #include <hpcmips/vr/vripreg.h> 52 #include <hpcmips/vr/vripvar.h> 53 #include <hpcmips/vr/vrgiureg.h> 54 #include <hpcmips/vr/vrgiuvar.h> 55 56 #include "locators.h" 57 58 #define VRGIUDEBUG 59 #ifdef VRGIUDEBUG 60 #define DEBUG_IO 1 61 #define DEBUG_INTR 2 62 #ifndef VRGIUDEBUG_CONF 63 #define VRGIUDEBUG_CONF 0 64 #endif /* VRGIUDEBUG_CONF */ 65 int vrgiu_debug = VRGIUDEBUG_CONF; 66 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 67 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 68 #define DDUMP_IOSETTING(flag, sc) \ 69 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 70 #define VPRINTF(flag, arg) \ 71 if (bootverbose || vrgiu_debug & flag) printf arg; 72 #define VDUMP_IO(flag, sc) \ 73 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 74 #define VDUMP_IOSETTING(flag, sc) \ 75 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 76 #else 77 #define DPRINTF(flag, arg) 78 #define DDUMP_IO(flag, sc) 79 #define DDUMP_IOSETTING(flag, sc) 80 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 81 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 82 #define VDUMP_IOSETTING(flag, sc) \ 83 if (bootverbose) vrgiu_dump_iosetting(sc); 84 #endif 85 86 #ifdef VRGIU_INTR_NOLED 87 int vrgiu_intr_led = 0; 88 #else /* VRGIU_INTR_NOLED */ 89 int vrgiu_intr_led = 1; 90 #endif /* VRGIU_INTR_NOLED */ 91 92 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 93 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 94 95 int vrgiu_match(struct device*, struct cfdata*, void*); 96 void vrgiu_attach(struct device*, struct device*, void*); 97 int vrgiu_intr(void*); 98 int vrgiu_print(void*, const char*); 99 void vrgiu_callback(struct device*); 100 101 void vrgiu_dump_regs(struct vrgiu_softc *); 102 void vrgiu_dump_io(struct vrgiu_softc *); 103 void vrgiu_diff_io(void); 104 void vrgiu_dump_iosetting(struct vrgiu_softc *); 105 void vrgiu_diff_iosetting(void); 106 u_int32_t vrgiu_regread_4(struct vrgiu_softc *, bus_addr_t); 107 u_int16_t vrgiu_regread(struct vrgiu_softc *, bus_addr_t); 108 void vrgiu_regwrite_4(struct vrgiu_softc *, bus_addr_t, u_int32_t); 109 void vrgiu_regwrite(struct vrgiu_softc *, bus_addr_t, u_int16_t); 110 111 static int vrgiu_port_read(hpcio_chip_t, int); 112 static void vrgiu_port_write(hpcio_chip_t, int, int); 113 static void *vrgiu_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 114 static void vrgiu_intr_disestablish(hpcio_chip_t, void*); 115 static void vrgiu_intr_clear(hpcio_chip_t, void*); 116 static void vrgiu_register_iochip(hpcio_chip_t, hpcio_chip_t); 117 static void vrgiu_update(hpcio_chip_t); 118 static void vrgiu_dump(hpcio_chip_t); 119 static hpcio_chip_t vrgiu_getchip(void*, int); 120 121 static struct hpcio_chip vrgiu_iochip = { 122 .hc_portread = vrgiu_port_read, 123 .hc_portwrite = vrgiu_port_write, 124 .hc_intr_establish = vrgiu_intr_establish, 125 .hc_intr_disestablish = vrgiu_intr_disestablish, 126 .hc_intr_clear = vrgiu_intr_clear, 127 .hc_register_iochip = vrgiu_register_iochip, 128 .hc_update = vrgiu_update, 129 .hc_dump = vrgiu_dump, 130 }; 131 132 struct cfattach vrgiu_ca = { 133 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 134 }; 135 136 struct vrgiu_softc *this_giu; 137 138 int 139 vrgiu_match(parent, cf, aux) 140 struct device *parent; 141 struct cfdata *cf; 142 void *aux; 143 { 144 return 2; /* 1st attach group of vrip */ 145 } 146 147 void 148 vrgiu_attach(parent, self, aux) 149 struct device *parent; 150 struct device *self; 151 void *aux; 152 { 153 struct vrip_attach_args *va = aux; 154 struct vrgiu_softc *sc = (void*)self; 155 struct hpcio_attach_args haa; 156 int i; 157 158 this_giu = sc; 159 sc->sc_vc = va->va_vc; 160 sc->sc_iot = va->va_iot; 161 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 162 0 /* no cache */, &sc->sc_ioh); 163 /* 164 * Disable all interrupts. 165 */ 166 sc->sc_intr_mask = 0; 167 printf("\n"); 168 #ifdef WINCE_DEFAULT_SETTING 169 #warning WINCE_DEFAULT_SETTING 170 #else 171 VPRINTF(DEBUG_IO, ("WIN setting: ")); 172 VDUMP_IOSETTING(DEBUG_IO, sc); 173 VPRINTF(DEBUG_IO, ("\n")); 174 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 175 #endif 176 177 for (i = 0; i < MAX_GPIO_INOUT; i++) 178 TAILQ_INIT(&sc->sc_intr_head[i]); 179 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 180 vrgiu_intr, sc))) { 181 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 182 return; 183 } 184 /* 185 * fill hpcio_chip structure 186 */ 187 sc->sc_iochip = vrgiu_iochip; /* structure copy */ 188 sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRGIU; 189 sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 190 sc->sc_iochip.hc_sc = sc; 191 /* Register functions to upper interface */ 192 vrip_gpio_register(va->va_vc, &sc->sc_iochip); 193 194 /* Display port status (Input/Output) for debugging */ 195 VPRINTF(DEBUG_IO, ("I/O setting: ")); 196 VDUMP_IOSETTING(DEBUG_IO, sc); 197 VPRINTF(DEBUG_IO, ("\n")); 198 VPRINTF(DEBUG_IO, (" data:")); 199 VDUMP_IO(DEBUG_IO, sc); 200 201 /* 202 * hpcio I/F 203 */ 204 haa.haa_busname = HPCIO_BUSNAME; 205 haa.haa_sc = sc; 206 haa.haa_getchip = vrgiu_getchip; 207 haa.haa_iot = sc->sc_iot; 208 while (config_found(self, &haa, vrgiu_print)) ; 209 /* 210 * GIU-ISA bridge 211 */ 212 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 213 config_defer(self, vrgiu_callback); 214 #else 215 vrgiu_callback(self); 216 #endif 217 } 218 219 void 220 vrgiu_callback(self) 221 struct device *self; 222 { 223 struct vrgiu_softc *sc = (void*)self; 224 struct hpcio_attach_args haa; 225 226 haa.haa_busname = "vrisab"; 227 haa.haa_sc = sc; 228 haa.haa_getchip = vrgiu_getchip; 229 haa.haa_iot = sc->sc_iot; 230 config_found(self, &haa, vrgiu_print); 231 } 232 233 int 234 vrgiu_print(aux, pnp) 235 void *aux; 236 const char *pnp; 237 { 238 if (pnp) 239 return (QUIET); 240 return (UNCONF); 241 } 242 243 void 244 vrgiu_dump_iosetting(sc) 245 struct vrgiu_softc *sc; 246 { 247 long iosel, inten, useupdn, termupdn; 248 u_int32_t m; 249 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 250 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 251 #ifdef ONLY_VR4122 252 useupdn = termupdn = 0; 253 #else 254 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 255 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 256 #endif 257 for (m = 0x80000000; m; m >>=1) 258 printf ("%c" , (useupdn&m) ? 259 ((termupdn&m) ? 'U' : 'D') : 260 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 261 } 262 263 void 264 vrgiu_diff_iosetting() 265 { 266 struct vrgiu_softc *sc = this_giu; 267 static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0; 268 long iosel, inten, useupdn, termupdn; 269 u_int32_t m; 270 271 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 272 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 273 #ifdef ONLY_VR4122 274 useupdn = termupdn = 0; 275 #else 276 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 277 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 278 #endif 279 if (oiosel != iosel || ointen != inten || 280 ouseupdn != useupdn || otermupdn != termupdn) { 281 for (m = 0x80000000; m; m >>=1) 282 printf ("%c" , (useupdn&m) ? 283 ((termupdn&m) ? 'U' : 'D') : 284 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 285 } 286 oiosel = iosel; 287 ointen = inten; 288 ouseupdn = useupdn; 289 otermupdn = termupdn; 290 } 291 292 void 293 vrgiu_dump_io(sc) 294 struct vrgiu_softc *sc; 295 { 296 u_int32_t preg[2]; 297 298 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 299 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 300 301 bitdisp64(preg); 302 } 303 304 void 305 vrgiu_diff_io() 306 { 307 struct vrgiu_softc *sc = this_giu; 308 static u_int32_t opreg[2] = {0, 0}; 309 u_int32_t preg[2]; 310 311 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 312 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 313 314 if (opreg[0] != preg[0] || opreg[1] != preg[1]) { 315 printf("giu data: "); 316 bitdisp64(preg); 317 } 318 opreg[0] = preg[0]; 319 opreg[1] = preg[1]; 320 } 321 322 void 323 vrgiu_dump_regs(sc) 324 struct vrgiu_softc *sc; 325 { 326 if (sc == NULL) { 327 panic("%s(%d): VRGIU device not initialized\n", 328 __FILE__, __LINE__); 329 } 330 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 331 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 332 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 333 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 334 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 335 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 336 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 337 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 338 } 339 /* 340 * GIU regster access method. 341 */ 342 u_int32_t 343 vrgiu_regread_4(sc, offs) 344 struct vrgiu_softc *sc; 345 bus_addr_t offs; 346 { 347 u_int16_t reg[2]; 348 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 349 return reg[0]|(reg[1]<<16); 350 } 351 352 u_int16_t 353 vrgiu_regread(sc, off) 354 struct vrgiu_softc *sc; 355 bus_addr_t off; 356 { 357 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 358 } 359 360 void 361 vrgiu_regwrite_4(sc, offs, data) 362 struct vrgiu_softc *sc; 363 bus_addr_t offs; 364 u_int32_t data; 365 { 366 u_int16_t reg[2]; 367 reg[0] = data & 0xffff; 368 reg[1] = (data>>16)&0xffff; 369 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 370 } 371 372 void 373 vrgiu_regwrite(sc, off, data) 374 struct vrgiu_softc *sc; 375 bus_addr_t off; 376 u_int16_t data; 377 { 378 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 379 } 380 381 /* 382 * PORT 383 */ 384 int 385 vrgiu_port_read(hc, port) 386 hpcio_chip_t hc; 387 int port; 388 { 389 struct vrgiu_softc *sc = hc->hc_sc; 390 int on; 391 392 if (!LEGAL_OUT_PORT(port)) 393 panic("vrgiu_port_read: illegal gpio port"); 394 395 if (port < 32) 396 on = (vrgiu_regread_4(sc, GIUPIOD_REG) & (1 << port)); 397 else 398 on = (vrgiu_regread_4(sc, GIUPODAT_REG) & (1 << (port - 32))); 399 400 return (on ? 1 : 0); 401 } 402 403 void 404 vrgiu_port_write(hc, port, onoff) 405 hpcio_chip_t hc; 406 int port; 407 int onoff; 408 { 409 struct vrgiu_softc *sc = hc->hc_sc; 410 u_int32_t reg[2]; 411 int bank; 412 413 if (!LEGAL_OUT_PORT(port)) 414 panic("vrgiu_port_write: illegal gpio port"); 415 416 reg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 417 reg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 418 bank = port < 32 ? 0 : 1; 419 if (bank == 1) 420 port -= 32; 421 422 if (onoff) 423 reg[bank] |= (1<<port); 424 else 425 reg[bank] &= ~(1<<port); 426 vrgiu_regwrite_4(sc, GIUPIOD_REG, reg[0]); 427 vrgiu_regwrite_4(sc, GIUPODAT_REG, reg[1]); 428 } 429 430 static void 431 vrgiu_update(hc) 432 hpcio_chip_t hc; 433 { 434 } 435 436 static void 437 vrgiu_dump(hc) 438 hpcio_chip_t hc; 439 { 440 } 441 442 static hpcio_chip_t 443 vrgiu_getchip(scx, chipid) 444 void* scx; 445 int chipid; 446 { 447 struct vrgiu_softc *sc = scx; 448 449 return (&sc->sc_iochip); 450 } 451 452 /* 453 * For before autoconfiguration. 454 */ 455 void 456 __vrgiu_out(port, data) 457 int port; 458 int data; 459 { 460 u_int16_t reg; 461 u_int32_t addr; 462 int offs; 463 464 if (!LEGAL_OUT_PORT(port)) 465 panic("__vrgiu_out: illegal gpio port"); 466 if (port < 16) { 467 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 468 offs = port; 469 } else if (port < 32) { 470 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 471 offs = port - 16; 472 } else if (port < 48) { 473 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 474 offs = port - 32; 475 } else { 476 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 477 offs = port - 48; 478 panic ("__vrgiu_out: not coded yet."); 479 } 480 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 481 482 wbflush(); 483 reg = *((volatile u_int16_t*)addr); 484 if (data) { 485 reg |= (1 << offs); 486 } else { 487 reg &= ~(1 << offs); 488 } 489 *((volatile u_int16_t*)addr) = reg; 490 wbflush(); 491 } 492 /* 493 * Interrupt staff 494 */ 495 void * 496 vrgiu_intr_establish(hc, port, mode, ih_fun, ih_arg) 497 hpcio_chip_t hc; 498 int port; /* GPIO pin # */ 499 int mode; /* GIU trigger setting */ 500 int (*ih_fun) __P((void*)); 501 void *ih_arg; 502 { 503 struct vrgiu_softc *sc = hc->hc_sc; 504 int s; 505 u_int32_t reg, mask; 506 struct vrgiu_intr_entry *ih; 507 508 if (!LEGAL_INTR_PORT(port)) 509 panic ("vrgiu_intr_establish: bogus interrupt line."); 510 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 511 panic ("vrgiu_intr_establish: bogus interrupt type."); 512 else 513 sc->sc_intr_mode[port] = mode; 514 mask = (1 << port); 515 516 s = splhigh(); 517 518 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 519 panic ("vrgiu_intr_establish: no memory."); 520 521 ih->ih_port = port; 522 ih->ih_fun = ih_fun; 523 ih->ih_arg = ih_arg; 524 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 525 #ifdef WINCE_DEFAULT_SETTING 526 #warning WINCE_DEFAULT_SETTING 527 #else 528 /* 529 * Setup registers 530 */ 531 /* Input mode */ 532 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 533 reg &= ~mask; 534 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 535 536 /* interrupt type */ 537 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 538 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 539 if (mode & HPCIO_INTR_EDGE) { 540 DPRINTF(DEBUG_INTR, ("edge]")); 541 reg |= mask; /* edge */ 542 } else { 543 DPRINTF(DEBUG_INTR, ("level]")); 544 reg &= ~mask; /* level */ 545 } 546 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 547 548 /* interrupt level */ 549 if (!(mode & HPCIO_INTR_EDGE)) { 550 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 551 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 552 if (mode & HPCIO_INTR_HIGH) { 553 DPRINTF(DEBUG_INTR, ("high]")); 554 reg |= mask; /* high */ 555 } else { 556 DPRINTF(DEBUG_INTR, ("low]")); 557 reg &= ~mask; /* low */ 558 } 559 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 560 } 561 /* hold or through */ 562 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 563 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 564 if (mode & HPCIO_INTR_HOLD) { 565 DPRINTF(DEBUG_INTR, ("hold]")); 566 reg |= mask; /* hold */ 567 } else { 568 DPRINTF(DEBUG_INTR, ("through]")); 569 reg &= ~mask; /* through */ 570 } 571 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 572 #endif 573 /* 574 * clear interrupt status 575 */ 576 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 577 reg &= ~mask; 578 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 579 /* 580 * enable interrupt 581 */ 582 #ifdef WINCE_DEFAULT_SETTING 583 #warning WINCE_DEFAULT_SETTING 584 #else 585 sc->sc_intr_mask |= mask; 586 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 587 /* Unmask GIU level 2 mask register */ 588 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 589 #endif 590 splx(s); 591 592 DPRINTF(DEBUG_INTR, ("\n")); 593 594 return ih; 595 } 596 597 void 598 vrgiu_intr_disestablish(hc, arg) 599 hpcio_chip_t hc; 600 void *arg; 601 { 602 struct vrgiu_intr_entry *ihe = arg; 603 struct vrgiu_softc *sc = hc->hc_sc; 604 int port = ihe->ih_port; 605 struct vrgiu_intr_entry *ih; 606 int s; 607 608 s = splhigh(); 609 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 610 if (ih == ihe) { 611 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 612 free(ih, M_DEVBUF); 613 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 614 /* Disable interrupt */ 615 #ifdef WINCE_DEFAULT_SETTING 616 #warning WINCE_DEFAULT_SETTING 617 #else 618 sc->sc_intr_mask &= ~(1<<port); 619 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 620 #endif 621 } 622 splx(s); 623 return; 624 } 625 } 626 panic("vrgiu_intr_disetablish: no such a handle."); 627 /* NOTREACHED */ 628 } 629 630 /* Clear interrupt */ 631 void 632 vrgiu_intr_clear(hc, arg) 633 hpcio_chip_t hc; 634 void *arg; 635 { 636 struct vrgiu_softc *sc = hc->hc_sc; 637 struct vrgiu_intr_entry *ihe = arg; 638 u_int32_t reg; 639 640 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 641 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port)); 642 } 643 644 static void 645 vrgiu_register_iochip(hc, iochip) 646 hpcio_chip_t hc; 647 hpcio_chip_t iochip; 648 { 649 struct vrgiu_softc *sc = hc->hc_sc; 650 651 vrip_gpio_register(sc->sc_vc, iochip); 652 } 653 654 /* interrupt handler */ 655 int 656 vrgiu_intr(arg) 657 void *arg; 658 { 659 #ifdef DUMP_GIU_LEVEL2_INTR 660 #warning DUMP_GIU_LEVEL2_INTR 661 static u_int32_t oreg; 662 #endif 663 struct vrgiu_softc *sc = arg; 664 int i; 665 u_int32_t reg; 666 int ledvalue = CONFIG_HOOK_LED_FLASH; 667 668 /* Get Level 2 interrupt status */ 669 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 670 #ifdef DUMP_GIU_LEVEL2_INTR 671 #warning DUMP_GIU_LEVEL2_INTR 672 { 673 u_int32_t uedge, dedge, j; 674 for (j = 0x80000000; j > 0; j >>=1) 675 printf ("%c" , reg&j ? '|' : '.'); 676 uedge = (reg ^ oreg) & reg; 677 dedge = (reg ^ oreg) & ~reg; 678 if (uedge || dedge) { 679 for (j = 0; j < 32; j++) { 680 if (uedge & (1 << j)) 681 printf ("+%d", j); 682 else if (dedge & (1 << j)) 683 printf ("-%d", j); 684 } 685 } 686 oreg = reg; 687 printf ("\n"); 688 } 689 #endif 690 /* Clear interrupt */ 691 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 692 693 /* Dispatch handler */ 694 for (i = 0; i < MAX_GPIO_INOUT; i++) { 695 if (reg & (1 << i)) { 696 register struct vrgiu_intr_entry *ih; 697 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 698 ih->ih_fun(ih->ih_arg); 699 } 700 } 701 } 702 703 if (vrgiu_intr_led) 704 config_hook_call(CONFIG_HOOK_SET, 705 CONFIG_HOOK_LED, 706 (void *)&ledvalue); 707 return 0; 708 } 709
Indexes created Mon Sep 29 21:09:56 GMT 2025