vrgiu.c revision 1.27
1 /* $NetBSD: vrgiu.c,v 1.27 2001/12/16 09:58:34 takemura Exp $ */ 2 /*- 3 * Copyright (c) 1999-2001 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/reboot.h> 42 43 #include <mips/cpuregs.h> 44 #include <machine/bus.h> 45 #include <machine/config_hook.h> 46 47 #include <dev/hpc/hpciovar.h> 48 49 #include "opt_vr41xx.h" 50 #include <hpcmips/vr/vrcpudef.h> 51 #include <hpcmips/vr/vripreg.h> 52 #include <hpcmips/vr/vripvar.h> 53 #include <hpcmips/vr/vrgiureg.h> 54 #include <hpcmips/vr/vrgiuvar.h> 55 56 #include "locators.h" 57 58 /* 59 * constant and macro definitions 60 */ 61 #define VRGIUDEBUG 62 #ifdef VRGIUDEBUG 63 #define DEBUG_IO 1 64 #define DEBUG_INTR 2 65 #ifndef VRGIUDEBUG_CONF 66 #define VRGIUDEBUG_CONF 0 67 #endif /* VRGIUDEBUG_CONF */ 68 int vrgiu_debug = VRGIUDEBUG_CONF; 69 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 70 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 71 #define DDUMP_IOSETTING(flag, sc) \ 72 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 73 #define VPRINTF(flag, arg) \ 74 if (bootverbose || vrgiu_debug & flag) printf arg; 75 #define VDUMP_IO(flag, sc) \ 76 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 77 #define VDUMP_IOSETTING(flag, sc) \ 78 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 79 #else 80 #define DPRINTF(flag, arg) 81 #define DDUMP_IO(flag, sc) 82 #define DDUMP_IOSETTING(flag, sc) 83 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 84 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 85 #define VDUMP_IOSETTING(flag, sc) \ 86 if (bootverbose) vrgiu_dump_iosetting(sc); 87 #endif 88 89 #ifdef VRGIU_INTR_NOLED 90 int vrgiu_intr_led = 0; 91 #else /* VRGIU_INTR_NOLED */ 92 int vrgiu_intr_led = 1; 93 #endif /* VRGIU_INTR_NOLED */ 94 95 #define MAX_GPIO_OUT 50 /* port 32:49 are output only port */ 96 #define MAX_GPIO_INOUT 32 /* input/output port(0:31) */ 97 98 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 99 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 100 101 /* flags for variant chips */ 102 #if !defined(VR4122) && !defined(VR4131) 103 #define VRGIU_HAVE_PULLUPDNREGS 104 #endif 105 106 /* 107 * type declarations 108 */ 109 struct vrgiu_intr_entry { 110 int ih_port; 111 int (*ih_fun)(void *); 112 void *ih_arg; 113 TAILQ_ENTRY(vrgiu_intr_entry) ih_link; 114 }; 115 116 struct vrgiu_softc { 117 struct device sc_dev; 118 bus_space_tag_t sc_iot; 119 bus_space_handle_t sc_ioh; 120 /* Interrupt */ 121 vrip_chipset_tag_t sc_vc; 122 void *sc_ih; 123 u_int32_t sc_intr_mask; 124 u_int32_t sc_intr_mode[MAX_GPIO_INOUT]; 125 TAILQ_HEAD(, vrgiu_intr_entry) sc_intr_head[MAX_GPIO_INOUT]; 126 struct hpcio_chip sc_iochip; 127 }; 128 129 /* 130 * prototypes 131 */ 132 int vrgiu_match(struct device*, struct cfdata*, void*); 133 void vrgiu_attach(struct device*, struct device*, void*); 134 int vrgiu_intr(void*); 135 int vrgiu_print(void*, const char*); 136 void vrgiu_callback(struct device*); 137 138 void vrgiu_dump_regs(struct vrgiu_softc *); 139 void vrgiu_dump_io(struct vrgiu_softc *); 140 void vrgiu_diff_io(void); 141 void vrgiu_dump_iosetting(struct vrgiu_softc *); 142 void vrgiu_diff_iosetting(void); 143 u_int32_t vrgiu_regread_4(struct vrgiu_softc *, bus_addr_t); 144 u_int16_t vrgiu_regread(struct vrgiu_softc *, bus_addr_t); 145 void vrgiu_regwrite_4(struct vrgiu_softc *, bus_addr_t, u_int32_t); 146 void vrgiu_regwrite(struct vrgiu_softc *, bus_addr_t, u_int16_t); 147 148 static int vrgiu_port_read(hpcio_chip_t, int); 149 static void vrgiu_port_write(hpcio_chip_t, int, int); 150 static void *vrgiu_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 151 static void vrgiu_intr_disestablish(hpcio_chip_t, void*); 152 static void vrgiu_intr_clear(hpcio_chip_t, void*); 153 static void vrgiu_register_iochip(hpcio_chip_t, hpcio_chip_t); 154 static void vrgiu_update(hpcio_chip_t); 155 static void vrgiu_dump(hpcio_chip_t); 156 static hpcio_chip_t vrgiu_getchip(void*, int); 157 158 /* 159 * variables 160 */ 161 static struct hpcio_chip vrgiu_iochip = { 162 .hc_portread = vrgiu_port_read, 163 .hc_portwrite = vrgiu_port_write, 164 .hc_intr_establish = vrgiu_intr_establish, 165 .hc_intr_disestablish = vrgiu_intr_disestablish, 166 .hc_intr_clear = vrgiu_intr_clear, 167 .hc_register_iochip = vrgiu_register_iochip, 168 .hc_update = vrgiu_update, 169 .hc_dump = vrgiu_dump, 170 }; 171 172 struct cfattach vrgiu_ca = { 173 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 174 }; 175 176 struct vrgiu_softc *this_giu; 177 178 /* 179 * function bodies 180 */ 181 int 182 vrgiu_match(struct device *parent, struct cfdata *cf, void *aux) 183 { 184 185 return (2); /* 1st attach group of vrip */ 186 } 187 188 void 189 vrgiu_attach(struct device *parent, struct device *self, void *aux) 190 { 191 struct vrip_attach_args *va = aux; 192 struct vrgiu_softc *sc = (void*)self; 193 struct hpcio_attach_args haa; 194 int i; 195 196 this_giu = sc; 197 sc->sc_vc = va->va_vc; 198 sc->sc_iot = va->va_iot; 199 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 200 0 /* no cache */, &sc->sc_ioh); 201 /* 202 * Disable all interrupts. 203 */ 204 sc->sc_intr_mask = 0; 205 printf("\n"); 206 #ifdef WINCE_DEFAULT_SETTING 207 #warning WINCE_DEFAULT_SETTING 208 #else 209 VPRINTF(DEBUG_IO, ("WIN setting: ")); 210 VDUMP_IOSETTING(DEBUG_IO, sc); 211 VPRINTF(DEBUG_IO, ("\n")); 212 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 213 #endif 214 215 for (i = 0; i < MAX_GPIO_INOUT; i++) 216 TAILQ_INIT(&sc->sc_intr_head[i]); 217 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 218 vrgiu_intr, sc))) { 219 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 220 return; 221 } 222 /* 223 * fill hpcio_chip structure 224 */ 225 sc->sc_iochip = vrgiu_iochip; /* structure copy */ 226 sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRGIU; 227 sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 228 sc->sc_iochip.hc_sc = sc; 229 /* Register functions to upper interface */ 230 vrip_gpio_register(va->va_vc, &sc->sc_iochip); 231 232 /* Display port status (Input/Output) for debugging */ 233 VPRINTF(DEBUG_IO, ("I/O setting: ")); 234 VDUMP_IOSETTING(DEBUG_IO, sc); 235 VPRINTF(DEBUG_IO, ("\n")); 236 VPRINTF(DEBUG_IO, (" data:")); 237 VDUMP_IO(DEBUG_IO, sc); 238 239 /* 240 * hpcio I/F 241 */ 242 haa.haa_busname = HPCIO_BUSNAME; 243 haa.haa_sc = sc; 244 haa.haa_getchip = vrgiu_getchip; 245 haa.haa_iot = sc->sc_iot; 246 while (config_found(self, &haa, vrgiu_print)) ; 247 /* 248 * GIU-ISA bridge 249 */ 250 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 251 config_defer(self, vrgiu_callback); 252 #else 253 vrgiu_callback(self); 254 #endif 255 } 256 257 void 258 vrgiu_callback(struct device *self) 259 { 260 struct vrgiu_softc *sc = (void*)self; 261 struct hpcio_attach_args haa; 262 263 haa.haa_busname = "vrisab"; 264 haa.haa_sc = sc; 265 haa.haa_getchip = vrgiu_getchip; 266 haa.haa_iot = sc->sc_iot; 267 config_found(self, &haa, vrgiu_print); 268 } 269 270 int 271 vrgiu_print(void *aux, const char *pnp) 272 { 273 if (pnp) 274 return (QUIET); 275 return (UNCONF); 276 } 277 278 void 279 vrgiu_dump_iosetting(struct vrgiu_softc *sc) 280 { 281 long iosel, inten, useupdn, termupdn; 282 u_int32_t m; 283 284 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 285 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 286 #ifndef VRGIU_HAVE_PULLUPDNREGS 287 useupdn = termupdn = 0; 288 #else 289 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 290 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 291 #endif 292 for (m = 0x80000000; m; m >>=1) 293 printf ("%c" , (useupdn&m) ? 294 ((termupdn&m) ? 'U' : 'D') : 295 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 296 } 297 298 void 299 vrgiu_diff_iosetting() 300 { 301 struct vrgiu_softc *sc = this_giu; 302 static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0; 303 long iosel, inten, useupdn, termupdn; 304 u_int32_t m; 305 306 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 307 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 308 #ifndef VRGIU_HAVE_PULLUPDNREGS 309 useupdn = termupdn = 0; 310 #else 311 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 312 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 313 #endif 314 if (oiosel != iosel || ointen != inten || 315 ouseupdn != useupdn || otermupdn != termupdn) { 316 for (m = 0x80000000; m; m >>=1) 317 printf ("%c" , (useupdn&m) ? 318 ((termupdn&m) ? 'U' : 'D') : 319 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 320 } 321 oiosel = iosel; 322 ointen = inten; 323 ouseupdn = useupdn; 324 otermupdn = termupdn; 325 } 326 327 void 328 vrgiu_dump_io(struct vrgiu_softc *sc) 329 { 330 u_int32_t preg[2]; 331 332 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 333 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 334 335 bitdisp64(preg); 336 } 337 338 void 339 vrgiu_diff_io() 340 { 341 struct vrgiu_softc *sc = this_giu; 342 static u_int32_t opreg[2] = {0, 0}; 343 u_int32_t preg[2]; 344 345 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 346 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 347 348 if (opreg[0] != preg[0] || opreg[1] != preg[1]) { 349 printf("giu data: "); 350 bitdisp64(preg); 351 } 352 opreg[0] = preg[0]; 353 opreg[1] = preg[1]; 354 } 355 356 void 357 vrgiu_dump_regs(struct vrgiu_softc *sc) 358 { 359 360 if (sc == NULL) { 361 panic("%s(%d): VRGIU device not initialized\n", 362 __FILE__, __LINE__); 363 } 364 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 365 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 366 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 367 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 368 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 369 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 370 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 371 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 372 } 373 /* 374 * GIU regster access method. 375 */ 376 u_int32_t 377 vrgiu_regread_4(struct vrgiu_softc *sc, bus_addr_t offs) 378 { 379 u_int16_t reg[2]; 380 381 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 382 383 return (reg[0] | (reg[1] << 16)); 384 } 385 386 u_int16_t 387 vrgiu_regread(struct vrgiu_softc *sc, bus_addr_t off) 388 { 389 390 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, off)); 391 } 392 393 void 394 vrgiu_regwrite_4(struct vrgiu_softc *sc, bus_addr_t offs, u_int32_t data) 395 { 396 u_int16_t reg[2]; 397 398 reg[0] = data & 0xffff; 399 reg[1] = (data>>16)&0xffff; 400 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 401 } 402 403 void 404 vrgiu_regwrite(struct vrgiu_softc *sc, bus_addr_t off, u_int16_t data) 405 { 406 407 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 408 } 409 410 /* 411 * PORT 412 */ 413 int 414 vrgiu_port_read(hpcio_chip_t hc, int port) 415 { 416 struct vrgiu_softc *sc = hc->hc_sc; 417 int on; 418 419 if (!LEGAL_OUT_PORT(port)) 420 panic("vrgiu_port_read: illegal gpio port"); 421 422 if (port < 32) 423 on = (vrgiu_regread_4(sc, GIUPIOD_REG) & (1 << port)); 424 else 425 on = (vrgiu_regread_4(sc, GIUPODAT_REG) & (1 << (port - 32))); 426 427 return (on ? 1 : 0); 428 } 429 430 void 431 vrgiu_port_write(hpcio_chip_t hc, int port, int onoff) 432 { 433 struct vrgiu_softc *sc = hc->hc_sc; 434 u_int32_t reg[2]; 435 int bank; 436 437 if (!LEGAL_OUT_PORT(port)) 438 panic("vrgiu_port_write: illegal gpio port"); 439 440 reg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 441 reg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 442 bank = port < 32 ? 0 : 1; 443 if (bank == 1) 444 port -= 32; 445 446 if (onoff) 447 reg[bank] |= (1<<port); 448 else 449 reg[bank] &= ~(1<<port); 450 vrgiu_regwrite_4(sc, GIUPIOD_REG, reg[0]); 451 vrgiu_regwrite_4(sc, GIUPODAT_REG, reg[1]); 452 } 453 454 static void 455 vrgiu_update(hpcio_chip_t hc) 456 { 457 } 458 459 static void 460 vrgiu_dump(hpcio_chip_t hc) 461 { 462 } 463 464 static hpcio_chip_t 465 vrgiu_getchip(void* scx, int chipid) 466 { 467 struct vrgiu_softc *sc = scx; 468 469 return (&sc->sc_iochip); 470 } 471 472 /* 473 * For before autoconfiguration. 474 */ 475 void 476 __vrgiu_out(int port, int data) 477 { 478 u_int16_t reg; 479 u_int32_t addr; 480 int offs; 481 482 if (!LEGAL_OUT_PORT(port)) 483 panic("__vrgiu_out: illegal gpio port"); 484 if (port < 16) { 485 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 486 offs = port; 487 } else if (port < 32) { 488 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 489 offs = port - 16; 490 } else if (port < 48) { 491 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 492 offs = port - 32; 493 } else { 494 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 495 offs = port - 48; 496 panic ("__vrgiu_out: not coded yet."); 497 } 498 DPRINTF(DEBUG_IO, ("__vrgiu_out: addr %08x bit %d\n", addr, offs)); 499 500 wbflush(); 501 reg = *((volatile u_int16_t*)addr); 502 if (data) { 503 reg |= (1 << offs); 504 } else { 505 reg &= ~(1 << offs); 506 } 507 *((volatile u_int16_t*)addr) = reg; 508 wbflush(); 509 } 510 /* 511 * Interrupt staff 512 */ 513 void * 514 vrgiu_intr_establish( 515 hpcio_chip_t hc, 516 int port, /* GPIO pin # */ 517 int mode, /* GIU trigger setting */ 518 int (*ih_fun)(void *), 519 void *ih_arg) 520 { 521 struct vrgiu_softc *sc = hc->hc_sc; 522 int s; 523 u_int32_t reg, mask; 524 struct vrgiu_intr_entry *ih; 525 526 if (!LEGAL_INTR_PORT(port)) 527 panic ("vrgiu_intr_establish: bogus interrupt line."); 528 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 529 panic ("vrgiu_intr_establish: bogus interrupt type."); 530 else 531 sc->sc_intr_mode[port] = mode; 532 mask = (1 << port); 533 534 s = splhigh(); 535 536 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 537 panic ("vrgiu_intr_establish: no memory."); 538 539 ih->ih_port = port; 540 ih->ih_fun = ih_fun; 541 ih->ih_arg = ih_arg; 542 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 543 #ifdef WINCE_DEFAULT_SETTING 544 #warning WINCE_DEFAULT_SETTING 545 #else 546 /* 547 * Setup registers 548 */ 549 /* Input mode */ 550 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 551 reg &= ~mask; 552 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 553 554 /* interrupt type */ 555 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 556 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 557 if (mode & HPCIO_INTR_EDGE) { 558 DPRINTF(DEBUG_INTR, ("edge]")); 559 reg |= mask; /* edge */ 560 } else { 561 DPRINTF(DEBUG_INTR, ("level]")); 562 reg &= ~mask; /* level */ 563 } 564 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 565 566 /* interrupt level */ 567 if (!(mode & HPCIO_INTR_EDGE)) { 568 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 569 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 570 if (mode & HPCIO_INTR_HIGH) { 571 DPRINTF(DEBUG_INTR, ("high]")); 572 reg |= mask; /* high */ 573 } else { 574 DPRINTF(DEBUG_INTR, ("low]")); 575 reg &= ~mask; /* low */ 576 } 577 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 578 } 579 /* hold or through */ 580 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 581 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 582 if (mode & HPCIO_INTR_HOLD) { 583 DPRINTF(DEBUG_INTR, ("hold]")); 584 reg |= mask; /* hold */ 585 } else { 586 DPRINTF(DEBUG_INTR, ("through]")); 587 reg &= ~mask; /* through */ 588 } 589 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 590 #endif 591 /* 592 * clear interrupt status 593 */ 594 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 595 reg &= ~mask; 596 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 597 /* 598 * enable interrupt 599 */ 600 #ifdef WINCE_DEFAULT_SETTING 601 #warning WINCE_DEFAULT_SETTING 602 #else 603 sc->sc_intr_mask |= mask; 604 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 605 /* Unmask GIU level 2 mask register */ 606 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 607 #endif 608 splx(s); 609 610 DPRINTF(DEBUG_INTR, ("\n")); 611 612 return (ih); 613 } 614 615 void 616 vrgiu_intr_disestablish(hpcio_chip_t hc, void *arg) 617 { 618 struct vrgiu_intr_entry *ihe = arg; 619 struct vrgiu_softc *sc = hc->hc_sc; 620 int port = ihe->ih_port; 621 struct vrgiu_intr_entry *ih; 622 int s; 623 624 s = splhigh(); 625 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 626 if (ih == ihe) { 627 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 628 free(ih, M_DEVBUF); 629 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 630 /* Disable interrupt */ 631 #ifdef WINCE_DEFAULT_SETTING 632 #warning WINCE_DEFAULT_SETTING 633 #else 634 sc->sc_intr_mask &= ~(1<<port); 635 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 636 #endif 637 } 638 splx(s); 639 return; 640 } 641 } 642 panic("vrgiu_intr_disetablish: no such a handle."); 643 /* NOTREACHED */ 644 } 645 646 /* Clear interrupt */ 647 void 648 vrgiu_intr_clear(hpcio_chip_t hc, void *arg) 649 { 650 struct vrgiu_softc *sc = hc->hc_sc; 651 struct vrgiu_intr_entry *ihe = arg; 652 u_int32_t reg; 653 654 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 655 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port)); 656 } 657 658 static void 659 vrgiu_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip) 660 { 661 struct vrgiu_softc *sc = hc->hc_sc; 662 663 vrip_gpio_register(sc->sc_vc, iochip); 664 } 665 666 /* interrupt handler */ 667 int 668 vrgiu_intr(void *arg) 669 { 670 #ifdef DUMP_GIU_LEVEL2_INTR 671 #warning DUMP_GIU_LEVEL2_INTR 672 static u_int32_t oreg; 673 #endif 674 struct vrgiu_softc *sc = arg; 675 int i; 676 u_int32_t reg; 677 int ledvalue = CONFIG_HOOK_LED_FLASH; 678 679 /* Get Level 2 interrupt status */ 680 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 681 #ifdef DUMP_GIU_LEVEL2_INTR 682 #warning DUMP_GIU_LEVEL2_INTR 683 { 684 u_int32_t uedge, dedge, j; 685 for (j = 0x80000000; j > 0; j >>=1) 686 printf ("%c" , reg&j ? '|' : '.'); 687 uedge = (reg ^ oreg) & reg; 688 dedge = (reg ^ oreg) & ~reg; 689 if (uedge || dedge) { 690 for (j = 0; j < 32; j++) { 691 if (uedge & (1 << j)) 692 printf ("+%d", j); 693 else if (dedge & (1 << j)) 694 printf ("-%d", j); 695 } 696 } 697 oreg = reg; 698 printf ("\n"); 699 } 700 #endif 701 /* Clear interrupt */ 702 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 703 704 /* Dispatch handler */ 705 for (i = 0; i < MAX_GPIO_INOUT; i++) { 706 if (reg & (1 << i)) { 707 register struct vrgiu_intr_entry *ih; 708 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 709 ih->ih_fun(ih->ih_arg); 710 } 711 } 712 } 713 714 if (vrgiu_intr_led) 715 config_hook_call(CONFIG_HOOK_SET, CONFIG_HOOK_LED, 716 (void *)&ledvalue); 717 return (0); 718 } 719
Indexes created Sun Sep 28 16:09:52 GMT 2025