vrgiu.c revision 1.33
1 /* $NetBSD: vrgiu.c,v 1.33 2002/02/09 15:00:40 sato Exp $ */ 2 /*- 3 * Copyright (c) 1999-2001 4 * Shin Takemura and PocketBSD Project. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the PocketBSD project 17 * and its contributors. 18 * 4. Neither the name of the project nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/reboot.h> 42 43 #include <mips/cpuregs.h> 44 #include <machine/bus.h> 45 #include <machine/config_hook.h> 46 #include <machine/debug.h> 47 48 #include <dev/hpc/hpciovar.h> 49 50 #include "opt_vr41xx.h" 51 #include <hpcmips/vr/vrcpudef.h> 52 #include <hpcmips/vr/vripif.h> 53 #include <hpcmips/vr/vripreg.h> 54 #include <hpcmips/vr/vrgiureg.h> 55 56 #include "locators.h" 57 58 /* 59 * constant and macro definitions 60 */ 61 #define VRGIUDEBUG 62 #ifdef VRGIUDEBUG 63 #define DEBUG_IO 1 64 #define DEBUG_INTR 2 65 #ifndef VRGIUDEBUG_CONF 66 #define VRGIUDEBUG_CONF 0 67 #endif /* VRGIUDEBUG_CONF */ 68 int vrgiu_debug = VRGIUDEBUG_CONF; 69 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 70 #define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc); 71 #define DDUMP_IOSETTING(flag, sc) \ 72 if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 73 #define VPRINTF(flag, arg) \ 74 if (bootverbose || vrgiu_debug & flag) printf arg; 75 #define VDUMP_IO(flag, sc) \ 76 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc); 77 #define VDUMP_IOSETTING(flag, sc) \ 78 if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc); 79 #else 80 #define DPRINTF(flag, arg) 81 #define DDUMP_IO(flag, sc) 82 #define DDUMP_IOSETTING(flag, sc) 83 #define VPRINTF(flag, arg) if (bootverbose) printf arg; 84 #define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc); 85 #define VDUMP_IOSETTING(flag, sc) \ 86 if (bootverbose) vrgiu_dump_iosetting(sc); 87 #endif 88 89 #ifdef VRGIU_INTR_NOLED 90 int vrgiu_intr_led = 0; 91 #else /* VRGIU_INTR_NOLED */ 92 int vrgiu_intr_led = 1; 93 #endif /* VRGIU_INTR_NOLED */ 94 95 #define MAX_GPIO_OUT 50 /* port 32:49 are output only port */ 96 #define MAX_GPIO_INOUT 32 /* input/output port(0:31) */ 97 98 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 99 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 100 101 /* 102 * type declarations 103 */ 104 struct vrgiu_intr_entry { 105 int ih_port; 106 int (*ih_fun)(void *); 107 void *ih_arg; 108 TAILQ_ENTRY(vrgiu_intr_entry) ih_link; 109 }; 110 111 struct vrgiu_softc { 112 struct device sc_dev; 113 bus_space_tag_t sc_iot; 114 bus_space_handle_t sc_ioh; 115 /* Interrupt */ 116 vrip_chipset_tag_t sc_vc; 117 void *sc_ih; 118 u_int32_t sc_intr_mask; 119 u_int32_t sc_intr_mode[MAX_GPIO_INOUT]; 120 TAILQ_HEAD(, vrgiu_intr_entry) sc_intr_head[MAX_GPIO_INOUT]; 121 struct hpcio_chip sc_iochip; 122 }; 123 124 /* 125 * prototypes 126 */ 127 int vrgiu_match(struct device*, struct cfdata*, void*); 128 void vrgiu_attach(struct device*, struct device*, void*); 129 int vrgiu_intr(void*); 130 int vrgiu_print(void*, const char*); 131 void vrgiu_callback(struct device*); 132 133 void vrgiu_dump_regs(struct vrgiu_softc *); 134 void vrgiu_dump_io(struct vrgiu_softc *); 135 void vrgiu_diff_io(void); 136 void vrgiu_dump_iosetting(struct vrgiu_softc *); 137 void vrgiu_diff_iosetting(void); 138 u_int32_t vrgiu_regread_4(struct vrgiu_softc *, bus_addr_t); 139 u_int16_t vrgiu_regread(struct vrgiu_softc *, bus_addr_t); 140 void vrgiu_regwrite_4(struct vrgiu_softc *, bus_addr_t, u_int32_t); 141 void vrgiu_regwrite(struct vrgiu_softc *, bus_addr_t, u_int16_t); 142 143 static int vrgiu_port_read(hpcio_chip_t, int); 144 static void vrgiu_port_write(hpcio_chip_t, int, int); 145 static void *vrgiu_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*); 146 static void vrgiu_intr_disestablish(hpcio_chip_t, void*); 147 static void vrgiu_intr_clear(hpcio_chip_t, void*); 148 static void vrgiu_register_iochip(hpcio_chip_t, hpcio_chip_t); 149 static void vrgiu_update(hpcio_chip_t); 150 static void vrgiu_dump(hpcio_chip_t); 151 static hpcio_chip_t vrgiu_getchip(void*, int); 152 153 /* 154 * variables 155 */ 156 static struct hpcio_chip vrgiu_iochip = { 157 .hc_portread = vrgiu_port_read, 158 .hc_portwrite = vrgiu_port_write, 159 .hc_intr_establish = vrgiu_intr_establish, 160 .hc_intr_disestablish = vrgiu_intr_disestablish, 161 .hc_intr_clear = vrgiu_intr_clear, 162 .hc_register_iochip = vrgiu_register_iochip, 163 .hc_update = vrgiu_update, 164 .hc_dump = vrgiu_dump, 165 }; 166 167 struct cfattach vrgiu_ca = { 168 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 169 }; 170 171 struct vrgiu_softc *this_giu; 172 173 /* 174 * function bodies 175 */ 176 int 177 vrgiu_match(struct device *parent, struct cfdata *cf, void *aux) 178 { 179 180 return (2); /* 1st attach group of vrip */ 181 } 182 183 void 184 vrgiu_attach(struct device *parent, struct device *self, void *aux) 185 { 186 struct vrip_attach_args *va = aux; 187 struct vrgiu_softc *sc = (void*)self; 188 struct hpcio_attach_args haa; 189 int i; 190 191 this_giu = sc; 192 sc->sc_vc = va->va_vc; 193 sc->sc_iot = va->va_iot; 194 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 195 0 /* no cache */, &sc->sc_ioh); 196 /* 197 * Disable all interrupts. 198 */ 199 sc->sc_intr_mask = 0; 200 printf("\n"); 201 #ifdef WINCE_DEFAULT_SETTING 202 #warning WINCE_DEFAULT_SETTING 203 #else 204 VPRINTF(DEBUG_IO, (" " 205 " 3 2 1\n")); 206 VPRINTF(DEBUG_IO, (" " 207 "10987654321098765432109876543210\n")); 208 VPRINTF(DEBUG_IO, ("WIN setting: ")); 209 VDUMP_IOSETTING(DEBUG_IO, sc); 210 VPRINTF(DEBUG_IO, ("\n")); 211 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 212 #endif 213 214 for (i = 0; i < MAX_GPIO_INOUT; i++) 215 TAILQ_INIT(&sc->sc_intr_head[i]); 216 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_unit, 0, 217 IPL_BIO, vrgiu_intr, sc))) { 218 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 219 return; 220 } 221 /* 222 * fill hpcio_chip structure 223 */ 224 sc->sc_iochip = vrgiu_iochip; /* structure copy */ 225 sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRGIU; 226 sc->sc_iochip.hc_name = sc->sc_dev.dv_xname; 227 sc->sc_iochip.hc_sc = sc; 228 /* Register functions to upper interface */ 229 vrip_register_gpio(va->va_vc, &sc->sc_iochip); 230 231 /* Display port status (Input/Output) for debugging */ 232 VPRINTF(DEBUG_IO, ("I/O setting: ")); 233 VDUMP_IOSETTING(DEBUG_IO, sc); 234 VPRINTF(DEBUG_IO, ("\n")); 235 VPRINTF(DEBUG_IO, (" data:")); 236 VDUMP_IO(DEBUG_IO, sc); 237 238 /* 239 * hpcio I/F 240 */ 241 haa.haa_busname = HPCIO_BUSNAME; 242 haa.haa_sc = sc; 243 haa.haa_getchip = vrgiu_getchip; 244 haa.haa_iot = sc->sc_iot; 245 while (config_found(self, &haa, vrgiu_print)) ; 246 /* 247 * GIU-ISA bridge 248 */ 249 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 250 config_defer(self, vrgiu_callback); 251 #else 252 vrgiu_callback(self); 253 #endif 254 } 255 256 void 257 vrgiu_callback(struct device *self) 258 { 259 struct vrgiu_softc *sc = (void*)self; 260 struct hpcio_attach_args haa; 261 262 haa.haa_busname = "vrisab"; 263 haa.haa_sc = sc; 264 haa.haa_getchip = vrgiu_getchip; 265 haa.haa_iot = sc->sc_iot; 266 config_found(self, &haa, vrgiu_print); 267 } 268 269 int 270 vrgiu_print(void *aux, const char *pnp) 271 { 272 if (pnp) 273 return (QUIET); 274 return (UNCONF); 275 } 276 277 void 278 vrgiu_dump_iosetting(struct vrgiu_softc *sc) 279 { 280 long iosel, inten, useupdn, termupdn, edge, hold, level; 281 u_int32_t m; 282 char syms[] = "iiiiiiiilhLHeeEEoooooooooooooooo" 283 "DDDDDDDDDDDDDDDDUUUUUUUUUUUUUUUU"; 284 285 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 286 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 287 edge = vrgiu_regread_4(sc, GIUINTTYP_REG); 288 hold = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 289 level = vrgiu_regread_4(sc, GIUINTALSEL_REG); 290 291 if (GIUUSEUPDN_REG_W == GIU_NO_REG_W) 292 useupdn = 0; 293 else 294 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 295 if (GIUTERMUPDN_REG_W == GIU_NO_REG_W) 296 termupdn = 0; 297 else 298 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 299 for (m = 0x80000000; m; m >>=1) 300 printf ("%c", syms[ 301 ((useupdn&m) ? 32 : 0) + 302 ((iosel&m) ? 16 : 0) + ((termupdn&m) ? 16 : 0) + 303 ((inten&m) ? 8 : 0) + 304 ((edge&m) ? 4 : 0) + 305 ((hold&m) ? 2 : 0) + 306 ((level&m) ? 1 : 0)]); 307 } 308 309 void 310 vrgiu_diff_iosetting() 311 { 312 struct vrgiu_softc *sc = this_giu; 313 static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0; 314 long iosel, inten, useupdn, termupdn; 315 u_int32_t m; 316 317 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 318 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 319 if (GIUUSEUPDN_REG_W == GIU_NO_REG_W) 320 useupdn = 0; 321 else 322 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 323 if (GIUTERMUPDN_REG_W == GIU_NO_REG_W) 324 termupdn = 0; 325 else 326 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 327 if (oiosel != iosel || ointen != inten || 328 ouseupdn != useupdn || otermupdn != termupdn) { 329 for (m = 0x80000000; m; m >>=1) 330 printf ("%c" , (useupdn&m) ? 331 ((termupdn&m) ? 'U' : 'D') : 332 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 333 } 334 oiosel = iosel; 335 ointen = inten; 336 ouseupdn = useupdn; 337 otermupdn = termupdn; 338 } 339 340 void 341 vrgiu_dump_io(struct vrgiu_softc *sc) 342 { 343 344 dbg_bit_print(vrgiu_regread_4(sc, GIUPIOD_REG)); 345 dbg_bit_print(vrgiu_regread_4(sc, GIUPODAT_REG)); 346 } 347 348 void 349 vrgiu_diff_io() 350 { 351 struct vrgiu_softc *sc = this_giu; 352 static u_int32_t opreg[2] = {0, 0}; 353 u_int32_t preg[2]; 354 355 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 356 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 357 358 if (opreg[0] != preg[0] || opreg[1] != preg[1]) { 359 printf("giu data: "); 360 dbg_bit_print(preg[0]); 361 dbg_bit_print(preg[1]); 362 } 363 opreg[0] = preg[0]; 364 opreg[1] = preg[1]; 365 } 366 367 void 368 vrgiu_dump_regs(struct vrgiu_softc *sc) 369 { 370 371 if (sc == NULL) { 372 panic("%s(%d): VRGIU device not initialized\n", 373 __FILE__, __LINE__); 374 } 375 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 376 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 377 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 378 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 379 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 380 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 381 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 382 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 383 } 384 /* 385 * GIU regster access method. 386 */ 387 u_int32_t 388 vrgiu_regread_4(struct vrgiu_softc *sc, bus_addr_t offs) 389 { 390 u_int16_t reg[2]; 391 392 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 393 394 return (reg[0] | (reg[1] << 16)); 395 } 396 397 u_int16_t 398 vrgiu_regread(struct vrgiu_softc *sc, bus_addr_t off) 399 { 400 401 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, off)); 402 } 403 404 void 405 vrgiu_regwrite_4(struct vrgiu_softc *sc, bus_addr_t offs, u_int32_t data) 406 { 407 u_int16_t reg[2]; 408 409 reg[0] = data & 0xffff; 410 reg[1] = (data>>16)&0xffff; 411 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 412 } 413 414 void 415 vrgiu_regwrite(struct vrgiu_softc *sc, bus_addr_t off, u_int16_t data) 416 { 417 418 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 419 } 420 421 /* 422 * PORT 423 */ 424 int 425 vrgiu_port_read(hpcio_chip_t hc, int port) 426 { 427 struct vrgiu_softc *sc = hc->hc_sc; 428 int on; 429 430 if (!LEGAL_OUT_PORT(port)) 431 panic("vrgiu_port_read: illegal gpio port"); 432 433 if (port < 32) 434 on = (vrgiu_regread_4(sc, GIUPIOD_REG) & (1 << port)); 435 else 436 on = (vrgiu_regread_4(sc, GIUPODAT_REG) & (1 << (port - 32))); 437 438 return (on ? 1 : 0); 439 } 440 441 void 442 vrgiu_port_write(hpcio_chip_t hc, int port, int onoff) 443 { 444 struct vrgiu_softc *sc = hc->hc_sc; 445 u_int32_t reg[2]; 446 int bank; 447 448 if (!LEGAL_OUT_PORT(port)) 449 panic("vrgiu_port_write: illegal gpio port"); 450 451 reg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 452 reg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 453 bank = port < 32 ? 0 : 1; 454 if (bank == 1) 455 port -= 32; 456 457 if (onoff) 458 reg[bank] |= (1<<port); 459 else 460 reg[bank] &= ~(1<<port); 461 vrgiu_regwrite_4(sc, GIUPIOD_REG, reg[0]); 462 vrgiu_regwrite_4(sc, GIUPODAT_REG, reg[1]); 463 } 464 465 static void 466 vrgiu_update(hpcio_chip_t hc) 467 { 468 } 469 470 static void 471 vrgiu_dump(hpcio_chip_t hc) 472 { 473 } 474 475 static hpcio_chip_t 476 vrgiu_getchip(void* scx, int chipid) 477 { 478 struct vrgiu_softc *sc = scx; 479 480 return (&sc->sc_iochip); 481 } 482 483 /* 484 * Interrupt staff 485 */ 486 void * 487 vrgiu_intr_establish( 488 hpcio_chip_t hc, 489 int port, /* GPIO pin # */ 490 int mode, /* GIU trigger setting */ 491 int (*ih_fun)(void *), 492 void *ih_arg) 493 { 494 struct vrgiu_softc *sc = hc->hc_sc; 495 int s; 496 u_int32_t reg, mask; 497 struct vrgiu_intr_entry *ih; 498 499 if (!LEGAL_INTR_PORT(port)) 500 panic ("vrgiu_intr_establish: bogus interrupt line."); 501 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 502 panic ("vrgiu_intr_establish: bogus interrupt type."); 503 else 504 sc->sc_intr_mode[port] = mode; 505 mask = (1 << port); 506 507 s = splhigh(); 508 509 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 510 panic ("vrgiu_intr_establish: no memory."); 511 512 DPRINTF(DEBUG_INTR, ("%s: port %d ", sc->sc_dev.dv_xname, port)); 513 ih->ih_port = port; 514 ih->ih_fun = ih_fun; 515 ih->ih_arg = ih_arg; 516 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 517 #ifdef WINCE_DEFAULT_SETTING 518 #warning WINCE_DEFAULT_SETTING 519 #else 520 /* 521 * Setup registers 522 */ 523 /* Input mode */ 524 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 525 reg &= ~mask; 526 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 527 528 /* interrupt type */ 529 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 530 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 531 if (mode & HPCIO_INTR_EDGE) { 532 DPRINTF(DEBUG_INTR, ("edge]")); 533 reg |= mask; /* edge */ 534 } else { 535 DPRINTF(DEBUG_INTR, ("level]")); 536 reg &= ~mask; /* level */ 537 } 538 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 539 540 /* interrupt level */ 541 if (!(mode & HPCIO_INTR_EDGE)) { 542 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 543 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 544 if (mode & HPCIO_INTR_HIGH) { 545 DPRINTF(DEBUG_INTR, ("high]")); 546 reg |= mask; /* high */ 547 } else { 548 DPRINTF(DEBUG_INTR, ("low]")); 549 reg &= ~mask; /* low */ 550 } 551 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 552 } 553 /* hold or through */ 554 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 555 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 556 if (mode & HPCIO_INTR_HOLD) { 557 DPRINTF(DEBUG_INTR, ("hold]")); 558 reg |= mask; /* hold */ 559 } else { 560 DPRINTF(DEBUG_INTR, ("through]")); 561 reg &= ~mask; /* through */ 562 } 563 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 564 #endif 565 /* 566 * clear interrupt status 567 */ 568 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 569 reg &= ~mask; 570 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 571 /* 572 * enable interrupt 573 */ 574 #ifdef WINCE_DEFAULT_SETTING 575 #warning WINCE_DEFAULT_SETTING 576 #else 577 sc->sc_intr_mask |= mask; 578 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 579 /* Unmask GIU level 2 mask register */ 580 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 581 #endif 582 splx(s); 583 584 DPRINTF(DEBUG_INTR, ("\n")); 585 586 return (ih); 587 } 588 589 void 590 vrgiu_intr_disestablish(hpcio_chip_t hc, void *arg) 591 { 592 struct vrgiu_intr_entry *ihe = arg; 593 struct vrgiu_softc *sc = hc->hc_sc; 594 int port = ihe->ih_port; 595 struct vrgiu_intr_entry *ih; 596 int s; 597 598 s = splhigh(); 599 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 600 if (ih == ihe) { 601 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 602 free(ih, M_DEVBUF); 603 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 604 /* Disable interrupt */ 605 #ifdef WINCE_DEFAULT_SETTING 606 #warning WINCE_DEFAULT_SETTING 607 #else 608 sc->sc_intr_mask &= ~(1<<port); 609 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 610 #endif 611 } 612 splx(s); 613 return; 614 } 615 } 616 panic("vrgiu_intr_disetablish: no such a handle."); 617 /* NOTREACHED */ 618 } 619 620 /* Clear interrupt */ 621 void 622 vrgiu_intr_clear(hpcio_chip_t hc, void *arg) 623 { 624 struct vrgiu_softc *sc = hc->hc_sc; 625 struct vrgiu_intr_entry *ihe = arg; 626 u_int32_t reg; 627 628 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 629 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port)); 630 } 631 632 static void 633 vrgiu_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip) 634 { 635 struct vrgiu_softc *sc = hc->hc_sc; 636 637 vrip_register_gpio(sc->sc_vc, iochip); 638 } 639 640 /* interrupt handler */ 641 int 642 vrgiu_intr(void *arg) 643 { 644 #ifdef DUMP_GIU_LEVEL2_INTR 645 #warning DUMP_GIU_LEVEL2_INTR 646 static u_int32_t oreg; 647 #endif 648 struct vrgiu_softc *sc = arg; 649 int i; 650 u_int32_t reg; 651 int ledvalue = CONFIG_HOOK_LED_FLASH; 652 653 /* Get Level 2 interrupt status */ 654 vrip_intr_getstatus2 (sc->sc_vc, sc->sc_ih, ®); 655 #ifdef DUMP_GIU_LEVEL2_INTR 656 #warning DUMP_GIU_LEVEL2_INTR 657 { 658 u_int32_t uedge, dedge, j; 659 for (j = 0x80000000; j > 0; j >>=1) 660 printf ("%c" , reg&j ? '|' : '.'); 661 uedge = (reg ^ oreg) & reg; 662 dedge = (reg ^ oreg) & ~reg; 663 if (uedge || dedge) { 664 for (j = 0; j < 32; j++) { 665 if (uedge & (1 << j)) 666 printf ("+%d", j); 667 else if (dedge & (1 << j)) 668 printf ("-%d", j); 669 } 670 } 671 oreg = reg; 672 printf ("\n"); 673 } 674 #endif 675 /* Clear interrupt */ 676 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 677 678 /* Dispatch handler */ 679 for (i = 0; i < MAX_GPIO_INOUT; i++) { 680 if (reg & (1 << i)) { 681 register struct vrgiu_intr_entry *ih; 682 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 683 ih->ih_fun(ih->ih_arg); 684 } 685 } 686 } 687 688 if (vrgiu_intr_led) 689 config_hook_call(CONFIG_HOOK_SET, CONFIG_HOOK_LED, 690 (void *)&ledvalue); 691 return (0); 692 } 693
Indexes created Tue Sep 30 07:10:03 GMT 2025