vrgiu.c revision 1.8
1 /* $NetBSD: vrgiu.c,v 1.8 2000/03/11 09:11:33 shin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/queue.h> 42 #define TAILQ_FOREACH(var, head, field) \ 43 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 44 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 45 46 #include <mips/cpuregs.h> 47 #include <machine/bus.h> 48 49 #include <hpcmips/vr/vripreg.h> 50 #include <hpcmips/vr/vripvar.h> 51 #include <hpcmips/vr/vrgiureg.h> 52 53 #include "locators.h" 54 55 #define VRGIUDEBUG 56 #ifdef VRGIUDEBUG 57 #define DEBUG_IO 1 58 #define DEBUG_INTR 2 59 #ifndef VRGIUDEBUG_CONF 60 #define VRGIUDEBUG_CONF DEBUG_IO 61 /* #define VRGIUDEBUG_CONF 0 */ 62 #endif /* VRGIUDEBUG_CONF */ 63 int vrgiu_debug = VRGIUDEBUG_CONF; 64 #define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg; 65 #else 66 #define DPRINTF(flag, arg) 67 #endif 68 69 #define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT) 70 #define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT) 71 72 int vrgiu_match __P((struct device*, struct cfdata*, void*)); 73 void vrgiu_attach __P((struct device*, struct device*, void*)); 74 int vrgiu_intr __P((void*)); 75 int vrgiu_print __P((void*, const char*)); 76 void vrgiu_callback __P((struct device*)); 77 78 void vrgiu_dump_regs(struct vrgiu_softc *sc); 79 void vrgiu_dump_iosetting(struct vrgiu_softc *sc); 80 u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t)); 81 u_int16_t vrgiu_regread __P((vrgiu_chipset_tag_t, bus_addr_t)); 82 void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t)); 83 void vrgiu_regwrite __P((vrgiu_chipset_tag_t, bus_addr_t, u_int16_t)); 84 85 int vrgiu_port_read __P((vrgiu_chipset_tag_t, int)); 86 int vrgiu_port_write __P((vrgiu_chipset_tag_t, int, int)); 87 88 void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*)); 89 void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*)); 90 91 struct vrgiu_function_tag vrgiu_functions = { 92 vrgiu_port_read, 93 vrgiu_port_write, 94 vrgiu_regread_4, 95 vrgiu_regwrite_4, 96 vrgiu_intr_establish, 97 vrgiu_intr_disestablish 98 }; 99 100 struct cfattach vrgiu_ca = { 101 sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach 102 }; 103 104 int 105 vrgiu_match(parent, cf, aux) 106 struct device *parent; 107 struct cfdata *cf; 108 void *aux; 109 { 110 return 2; /* 1st attach group of vrip */ 111 } 112 113 void 114 vrgiu_attach(parent, self, aux) 115 struct device *parent; 116 struct device *self; 117 void *aux; 118 { 119 struct vrip_attach_args *va = aux; 120 struct vrgiu_softc *sc = (void*)self; 121 struct gpbus_attach_args gpa; 122 int i; 123 124 sc->sc_vc = va->va_vc; 125 sc->sc_iot = va->va_iot; 126 bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 127 0 /* no cache */, &sc->sc_ioh); 128 /* 129 * Disable all interrupts. 130 */ 131 sc->sc_intr_mask = 0; 132 printf("\n"); 133 #ifdef WINCE_DEFAULT_SETTING 134 #warning WINCE_DEFAULT_SETTING 135 #else 136 #ifdef VRGIUDEBUG 137 if (vrgiu_debug & DEBUG_IO) { 138 printf("WIN setting: "); 139 vrgiu_dump_iosetting(sc); 140 printf("\n"); 141 } 142 #endif /* VRGIUDEBUG */ 143 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 144 #endif 145 146 for (i = 0; i < MAX_GPIO_INOUT; i++) 147 TAILQ_INIT(&sc->sc_intr_head[i]); 148 if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO, 149 vrgiu_intr, sc))) { 150 printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname); 151 return; 152 } 153 vrgiu_functions.gf_intr_establish = vrgiu_intr_establish; 154 vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish; 155 /* 156 * Register functions to upper interface. 157 */ 158 vrip_giu_function_register(va->va_vc, &vrgiu_functions, self); 159 #ifdef VRGIUDEBUG 160 /* Display port status (Input/Output) for debugging */ 161 if (vrgiu_debug & DEBUG_IO) { 162 u_int32_t preg[2]; 163 164 printf("I/O setting: "); 165 vrgiu_dump_iosetting(sc); 166 printf("\n"); 167 168 preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG); 169 preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG); 170 printf(" data:"); 171 bitdisp64(preg); 172 } 173 #endif /* VRGIUDEBUG */ 174 /* 175 * General purpose bus 176 */ 177 gpa.gpa_busname = "gpbus"; 178 gpa.gpa_gc = sc; 179 gpa.gpa_gf = &vrgiu_functions; 180 while (config_found(self, &gpa, vrgiu_print)) ; 181 /* 182 * GIU-ISA bridge 183 */ 184 #if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/ 185 config_defer(self, vrgiu_callback); 186 #else 187 vrgiu_callback(self); 188 #endif 189 } 190 191 void 192 vrgiu_callback(self) 193 struct device *self; 194 { 195 struct vrgiu_softc *sc = (void*)self; 196 struct gpbus_attach_args gpa; 197 198 gpa.gpa_busname = "vrisab"; 199 gpa.gpa_gc = sc; 200 gpa.gpa_gf = &vrgiu_functions; 201 config_found(self, &gpa, vrgiu_print); 202 } 203 204 int 205 vrgiu_print(aux, pnp) 206 void *aux; 207 const char *pnp; 208 { 209 if (pnp) 210 return (QUIET); 211 return (UNCONF); 212 } 213 214 void 215 vrgiu_dump_iosetting(sc) 216 struct vrgiu_softc *sc; 217 { 218 long iosel, inten, useupdn, termupdn; 219 u_int32_t m; 220 iosel= vrgiu_regread_4(sc, GIUIOSEL_REG); 221 inten= vrgiu_regread_4(sc, GIUINTEN_REG); 222 useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W); 223 termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W); 224 for (m = 0x80000000; m; m >>=1) 225 printf ("%c" , (useupdn&m) ? 226 ((termupdn&m) ? 'U' : 'D') : 227 ((iosel&m) ? 'o' : ((inten&m)?'I':'i'))); 228 } 229 230 void 231 vrgiu_dump_regs(sc) 232 struct vrgiu_softc *sc; 233 { 234 if (sc == NULL) { 235 panic("%s(%d): VRGIU device not initialized\n", 236 __FILE__, __LINE__); 237 } 238 printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG)); 239 printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG)); 240 printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG)); 241 printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG)); 242 printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG)); 243 printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG)); 244 printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG)); 245 printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG)); 246 } 247 /* 248 * GIU regster access method. 249 */ 250 u_int32_t 251 vrgiu_regread_4(vc, offs) 252 vrgiu_chipset_tag_t vc; 253 bus_addr_t offs; 254 { 255 struct vrgiu_softc *sc = (void*)vc; 256 u_int16_t reg[2]; 257 bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 258 return reg[0]|(reg[1]<<16); 259 } 260 261 u_int16_t 262 vrgiu_regread(vc, off) 263 vrgiu_chipset_tag_t vc; 264 bus_addr_t off; 265 { 266 struct vrgiu_softc *sc = (void*)vc; 267 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 268 } 269 270 void 271 vrgiu_regwrite_4(vc, offs, data) 272 vrgiu_chipset_tag_t vc; 273 bus_addr_t offs; 274 u_int32_t data; 275 { 276 struct vrgiu_softc *sc = (void*)vc; 277 278 u_int16_t reg[2]; 279 reg[0] = data & 0xffff; 280 reg[1] = (data>>16)&0xffff; 281 bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2); 282 } 283 284 void 285 vrgiu_regwrite(vc, off, data) 286 vrgiu_chipset_tag_t vc; 287 bus_addr_t off; 288 u_int16_t data; 289 { 290 struct vrgiu_softc *sc = (void*)vc; 291 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data); 292 } 293 294 /* 295 * PORT 296 */ 297 int 298 vrgiu_port_read(vc, port) 299 vrgiu_chipset_tag_t vc; 300 int port; 301 { 302 int on; 303 304 if (!LEGAL_OUT_PORT(port)) 305 panic("vrgiu_port_read: illegal gpio port"); 306 307 if (port < 32) 308 on = (vrgiu_regread_4(vc, GIUPIOD_REG) & (1 << port)); 309 else 310 on = (vrgiu_regread_4(vc, GIUPODAT_REG) & (1 << (port - 32))); 311 312 return (on ? 1 : 0); 313 } 314 315 int 316 vrgiu_port_write(vc, port, onoff) 317 vrgiu_chipset_tag_t vc; 318 int port; 319 int onoff; 320 { 321 u_int32_t reg[2]; 322 int bank; 323 324 if (!LEGAL_OUT_PORT(port)) 325 panic("vrgiu_port_write: illegal gpio port"); 326 327 reg[0] = vrgiu_regread_4(vc, GIUPIOD_REG); 328 reg[1] = vrgiu_regread_4(vc, GIUPODAT_REG); 329 bank = port < 32 ? 0 : 1; 330 if (bank == 1) 331 port -= 32; 332 333 if (onoff) 334 reg[bank] |= (1<<port); 335 else 336 reg[bank] &= ~(1<<port); 337 vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]); 338 vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]); 339 340 return 0; 341 } 342 /* 343 * For before autoconfiguration. 344 */ 345 void 346 __vrgiu_out(port, data) 347 int port; 348 int data; 349 { 350 u_int16_t reg; 351 u_int32_t addr; 352 int offs; 353 354 if (!LEGAL_OUT_PORT(port)) 355 panic("__vrgiu_out: illegal gpio port"); 356 if (port < 16) { 357 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W)); 358 offs = port; 359 } else if (port < 32) { 360 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W)); 361 offs = port - 16; 362 } else if (port < 48) { 363 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W)); 364 offs = port - 32; 365 } else { 366 addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W)); 367 offs = port - 48; 368 panic ("__vrgiu_out: not coded yet."); 369 } 370 printf ("__vrgiu_out: addr %08x bit %d\n", addr, offs); 371 372 wbflush(); 373 reg = *((volatile u_int16_t*)addr); 374 if (data) { 375 reg |= (1 << offs); 376 } else { 377 reg &= ~(1 << offs); 378 } 379 *((volatile u_int16_t*)addr) = reg; 380 wbflush(); 381 } 382 /* 383 * Interrupt staff 384 */ 385 void * 386 vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg) 387 vrgiu_chipset_tag_t ic; 388 int port; /* GPIO pin # */ 389 int mode; /* GIU trigger setting */ 390 int level; /* XXX not yet */ 391 int (*ih_fun) __P((void*)); 392 void *ih_arg; 393 { 394 struct vrgiu_softc *sc = (void*)ic; 395 int s; 396 u_int32_t reg, mask; 397 struct vrgiu_intr_entry *ih; 398 399 if (!LEGAL_INTR_PORT(port)) 400 panic ("vrgiu_intr_establish: bogus interrupt line."); 401 if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port]) 402 panic ("vrgiu_intr_establish: bogus interrupt type."); 403 else 404 sc->sc_intr_mode[port] = mode; 405 mask = (1 << port); 406 407 s = splhigh(); 408 409 if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT))) 410 panic ("vrgiu_intr_establish: no memory."); 411 412 ih->ih_port = port; 413 ih->ih_fun = ih_fun; 414 ih->ih_arg = ih_arg; 415 TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link); 416 #ifdef WINCE_DEFAULT_SETTING 417 #warning WINCE_DEFAULT_SETTING 418 #else 419 /* 420 * Setup registers 421 */ 422 /* Input mode */ 423 reg = vrgiu_regread_4(sc, GIUIOSEL_REG); 424 reg &= ~mask; 425 vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg); 426 427 /* interrupt type */ 428 reg = vrgiu_regread_4(sc, GIUINTTYP_REG); 429 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level")); 430 if (mode & VRGIU_INTR_EDGE) { 431 DPRINTF(DEBUG_INTR, ("edge]")); 432 reg |= mask; /* edge */ 433 } else { 434 DPRINTF(DEBUG_INTR, ("level]")); 435 reg &= ~mask; /* level */ 436 } 437 vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg); 438 439 /* interrupt level */ 440 if (!(mode & VRGIU_INTR_EDGE)) { 441 reg = vrgiu_regread_4(sc, GIUINTALSEL_REG); 442 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low")); 443 if (mode & VRGIU_INTR_HIGH) { 444 DPRINTF(DEBUG_INTR, ("high]")); 445 reg |= mask; /* high */ 446 } else { 447 DPRINTF(DEBUG_INTR, ("low]")); 448 reg &= ~mask; /* low */ 449 } 450 vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg); 451 } 452 /* hold or through */ 453 reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG); 454 DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through")); 455 if (mode & VRGIU_INTR_HOLD) { 456 DPRINTF(DEBUG_INTR, ("hold]")); 457 reg |= mask; /* hold */ 458 } else { 459 DPRINTF(DEBUG_INTR, ("through]")); 460 reg &= ~mask; /* through */ 461 } 462 vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg); 463 #endif 464 /* 465 * clear interrupt status 466 */ 467 reg = vrgiu_regread_4(sc, GIUINTSTAT_REG); 468 reg &= ~mask; 469 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg); 470 /* 471 * enable interrupt 472 */ 473 #ifdef WINCE_DEFAULT_SETTING 474 #warning WINCE_DEFAULT_SETTING 475 #else 476 sc->sc_intr_mask |= mask; 477 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 478 /* Unmask GIU level 2 mask register */ 479 vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1); 480 #endif 481 splx(s); 482 483 DPRINTF(DEBUG_INTR, ("\n")); 484 #if 0 && defined VRGIUDEBUG 485 vrgiu_dump_regs(sc); 486 #endif 487 488 return ih; 489 } 490 491 void 492 vrgiu_intr_disestablish(ic, arg) 493 vrgiu_chipset_tag_t ic; 494 void *arg; 495 { 496 struct vrgiu_intr_entry *ihe = arg; 497 struct vrgiu_softc *sc = (void*)ic; 498 int port = ihe->ih_port; 499 struct vrgiu_intr_entry *ih; 500 int s; 501 502 s = splhigh(); 503 TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) { 504 if (ih == ihe) { 505 TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link); 506 free(ih, M_DEVBUF); 507 if (TAILQ_EMPTY(&sc->sc_intr_head[port])) { 508 /* Disable interrupt */ 509 #ifdef WINCE_DEFAULT_SETTING 510 #warning WINCE_DEFAULT_SETTING 511 #else 512 sc->sc_intr_mask &= ~(1<<port); 513 vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask); 514 #endif 515 } 516 splx(s); 517 return; 518 } 519 } 520 panic("vrgiu_intr_disetablish: no such a handle."); 521 /* NOTREACHED */ 522 } 523 524 int 525 vrgiu_intr(arg) 526 void *arg; 527 { 528 #ifdef DUMP_GIU_LEVEL2_INTR 529 #warning DUMP_GIU_LEVEL2_INTR 530 static u_int32_t oreg; 531 #endif 532 struct vrgiu_softc *sc = arg; 533 int i; 534 u_int32_t reg; 535 /* Get Level 2 interrupt status */ 536 vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®); 537 #ifdef DUMP_GIU_LEVEL2_INTR 538 #warning DUMP_GIU_LEVEL2_INTR 539 { 540 u_int32_t uedge, dedge, j; 541 for (j = 0x80000000; j > 0; j >>=1) 542 printf ("%c" , reg&j ? '|' : '.'); 543 uedge = (reg ^ oreg) & reg; 544 dedge = (reg ^ oreg) & ~reg; 545 if (uedge || dedge) { 546 for (j = 0; j < 32; j++) { 547 if (uedge & (1 << j)) 548 printf ("+%d", j); 549 else if (dedge & (1 << j)) 550 printf ("-%d", j); 551 } 552 } 553 oreg = reg; 554 printf ("\n"); 555 } 556 #endif 557 /* Clear interrupt */ 558 vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG)); 559 560 /* Dispatch handler */ 561 for (i = 0; i < MAX_GPIO_INOUT; i++) { 562 if (reg & (1 << i)) { 563 register struct vrgiu_intr_entry *ih; 564 TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) { 565 ih->ih_fun(ih->ih_arg); 566 } 567 } 568 } 569 570 return 0; 571 } 572
Indexes created Sat Sep 27 14:09:57 GMT 2025