vrip.c revision 1.12
1 /* $NetBSD: vrip.c,v 1.12 2001/09/16 05:32:21 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 #include "opt_vr41xx.h" 37 #include "opt_tx39xx.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/reboot.h> 43 44 #include <machine/cpu.h> 45 #include <machine/bus.h> 46 #include <machine/autoconf.h> 47 #include <machine/platid.h> 48 #include <machine/platid_mask.h> 49 50 #include <hpcmips/vr/vr.h> 51 #include <hpcmips/vr/vrcpudef.h> 52 #include <hpcmips/vr/vripreg.h> 53 #include <hpcmips/vr/vripvar.h> 54 #include <hpcmips/vr/icureg.h> 55 #include "locators.h" 56 57 #define VRIPDEBUG 58 #ifdef VRIPDEBUG 59 #ifndef VRIPDEBUG_CONF 60 #define VRIPDEBUG_CONF 0 61 #endif /* VRIPDEBUG_CONF */ 62 int vrip_debug = VRIPDEBUG_CONF; 63 #define DPRINTF(arg) if (vrip_debug) printf arg; 64 #define DBITDISP32(reg) if (vrip_debug) bitdisp32(reg); 65 #define DDUMP_LEVEL2MASK(sc,arg) if (vrip_debug) vrip_dump_level2mask(sc,arg) 66 #else 67 #define DPRINTF(arg) 68 #define DBITDISP32(arg) 69 #define DDUMP_LEVEL2MASK(sc,arg) 70 #endif 71 72 int vripmatch(struct device *, struct cfdata *, void *); 73 void vripattach(struct device *, struct device *, void *); 74 int vrip_print(void *, const char *); 75 int vrip_search(struct device *, struct cfdata *, void *); 76 int vrip_intr(void *, u_int32_t, u_int32_t); 77 78 static void vrip_dump_level2mask(vrip_chipset_tag_t, void *); 79 80 struct cfattach vrip_ca = { 81 sizeof(struct vrip_softc), vripmatch, vripattach 82 }; 83 84 #define MAX_LEVEL1 32 85 86 struct vrip_softc *the_vrip_sc = NULL; 87 88 static struct intrhand { 89 int (*ih_fun)(void *); 90 void *ih_arg; 91 int ih_l1line; 92 int ih_ipl; 93 bus_addr_t ih_lreg; 94 bus_addr_t ih_mlreg; 95 bus_addr_t ih_hreg; 96 bus_addr_t ih_mhreg; 97 } intrhand[MAX_LEVEL1] = { 98 [VRIP_INTR_PIU] = { 0, 0, 0, 0, ICUPIUINT_REG_W,MPIUINT_REG_W }, 99 [VRIP_INTR_AIU] = { 0, 0, 0, 0, AIUINT_REG_W, MAIUINT_REG_W }, 100 [VRIP_INTR_KIU] = { 0, 0, 0, 0, KIUINT_REG_W, MKIUINT_REG_W }, 101 [VRIP_INTR_GIU] = { 0, 0, 0, 0, GIUINT_L_REG_W, MGIUINT_L_REG_W, 102 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 103 [VRIP_INTR_FIR] = { 0, 0, 0, 0, FIRINT_REG_W, MFIRINT_REG_W }, 104 [VRIP_INTR_DSIU] = { 0, 0, 0, 0, DSIUINT_REG_W, MDSIUINT_REG_W }, 105 [VRIP_INTR_PCI] = { 0, 0, 0, 0, PCIINT_REG_W, MPCIINT_REG_W }, 106 [VRIP_INTR_SCU] = { 0, 0, 0, 0, SCUINT_REG_W, MSCUINT_REG_W }, 107 [VRIP_INTR_CSI] = { 0, 0, 0, 0, CSIINT_REG_W, MCSIINT_REG_W }, 108 [VRIP_INTR_BCU] = { 0, 0, 0, 0, BCUINT_REG_W, MBCUINT_REG_W } 109 }; 110 111 #define LEGAL_LEVEL1(x) ((x) >= 0 && (x) < MAX_LEVEL1) 112 113 void 114 bitdisp16(u_int16_t a) 115 { 116 u_int16_t j; 117 118 for (j = 0x8000; j > 0; j >>=1) 119 printf ("%c", a&j ?'|':'.'); 120 printf ("\n"); 121 } 122 123 void 124 bitdisp32(u_int32_t a) 125 { 126 u_int32_t j; 127 128 for (j = 0x80000000; j > 0; j >>=1) 129 printf ("%c" , a&j ? '|' : '.'); 130 printf ("\n"); 131 } 132 133 void 134 bitdisp64(u_int32_t a[2]) 135 { 136 u_int32_t j; 137 138 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 139 printf("%c" , a[1]&j ?';':',' ); 140 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 141 printf("%c" , a[0]&j ?'|':'.' ); 142 printf("\n"); 143 } 144 145 int 146 vripmatch(struct device *parent, struct cfdata *match, void *aux) 147 { 148 struct mainbus_attach_args *ma = aux; 149 150 #ifdef TX39XX 151 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 152 return (1); 153 #endif /* !TX39XX */ 154 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 155 return (0); 156 157 return (1); 158 } 159 160 void 161 vripattach(struct device *parent, struct device *self, void *aux) 162 { 163 struct mainbus_attach_args *ma = aux; 164 struct vrip_softc *sc = (struct vrip_softc*)self; 165 166 printf("\n"); 167 /* 168 * Map ICU (Interrupt Control Unit) register space. 169 */ 170 sc->sc_iot = ma->ma_iot; 171 if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR, 172 0x20 /*XXX lower area only*/, 173 0, /* no flags */ 174 &sc->sc_ioh)) { 175 printf("vripattach: can't map ICU register.\n"); 176 return; 177 } 178 179 /* 180 * Disable all Level 1 interrupts. 181 */ 182 sc->sc_intrmask = 0; 183 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 184 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000); 185 /* 186 * Level 1 interrupts are redirected to HwInt0 187 */ 188 vr_intr_establish(VR_INTR0, vrip_intr, self); 189 the_vrip_sc = sc; 190 /* 191 * Attach each devices 192 * GIU CMU interface interface is used by other system device. 193 * so attach first 194 */ 195 sc->sc_pri = 2; 196 config_search(vrip_search, self, vrip_print); 197 /* Other system devices. */ 198 sc->sc_pri = 1; 199 config_search(vrip_search, self, vrip_print); 200 } 201 202 int 203 vrip_print(void *aux, const char *hoge) 204 { 205 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 206 207 if (va->va_addr) 208 printf(" addr 0x%lx", va->va_addr); 209 if (va->va_size > 1) 210 printf("-0x%lx", va->va_addr + va->va_size - 1); 211 if (va->va_intr != VRIPCF_INTR_DEFAULT) 212 printf(" intr %d", va->va_intr); 213 214 return (UNCONF); 215 } 216 217 int 218 vrip_search(struct device *parent, struct cfdata *cf, void *aux) 219 { 220 struct vrip_softc *sc = (struct vrip_softc *)parent; 221 struct vrip_attach_args va; 222 223 va.va_vc = sc; 224 va.va_iot = sc->sc_iot; 225 va.va_addr = cf->cf_loc[VRIPCF_ADDR]; 226 va.va_size = cf->cf_loc[VRIPCF_SIZE]; 227 va.va_intr = cf->cf_loc[VRIPCF_INTR]; 228 va.va_addr2 = cf->cf_loc[VRIPCF_ADDR2]; 229 va.va_size2 = cf->cf_loc[VRIPCF_SIZE2]; 230 va.va_gpio_chips = sc->sc_gpio_chips; 231 va.va_cc = sc->sc_cc; 232 va.va_cf = sc->sc_cf; 233 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 234 config_attach(parent, cf, &va, vrip_print); 235 236 return (0); 237 } 238 239 void * 240 vrip_intr_establish(vrip_chipset_tag_t vc, int intr, int level, 241 int (*ih_fun)(void *), void *ih_arg) 242 { 243 struct intrhand *ih; 244 245 if (!LEGAL_LEVEL1(intr)) 246 return (0); 247 ih = &intrhand[intr]; 248 if (ih->ih_fun) /* Can't share level 1 interrupt */ 249 return (0); 250 ih->ih_l1line = intr; 251 ih->ih_fun = ih_fun; 252 ih->ih_arg = ih_arg; 253 254 /* Mask level 2 interrupt mask register. (disable interrupt) */ 255 vrip_intr_setmask2(vc, ih, ~0, 0); 256 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 257 vrip_intr_setmask1(vc, ih, 1); 258 259 return ((void *)ih); 260 } 261 262 void 263 vrip_intr_disestablish(vrip_chipset_tag_t vc, void *arg) 264 { 265 struct intrhand *ih = arg; 266 267 ih->ih_fun = NULL; 268 ih->ih_arg = NULL; 269 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 270 vrip_intr_setmask2(vc, ih, ~0, 0); 271 /* Mask Level 1 interrupt mask register (disable interrupt) */ 272 vrip_intr_setmask1(vc, ih, 0); 273 } 274 275 void 276 vrip_intr_suspend() 277 { 278 bus_space_tag_t iot = the_vrip_sc->sc_iot; 279 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 280 281 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 282 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0); 283 } 284 285 void 286 vrip_intr_resume() 287 { 288 u_int32_t reg = the_vrip_sc->sc_intrmask; 289 bus_space_tag_t iot = the_vrip_sc->sc_iot; 290 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 291 292 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 293 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 294 } 295 296 /* Set level 1 interrupt mask. */ 297 void 298 vrip_intr_setmask1(vrip_chipset_tag_t vc, void *arg, int enable) 299 { 300 struct vrip_softc *sc = (void*)vc; 301 struct intrhand *ih = arg; 302 int level1 = ih->ih_l1line; 303 bus_space_tag_t iot = sc->sc_iot; 304 bus_space_handle_t ioh = sc->sc_ioh; 305 u_int32_t reg = sc->sc_intrmask; 306 307 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 308 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 309 if (enable) 310 reg |= (1 << level1); 311 else { 312 reg &= ~(1 << level1); 313 } 314 sc->sc_intrmask = reg; 315 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 316 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 317 DBITDISP32(reg); 318 319 return; 320 } 321 322 static void 323 vrip_dump_level2mask(vrip_chipset_tag_t vc, void *arg) 324 { 325 struct vrip_softc *sc = (void*)vc; 326 struct intrhand *ih = arg; 327 u_int32_t reg; 328 329 if (ih->ih_mlreg) { 330 printf ("level1[%d] level2 mask:", ih->ih_l1line); 331 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 332 if (ih->ih_mhreg) { /* GIU [16:31] case only */ 333 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg) << 16); 334 bitdisp32(reg); 335 } else 336 bitdisp16(reg); 337 } 338 } 339 340 /* Get level 2 interrupt status */ 341 void 342 vrip_intr_get_status2(vrip_chipset_tag_t vc, void *arg, 343 u_int32_t *mask /* Level 2 mask */) 344 { 345 struct vrip_softc *sc = (void*)vc; 346 struct intrhand *ih = arg; 347 u_int32_t reg; 348 349 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 350 ih->ih_lreg); 351 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 352 ih->ih_hreg) << 16)&0xffff0000); 353 /* bitdisp32(reg);*/ 354 *mask = reg; 355 } 356 357 /* Set level 2 interrupt mask. */ 358 void 359 vrip_intr_setmask2(vrip_chipset_tag_t vc, void *arg, 360 u_int32_t mask /* Level 2 mask */, int onoff) 361 { 362 struct vrip_softc *sc = (void*)vc; 363 struct intrhand *ih = arg; 364 u_int16_t reg; 365 366 DPRINTF(("vrip_intr_setmask2:\n")); 367 DDUMP_LEVEL2MASK(vc, arg); 368 #ifdef WINCE_DEFAULT_SETTING 369 #warning WINCE_DEFAULT_SETTING 370 #else 371 if (ih->ih_mlreg) { 372 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 373 if (onoff) 374 reg |= (mask&0xffff); 375 else 376 reg &= ~(mask&0xffff); 377 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg, reg); 378 if (ih->ih_mhreg != -1) { /* GIU [16:31] case only */ 379 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 380 ih->ih_mhreg); 381 if (onoff) 382 reg |= ((mask >> 16) & 0xffff); 383 else 384 reg &= ~((mask >> 16) & 0xffff); 385 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 386 ih->ih_mhreg, reg); 387 } 388 } 389 #endif /* WINCE_DEFAULT_SETTING */ 390 DDUMP_LEVEL2MASK(vc, arg); 391 392 return; 393 } 394 395 int 396 vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 397 { 398 struct vrip_softc *sc = (struct vrip_softc*)arg; 399 bus_space_tag_t iot = sc->sc_iot; 400 bus_space_handle_t ioh = sc->sc_ioh; 401 int i; 402 u_int32_t reg, mask; 403 /* 404 * Read level1 interrupt status. 405 */ 406 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 407 ((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000); 408 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 409 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 410 reg &= mask; 411 412 /* 413 * Dispatch each handler. 414 */ 415 for (i = 0; i < 32; i++) { 416 register struct intrhand *ih = &intrhand[i]; 417 if (ih->ih_fun && (reg & (1 << i))) { 418 ih->ih_fun(ih->ih_arg); 419 } 420 } 421 422 return (1); 423 } 424 425 void 426 vrip_cmu_function_register(vrip_chipset_tag_t vc, vrcmu_function_tag_t func, 427 vrcmu_chipset_tag_t arg) 428 { 429 struct vrip_softc *sc = (void*)vc; 430 431 sc->sc_cf = func; 432 sc->sc_cc = arg; 433 } 434 435 void 436 vrip_gpio_register(vrip_chipset_tag_t vc, hpcio_chip_t chip) 437 { 438 struct vrip_softc *sc = (void*)vc; 439 440 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 441 panic("%s: '%s' has unknown id, %d", __FUNCTION__, 442 chip->hc_name, chip->hc_chipid); 443 sc->sc_gpio_chips[chip->hc_chipid] = chip; 444 } 445
Indexes created Sun Sep 28 16:09:52 GMT 2025