vrip.c revision 1.15
1 /* $NetBSD: vrip.c,v 1.15 2002/01/27 14:18:12 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the project nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include "opt_vr41xx.h" 33 #include "opt_tx39xx.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/reboot.h> 39 40 #include <machine/cpu.h> 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/platid.h> 44 #include <machine/platid_mask.h> 45 #include <machine/bitdisp.h> 46 47 #include <hpcmips/vr/vr.h> 48 #include <hpcmips/vr/vrcpudef.h> 49 #include <hpcmips/vr/vripunit.h> 50 #include <hpcmips/vr/vripif.h> 51 #include <hpcmips/vr/vripreg.h> 52 #include <hpcmips/vr/vripvar.h> 53 #include <hpcmips/vr/icureg.h> 54 #include <hpcmips/vr/cmureg.h> 55 #include "locators.h" 56 57 #define VRIPDEBUG 58 #ifdef VRIPDEBUG 59 #ifndef VRIPDEBUG_CONF 60 #define VRIPDEBUG_CONF 0 61 #endif /* VRIPDEBUG_CONF */ 62 int vrip_debug = VRIPDEBUG_CONF; 63 #define DPRINTF(arg) if (vrip_debug) printf arg; 64 #define DBITDISP32(reg) if (vrip_debug) bitdisp32(reg); 65 #define DDUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg) 66 #else 67 #define DPRINTF(arg) 68 #define DBITDISP32(arg) 69 #define DDUMP_LEVEL2MASK(sc,arg) 70 #endif 71 72 #define MAX_LEVEL1 32 73 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 74 75 struct vrip_softc { 76 struct device sc_dv; 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 hpcio_chip_t sc_gpio_chips[VRIP_NIOCHIPS]; 80 vrcmu_chipset_tag_t sc_cc; 81 int sc_pri; /* attaching device priority */ 82 u_int32_t sc_intrmask; 83 struct vrip_chipset_tag sc_chipset; 84 const struct vrip_unit *sc_units; 85 int sc_nunits; 86 struct intrhand { 87 int (*ih_fun)(void *); 88 void *ih_arg; 89 const struct vrip_unit *ih_unit; 90 } sc_intrhands[MAX_LEVEL1]; 91 }; 92 93 int vripmatch(struct device *, struct cfdata *, void *); 94 void vripattach(struct device *, struct device *, void *); 95 int vrip_print(void *, const char *); 96 int vrip_search(struct device *, struct cfdata *, void *); 97 int vrip_intr(void *, u_int32_t, u_int32_t); 98 99 int __vrip_power(vrip_chipset_tag_t, int, int); 100 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int, 101 int, int(*)(void*), void*); 102 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 103 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 104 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 105 u_int32_t, int); 106 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 107 u_int32_t*); 108 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 109 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 110 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *); 111 112 struct cfattach vrip_ca = { 113 sizeof(struct vrip_softc), vripmatch, vripattach 114 }; 115 116 struct vrip_softc *the_vrip_sc = NULL; 117 118 static const struct vrip_chipset_tag vrip_chipset_methods = { 119 .vc_power = __vrip_power, 120 .vc_intr_establish = __vrip_intr_establish, 121 .vc_intr_disestablish = __vrip_intr_disestablish, 122 .vc_intr_setmask1 = __vrip_intr_setmask1, 123 .vc_intr_setmask2 = __vrip_intr_setmask2, 124 .vc_intr_getstatus2 = __vrip_intr_getstatus2, 125 .vc_register_cmu = __vrip_register_cmu, 126 .vc_register_gpio = __vrip_register_gpio, 127 }; 128 129 static const struct vrip_unit vrip_units[] = { 130 [VRIP_UNIT_PMU] = { "pmu", 131 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, }, 132 [VRIP_UNIT_RTC] = { "rtc", 133 { VRIP_INTR_RTCL1, }, }, 134 [VRIP_UNIT_PIU] = { "piu", 135 { VRIP_INTR_PIU, }, 136 CMUMASK_PIU, 137 ICUPIUINT_REG_W, MPIUINT_REG_W }, 138 [VRIP_UNIT_KIU] = { "kiu", 139 { VRIP_INTR_KIU, }, 140 CMUMASK_KIU, 141 KIUINT_REG_W, MKIUINT_REG_W }, 142 [VRIP_UNIT_SIU] = { "siu", 143 { VRIP_INTR_SIU, }, }, 144 [VRIP_UNIT_GIU] = { "giu", 145 { VRIP_INTR_GIU, }, 146 0, 147 GIUINT_L_REG_W,MGIUINT_L_REG_W, 148 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 149 [VRIP_UNIT_LED] = { "led", 150 { VRIP_INTR_LED, }, }, 151 [VRIP_UNIT_AIU] = { "aiu", 152 { VRIP_INTR_AIU, }, 153 CMUMASK_AIU, 154 AIUINT_REG_W, MAIUINT_REG_W }, 155 [VRIP_UNIT_FIR] = { "fir", 156 { VRIP_INTR_FIR, }, 157 CMUMASK_FIR, 158 FIRINT_REG_W, MFIRINT_REG_W }, 159 [VRIP_UNIT_DSIU]= { "dsiu", 160 { VRIP_INTR_DSIU, }, 161 CMUMASK_DSIU, 162 DSIUINT_REG_W, MDSIUINT_REG_W }, 163 [VRIP_UNIT_PCIU]= { "pciu", 164 { VRIP_INTR_PCI, }, 165 CMUMASK_PCIU, 166 PCIINT_REG_W, MPCIINT_REG_W }, 167 [VRIP_UNIT_SCU] = { "scu", 168 { VRIP_INTR_SCU, }, 169 0, 170 SCUINT_REG_W, MSCUINT_REG_W }, 171 [VRIP_UNIT_CSI] = { "csi", 172 { VRIP_INTR_CSI, }, 173 CMUMASK_CSI, 174 CSIINT_REG_W, MCSIINT_REG_W }, 175 [VRIP_UNIT_BCU] = { "bcu", 176 { VRIP_INTR_BCU, }, 177 0, 178 BCUINT_REG_W, MBCUINT_REG_W } 179 }; 180 181 int 182 vripmatch(struct device *parent, struct cfdata *match, void *aux) 183 { 184 struct mainbus_attach_args *ma = aux; 185 186 #ifdef TX39XX 187 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 188 return (0); 189 #endif /* TX39XX */ 190 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 191 return (0); 192 193 return (1); 194 } 195 196 void 197 vripattach(struct device *parent, struct device *self, void *aux) 198 { 199 struct vrip_softc *sc = (struct vrip_softc*)self; 200 201 printf("\n"); 202 203 sc->sc_units = vrip_units; 204 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit); 205 206 vripattach_common(parent, self, aux); 207 } 208 209 void 210 vripattach_common(struct device *parent, struct device *self, void *aux) 211 { 212 struct mainbus_attach_args *ma = aux; 213 struct vrip_softc *sc = (struct vrip_softc*)self; 214 215 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */ 216 sc->sc_chipset.vc_sc = sc; 217 218 /* 219 * Map ICU (Interrupt Control Unit) register space. 220 */ 221 sc->sc_iot = ma->ma_iot; 222 if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR, 223 0x20 /*XXX lower area only*/, 224 0, /* no flags */ 225 &sc->sc_ioh)) { 226 printf("vripattach: can't map ICU register.\n"); 227 return; 228 } 229 230 /* 231 * Disable all Level 1 interrupts. 232 */ 233 sc->sc_intrmask = 0; 234 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 235 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000); 236 /* 237 * Level 1 interrupts are redirected to HwInt0 238 */ 239 vr_intr_establish(VR_INTR0, vrip_intr, self); 240 the_vrip_sc = sc; 241 /* 242 * Attach each devices 243 * GIU CMU interface interface is used by other system device. 244 * so attach first 245 */ 246 sc->sc_pri = 2; 247 config_search(vrip_search, self, vrip_print); 248 /* Other system devices. */ 249 sc->sc_pri = 1; 250 config_search(vrip_search, self, vrip_print); 251 } 252 253 int 254 vrip_print(void *aux, const char *hoge) 255 { 256 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 257 258 if (va->va_addr) 259 printf(" addr 0x%lx", va->va_addr); 260 if (va->va_size > 1) 261 printf("-0x%lx", va->va_addr + va->va_size - 1); 262 263 return (UNCONF); 264 } 265 266 int 267 vrip_search(struct device *parent, struct cfdata *cf, void *aux) 268 { 269 struct vrip_softc *sc = (struct vrip_softc *)parent; 270 struct vrip_attach_args va; 271 272 va.va_vc = &sc->sc_chipset; 273 va.va_iot = sc->sc_iot; 274 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 275 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 276 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 277 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 278 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 279 va.va_gpio_chips = sc->sc_gpio_chips; 280 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 281 config_attach(parent, cf, &va, vrip_print); 282 283 return (0); 284 } 285 286 int 287 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff) 288 { 289 struct vrip_softc *sc = vc->vc_sc; 290 const struct vrip_unit *vu; 291 292 if (sc->sc_chipset.vc_cc == NULL) 293 return (0); /* You have no clock mask unit yet. */ 294 if (!VALID_UNIT(sc, unit)) 295 return (0); 296 vu = &sc->sc_units[unit]; 297 298 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 299 vu->vu_clkmask, onoff); 300 } 301 302 vrip_intr_handle_t 303 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level, 304 int (*ih_fun)(void *), void *ih_arg) 305 { 306 struct vrip_softc *sc = vc->vc_sc; 307 const struct vrip_unit *vu; 308 struct intrhand *ih; 309 310 if (!VALID_UNIT(sc, unit)) 311 return (NULL); 312 vu = &sc->sc_units[unit]; 313 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 314 if (ih->ih_fun) /* Can't share level 1 interrupt */ 315 return (NULL); 316 ih->ih_fun = ih_fun; 317 ih->ih_arg = ih_arg; 318 ih->ih_unit = vu; 319 320 /* Mask level 2 interrupt mask register. (disable interrupt) */ 321 vrip_intr_setmask2(vc, ih, ~0, 0); 322 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 323 vrip_intr_setmask1(vc, ih, 1); 324 325 return ((void *)ih); 326 } 327 328 void 329 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 330 { 331 struct intrhand *ih = handle; 332 333 ih->ih_fun = NULL; 334 ih->ih_arg = NULL; 335 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 336 vrip_intr_setmask2(vc, ih, ~0, 0); 337 /* Mask Level 1 interrupt mask register (disable interrupt) */ 338 vrip_intr_setmask1(vc, ih, 0); 339 } 340 341 void 342 vrip_intr_suspend() 343 { 344 bus_space_tag_t iot = the_vrip_sc->sc_iot; 345 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 346 347 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 348 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0); 349 } 350 351 void 352 vrip_intr_resume() 353 { 354 u_int32_t reg = the_vrip_sc->sc_intrmask; 355 bus_space_tag_t iot = the_vrip_sc->sc_iot; 356 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 357 358 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 359 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 360 } 361 362 /* Set level 1 interrupt mask. */ 363 void 364 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 365 int enable) 366 { 367 struct vrip_softc *sc = vc->vc_sc; 368 struct intrhand *ih = handle; 369 int level1 = ih - sc->sc_intrhands; 370 bus_space_tag_t iot = sc->sc_iot; 371 bus_space_handle_t ioh = sc->sc_ioh; 372 u_int32_t reg = sc->sc_intrmask; 373 374 printf("__vrip_intr_setmask1: SYSINT: %s %d\n", enable ? "enable" : "disable", level1); 375 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 376 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 377 if (enable) 378 reg |= (1 << level1); 379 else { 380 reg &= ~(1 << level1); 381 } 382 sc->sc_intrmask = reg; 383 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 384 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 385 DBITDISP32(reg); 386 387 return; 388 } 389 390 void 391 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 392 { 393 struct vrip_softc *sc = vc->vc_sc; 394 struct intrhand *ih = handle; 395 const struct vrip_unit *vu = ih->ih_unit; 396 u_int32_t reg; 397 398 if (vu->vu_mlreg) { 399 printf ("level1[%d] level2 mask:", vu->vu_intr[0]); 400 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 401 if (vu->vu_mhreg) { /* GIU [16:31] case only */ 402 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mhreg) << 16); 403 bitdisp32(reg); 404 } else 405 bitdisp16(reg); 406 } 407 } 408 409 /* Get level 2 interrupt status */ 410 void 411 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 412 u_int32_t *mask /* Level 2 mask */) 413 { 414 struct vrip_softc *sc = vc->vc_sc; 415 struct intrhand *ih = handle; 416 const struct vrip_unit *vu = ih->ih_unit; 417 u_int32_t reg; 418 419 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 420 vu->vu_lreg); 421 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 422 vu->vu_hreg) << 16)&0xffff0000); 423 /* bitdisp32(reg);*/ 424 *mask = reg; 425 } 426 427 /* Set level 2 interrupt mask. */ 428 void 429 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 430 u_int32_t mask /* Level 2 mask */, int onoff) 431 { 432 struct vrip_softc *sc = vc->vc_sc; 433 struct intrhand *ih = handle; 434 const struct vrip_unit *vu = ih->ih_unit; 435 u_int16_t reg; 436 437 DPRINTF(("vrip_intr_setmask2:\n")); 438 DDUMP_LEVEL2MASK(vc, handle); 439 #ifdef WINCE_DEFAULT_SETTING 440 #warning WINCE_DEFAULT_SETTING 441 #else 442 if (vu->vu_mlreg) { 443 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 444 if (onoff) 445 reg |= (mask&0xffff); 446 else 447 reg &= ~(mask&0xffff); 448 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 449 if (vu->vu_mhreg != -1) { /* GIU [16:31] case only */ 450 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 451 vu->vu_mhreg); 452 if (onoff) 453 reg |= ((mask >> 16) & 0xffff); 454 else 455 reg &= ~((mask >> 16) & 0xffff); 456 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 457 vu->vu_mhreg, reg); 458 } 459 } 460 #endif /* WINCE_DEFAULT_SETTING */ 461 DDUMP_LEVEL2MASK(vc, handle); 462 463 return; 464 } 465 466 int 467 vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 468 { 469 struct vrip_softc *sc = (struct vrip_softc*)arg; 470 bus_space_tag_t iot = sc->sc_iot; 471 bus_space_handle_t ioh = sc->sc_ioh; 472 int i; 473 u_int32_t reg, mask; 474 /* 475 * Read level1 interrupt status. 476 */ 477 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 478 ((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000); 479 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 480 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 481 reg &= mask; 482 483 /* 484 * Dispatch each handler. 485 */ 486 for (i = 0; i < 32; i++) { 487 register struct intrhand *ih = &sc->sc_intrhands[i]; 488 if (ih->ih_fun && (reg & (1 << i))) { 489 ih->ih_fun(ih->ih_arg); 490 } 491 } 492 493 return (1); 494 } 495 496 void 497 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 498 { 499 struct vrip_softc *sc = vc->vc_sc; 500 501 sc->sc_chipset.vc_cc = cmu; 502 } 503 504 void 505 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 506 { 507 struct vrip_softc *sc = vc->vc_sc; 508 509 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 510 panic("%s: '%s' has unknown id, %d", __FUNCTION__, 511 chip->hc_name, chip->hc_chipid); 512 sc->sc_gpio_chips[chip->hc_chipid] = chip; 513 } 514
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