vrip.c revision 1.17
1 /* $NetBSD: vrip.c,v 1.17 2002/02/11 04:33:24 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the project nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include "opt_vr41xx.h" 33 #include "opt_tx39xx.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/reboot.h> 39 40 #include <machine/cpu.h> 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/platid.h> 44 #include <machine/platid_mask.h> 45 46 #include <hpcmips/vr/vr.h> 47 #include <hpcmips/vr/vrcpudef.h> 48 #include <hpcmips/vr/vripunit.h> 49 #include <hpcmips/vr/vripif.h> 50 #include <hpcmips/vr/vripreg.h> 51 #include <hpcmips/vr/vripvar.h> 52 #include <hpcmips/vr/icureg.h> 53 #include <hpcmips/vr/cmureg.h> 54 #include "locators.h" 55 56 #ifdef VRIP_DEBUG 57 #define DPRINTF_ENABLE 58 #define DPRINTF_DEBUG vrip_debug 59 #endif 60 #define USE_HPC_DPRINTF 61 #include <machine/debug.h> 62 63 #ifdef VRIP_DEBUG 64 #define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg); 65 #define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg) 66 #else 67 #define DBG_BIT_PRINT(arg) 68 #define DUMP_LEVEL2MASK(sc,arg) 69 #endif 70 71 #define MAX_LEVEL1 32 72 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 73 74 struct vrip_softc { 75 struct device sc_dv; 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 hpcio_chip_t sc_gpio_chips[VRIP_NIOCHIPS]; 79 vrcmu_chipset_tag_t sc_cc; 80 int sc_pri; /* attaching device priority */ 81 u_int32_t sc_intrmask; 82 struct vrip_chipset_tag sc_chipset; 83 const struct vrip_unit *sc_units; 84 int sc_nunits; 85 struct intrhand { 86 int (*ih_fun)(void *); 87 void *ih_arg; 88 const struct vrip_unit *ih_unit; 89 } sc_intrhands[MAX_LEVEL1]; 90 }; 91 92 int vripmatch(struct device *, struct cfdata *, void *); 93 void vripattach(struct device *, struct device *, void *); 94 int vrip_print(void *, const char *); 95 int vrip_search(struct device *, struct cfdata *, void *); 96 int vrip_intr(void *, u_int32_t, u_int32_t); 97 98 int __vrip_power(vrip_chipset_tag_t, int, int); 99 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int, 100 int, int(*)(void*), void*); 101 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 102 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 103 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 104 u_int32_t, int); 105 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 106 u_int32_t*); 107 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 108 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 109 void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 110 void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 111 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *); 112 113 struct cfattach vrip_ca = { 114 sizeof(struct vrip_softc), vripmatch, vripattach 115 }; 116 117 struct vrip_softc *the_vrip_sc = NULL; 118 119 static const struct vrip_chipset_tag vrip_chipset_methods = { 120 .vc_power = __vrip_power, 121 .vc_intr_establish = __vrip_intr_establish, 122 .vc_intr_disestablish = __vrip_intr_disestablish, 123 .vc_intr_setmask1 = __vrip_intr_setmask1, 124 .vc_intr_setmask2 = __vrip_intr_setmask2, 125 .vc_intr_getstatus2 = __vrip_intr_getstatus2, 126 .vc_register_cmu = __vrip_register_cmu, 127 .vc_register_gpio = __vrip_register_gpio, 128 .vc_register_dmaau = __vrip_register_dmaau, 129 .vc_register_dcu = __vrip_register_dcu, 130 }; 131 132 static const struct vrip_unit vrip_units[] = { 133 [VRIP_UNIT_PMU] = { "pmu", 134 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, }, 135 [VRIP_UNIT_RTC] = { "rtc", 136 { VRIP_INTR_RTCL1, }, }, 137 [VRIP_UNIT_PIU] = { "piu", 138 { VRIP_INTR_PIU, }, 139 CMUMASK_PIU, 140 ICUPIUINT_REG_W, MPIUINT_REG_W }, 141 [VRIP_UNIT_KIU] = { "kiu", 142 { VRIP_INTR_KIU, }, 143 CMUMASK_KIU, 144 KIUINT_REG_W, MKIUINT_REG_W }, 145 [VRIP_UNIT_SIU] = { "siu", 146 { VRIP_INTR_SIU, }, }, 147 [VRIP_UNIT_GIU] = { "giu", 148 { VRIP_INTR_GIU, }, 149 0, 150 GIUINT_L_REG_W,MGIUINT_L_REG_W, 151 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 152 [VRIP_UNIT_LED] = { "led", 153 { VRIP_INTR_LED, }, }, 154 [VRIP_UNIT_AIU] = { "aiu", 155 { VRIP_INTR_AIU, }, 156 CMUMASK_AIU, 157 AIUINT_REG_W, MAIUINT_REG_W }, 158 [VRIP_UNIT_FIR] = { "fir", 159 { VRIP_INTR_FIR, }, 160 CMUMASK_FIR, 161 FIRINT_REG_W, MFIRINT_REG_W }, 162 [VRIP_UNIT_DSIU]= { "dsiu", 163 { VRIP_INTR_DSIU, }, 164 CMUMASK_DSIU, 165 DSIUINT_REG_W, MDSIUINT_REG_W }, 166 [VRIP_UNIT_PCIU]= { "pciu", 167 { VRIP_INTR_PCI, }, 168 CMUMASK_PCIU, 169 PCIINT_REG_W, MPCIINT_REG_W }, 170 [VRIP_UNIT_SCU] = { "scu", 171 { VRIP_INTR_SCU, }, 172 0, 173 SCUINT_REG_W, MSCUINT_REG_W }, 174 [VRIP_UNIT_CSI] = { "csi", 175 { VRIP_INTR_CSI, }, 176 CMUMASK_CSI, 177 CSIINT_REG_W, MCSIINT_REG_W }, 178 [VRIP_UNIT_BCU] = { "bcu", 179 { VRIP_INTR_BCU, }, 180 0, 181 BCUINT_REG_W, MBCUINT_REG_W }, 182 }; 183 184 int 185 vripmatch(struct device *parent, struct cfdata *match, void *aux) 186 { 187 struct mainbus_attach_args *ma = aux; 188 189 #ifdef TX39XX 190 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 191 return (0); 192 #endif /* TX39XX */ 193 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 194 return (0); 195 196 return (1); 197 } 198 199 void 200 vripattach(struct device *parent, struct device *self, void *aux) 201 { 202 struct vrip_softc *sc = (struct vrip_softc*)self; 203 204 printf("\n"); 205 206 sc->sc_units = vrip_units; 207 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit); 208 209 vripattach_common(parent, self, aux); 210 } 211 212 void 213 vripattach_common(struct device *parent, struct device *self, void *aux) 214 { 215 struct mainbus_attach_args *ma = aux; 216 struct vrip_softc *sc = (struct vrip_softc*)self; 217 218 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */ 219 sc->sc_chipset.vc_sc = sc; 220 221 /* 222 * Map ICU (Interrupt Control Unit) register space. 223 */ 224 sc->sc_iot = ma->ma_iot; 225 if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR, 226 0x20 /*XXX lower area only*/, 227 0, /* no flags */ 228 &sc->sc_ioh)) { 229 printf("vripattach: can't map ICU register.\n"); 230 return; 231 } 232 233 /* 234 * Disable all Level 1 interrupts. 235 */ 236 sc->sc_intrmask = 0; 237 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 238 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000); 239 /* 240 * Level 1 interrupts are redirected to HwInt0 241 */ 242 vr_intr_establish(VR_INTR0, vrip_intr, self); 243 the_vrip_sc = sc; 244 /* 245 * Attach each devices 246 * GIU CMU DMAAU DCU interface interface is used by other system 247 * device. so attach first 248 */ 249 sc->sc_pri = 2; 250 config_search(vrip_search, self, vrip_print); 251 /* Other system devices. */ 252 sc->sc_pri = 1; 253 config_search(vrip_search, self, vrip_print); 254 } 255 256 int 257 vrip_print(void *aux, const char *hoge) 258 { 259 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 260 261 if (va->va_addr) 262 printf(" addr 0x%lx", va->va_addr); 263 if (va->va_size > 1) 264 printf("-0x%lx", va->va_addr + va->va_size - 1); 265 266 return (UNCONF); 267 } 268 269 int 270 vrip_search(struct device *parent, struct cfdata *cf, void *aux) 271 { 272 struct vrip_softc *sc = (struct vrip_softc *)parent; 273 struct vrip_attach_args va; 274 275 va.va_vc = &sc->sc_chipset; 276 va.va_iot = sc->sc_iot; 277 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 278 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 279 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 280 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 281 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 282 va.va_gpio_chips = sc->sc_gpio_chips; 283 va.va_cc = sc->sc_chipset.vc_cc; 284 va.va_ac = sc->sc_chipset.vc_ac; 285 va.va_dc = sc->sc_chipset.vc_dc; 286 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 287 config_attach(parent, cf, &va, vrip_print); 288 289 return (0); 290 } 291 292 int 293 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff) 294 { 295 struct vrip_softc *sc = vc->vc_sc; 296 const struct vrip_unit *vu; 297 298 if (sc->sc_chipset.vc_cc == NULL) 299 return (0); /* You have no clock mask unit yet. */ 300 if (!VALID_UNIT(sc, unit)) 301 return (0); 302 vu = &sc->sc_units[unit]; 303 304 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 305 vu->vu_clkmask, onoff); 306 } 307 308 vrip_intr_handle_t 309 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level, 310 int (*ih_fun)(void *), void *ih_arg) 311 { 312 struct vrip_softc *sc = vc->vc_sc; 313 const struct vrip_unit *vu; 314 struct intrhand *ih; 315 316 if (!VALID_UNIT(sc, unit)) 317 return (NULL); 318 vu = &sc->sc_units[unit]; 319 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 320 if (ih->ih_fun) /* Can't share level 1 interrupt */ 321 return (NULL); 322 ih->ih_fun = ih_fun; 323 ih->ih_arg = ih_arg; 324 ih->ih_unit = vu; 325 326 /* Mask level 2 interrupt mask register. (disable interrupt) */ 327 vrip_intr_setmask2(vc, ih, ~0, 0); 328 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 329 vrip_intr_setmask1(vc, ih, 1); 330 331 return ((void *)ih); 332 } 333 334 void 335 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 336 { 337 struct intrhand *ih = handle; 338 339 ih->ih_fun = NULL; 340 ih->ih_arg = NULL; 341 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 342 vrip_intr_setmask2(vc, ih, ~0, 0); 343 /* Mask Level 1 interrupt mask register (disable interrupt) */ 344 vrip_intr_setmask1(vc, ih, 0); 345 } 346 347 void 348 vrip_intr_suspend() 349 { 350 bus_space_tag_t iot = the_vrip_sc->sc_iot; 351 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 352 353 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 354 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0); 355 } 356 357 void 358 vrip_intr_resume() 359 { 360 u_int32_t reg = the_vrip_sc->sc_intrmask; 361 bus_space_tag_t iot = the_vrip_sc->sc_iot; 362 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 363 364 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 365 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 366 } 367 368 /* Set level 1 interrupt mask. */ 369 void 370 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 371 int enable) 372 { 373 struct vrip_softc *sc = vc->vc_sc; 374 struct intrhand *ih = handle; 375 int level1 = ih - sc->sc_intrhands; 376 bus_space_tag_t iot = sc->sc_iot; 377 bus_space_handle_t ioh = sc->sc_ioh; 378 u_int32_t reg = sc->sc_intrmask; 379 380 DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n", 381 enable ? "enable" : "disable", level1)); 382 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 383 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 384 if (enable) 385 reg |= (1 << level1); 386 else { 387 reg &= ~(1 << level1); 388 } 389 sc->sc_intrmask = reg; 390 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 391 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 392 DBG_BIT_PRINT(reg); 393 394 return; 395 } 396 397 void 398 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 399 { 400 struct vrip_softc *sc = vc->vc_sc; 401 struct intrhand *ih = handle; 402 const struct vrip_unit *vu = ih->ih_unit; 403 u_int32_t reg; 404 405 if (vu->vu_mlreg) { 406 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 407 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 408 if (vu->vu_mhreg) { /* GIU [16:31] case only */ 409 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 410 vu->vu_mhreg) << 16); 411 dbg_bit_print(reg); 412 } else 413 dbg_bit_print(reg); 414 } 415 } 416 417 /* Get level 2 interrupt status */ 418 void 419 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 420 u_int32_t *mask /* Level 2 mask */) 421 { 422 struct vrip_softc *sc = vc->vc_sc; 423 struct intrhand *ih = handle; 424 const struct vrip_unit *vu = ih->ih_unit; 425 u_int32_t reg; 426 427 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 428 vu->vu_lreg); 429 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 430 vu->vu_hreg) << 16)&0xffff0000); 431 /* dbg_bit_print(reg);*/ 432 *mask = reg; 433 } 434 435 /* Set level 2 interrupt mask. */ 436 void 437 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 438 u_int32_t mask /* Level 2 mask */, int onoff) 439 { 440 struct vrip_softc *sc = vc->vc_sc; 441 struct intrhand *ih = handle; 442 const struct vrip_unit *vu = ih->ih_unit; 443 u_int16_t reg; 444 445 DPRINTF(("vrip_intr_setmask2:\n")); 446 DUMP_LEVEL2MASK(vc, handle); 447 #ifdef WINCE_DEFAULT_SETTING 448 #warning WINCE_DEFAULT_SETTING 449 #else 450 if (vu->vu_mlreg) { 451 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 452 if (onoff) 453 reg |= (mask&0xffff); 454 else 455 reg &= ~(mask&0xffff); 456 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 457 if (vu->vu_mhreg != -1) { /* GIU [16:31] case only */ 458 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 459 vu->vu_mhreg); 460 if (onoff) 461 reg |= ((mask >> 16) & 0xffff); 462 else 463 reg &= ~((mask >> 16) & 0xffff); 464 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 465 vu->vu_mhreg, reg); 466 } 467 } 468 #endif /* WINCE_DEFAULT_SETTING */ 469 DUMP_LEVEL2MASK(vc, handle); 470 471 return; 472 } 473 474 int 475 vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 476 { 477 struct vrip_softc *sc = (struct vrip_softc*)arg; 478 bus_space_tag_t iot = sc->sc_iot; 479 bus_space_handle_t ioh = sc->sc_ioh; 480 int i; 481 u_int32_t reg, mask; 482 /* 483 * Read level1 interrupt status. 484 */ 485 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 486 ((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000); 487 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 488 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 489 reg &= mask; 490 491 /* 492 * Dispatch each handler. 493 */ 494 for (i = 0; i < 32; i++) { 495 register struct intrhand *ih = &sc->sc_intrhands[i]; 496 if (ih->ih_fun && (reg & (1 << i))) { 497 ih->ih_fun(ih->ih_arg); 498 } 499 } 500 501 return (1); 502 } 503 504 void 505 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 506 { 507 struct vrip_softc *sc = vc->vc_sc; 508 509 sc->sc_chipset.vc_cc = cmu; 510 } 511 512 void 513 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 514 { 515 struct vrip_softc *sc = vc->vc_sc; 516 517 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 518 panic("%s: '%s' has unknown id, %d", __FUNCTION__, 519 chip->hc_name, chip->hc_chipid); 520 sc->sc_gpio_chips[chip->hc_chipid] = chip; 521 } 522 523 void 524 __vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 525 { 526 struct vrip_softc *sc = vc->vc_sc; 527 528 sc->sc_chipset.vc_ac = dmaau; 529 } 530 531 void 532 __vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 533 { 534 struct vrip_softc *sc = vc->vc_sc; 535 536 sc->sc_chipset.vc_dc = dcu; 537 } 538
Indexes created Mon Sep 29 21:09:56 GMT 2025