vrip.c revision 1.18
1 /* $NetBSD: vrip.c,v 1.18 2002/02/11 04:56:27 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the project nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include "opt_vr41xx.h" 33 #include "opt_tx39xx.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/reboot.h> 39 40 #include <machine/cpu.h> 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/platid.h> 44 #include <machine/platid_mask.h> 45 46 #include <hpcmips/vr/vr.h> 47 #include <hpcmips/vr/vrcpudef.h> 48 #include <hpcmips/vr/vripunit.h> 49 #include <hpcmips/vr/vripif.h> 50 #include <hpcmips/vr/vripreg.h> 51 #include <hpcmips/vr/vripvar.h> 52 #include <hpcmips/vr/icureg.h> 53 #include <hpcmips/vr/cmureg.h> 54 #include "locators.h" 55 56 #ifdef VRIP_DEBUG 57 #define DPRINTF_ENABLE 58 #define DPRINTF_DEBUG vrip_debug 59 #endif 60 #define USE_HPC_DPRINTF 61 #include <machine/debug.h> 62 63 #ifdef VRIP_DEBUG 64 #define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg); 65 #define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg) 66 #else 67 #define DBG_BIT_PRINT(arg) 68 #define DUMP_LEVEL2MASK(sc,arg) 69 #endif 70 71 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 72 73 #ifdef SINGLE_VRIP_BASE 74 int vripmatch(struct device *, struct cfdata *, void *); 75 void vripattach(struct device *, struct device *, void *); 76 #endif 77 int vrip_print(void *, const char *); 78 int vrip_search(struct device *, struct cfdata *, void *); 79 int vrip_intr(void *, u_int32_t, u_int32_t); 80 81 int __vrip_power(vrip_chipset_tag_t, int, int); 82 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int, 83 int, int(*)(void*), void*); 84 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 85 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 86 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 87 u_int32_t, int); 88 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 89 u_int32_t*); 90 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 91 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 92 void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 93 void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 94 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *); 95 96 struct vrip_softc *the_vrip_sc = NULL; 97 98 static const struct vrip_chipset_tag vrip_chipset_methods = { 99 .vc_power = __vrip_power, 100 .vc_intr_establish = __vrip_intr_establish, 101 .vc_intr_disestablish = __vrip_intr_disestablish, 102 .vc_intr_setmask1 = __vrip_intr_setmask1, 103 .vc_intr_setmask2 = __vrip_intr_setmask2, 104 .vc_intr_getstatus2 = __vrip_intr_getstatus2, 105 .vc_register_cmu = __vrip_register_cmu, 106 .vc_register_gpio = __vrip_register_gpio, 107 .vc_register_dmaau = __vrip_register_dmaau, 108 .vc_register_dcu = __vrip_register_dcu, 109 }; 110 111 #ifdef SINGLE_VRIP_BASE 112 struct cfattach vrip_ca = { 113 sizeof(struct vrip_softc), vripmatch, vripattach 114 }; 115 116 static const struct vrip_unit vrip_units[] = { 117 [VRIP_UNIT_PMU] = { "pmu", 118 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, }, 119 [VRIP_UNIT_RTC] = { "rtc", 120 { VRIP_INTR_RTCL1, }, }, 121 [VRIP_UNIT_PIU] = { "piu", 122 { VRIP_INTR_PIU, }, 123 CMUMASK_PIU, 124 ICUPIUINT_REG_W, MPIUINT_REG_W }, 125 [VRIP_UNIT_KIU] = { "kiu", 126 { VRIP_INTR_KIU, }, 127 CMUMASK_KIU, 128 KIUINT_REG_W, MKIUINT_REG_W }, 129 [VRIP_UNIT_SIU] = { "siu", 130 { VRIP_INTR_SIU, }, }, 131 [VRIP_UNIT_GIU] = { "giu", 132 { VRIP_INTR_GIU, }, 133 0, 134 GIUINT_L_REG_W,MGIUINT_L_REG_W, 135 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 136 [VRIP_UNIT_LED] = { "led", 137 { VRIP_INTR_LED, }, }, 138 [VRIP_UNIT_AIU] = { "aiu", 139 { VRIP_INTR_AIU, }, 140 CMUMASK_AIU, 141 AIUINT_REG_W, MAIUINT_REG_W }, 142 [VRIP_UNIT_FIR] = { "fir", 143 { VRIP_INTR_FIR, }, 144 CMUMASK_FIR, 145 FIRINT_REG_W, MFIRINT_REG_W }, 146 [VRIP_UNIT_DSIU]= { "dsiu", 147 { VRIP_INTR_DSIU, }, 148 CMUMASK_DSIU, 149 DSIUINT_REG_W, MDSIUINT_REG_W }, 150 [VRIP_UNIT_PCIU]= { "pciu", 151 { VRIP_INTR_PCI, }, 152 CMUMASK_PCIU, 153 PCIINT_REG_W, MPCIINT_REG_W }, 154 [VRIP_UNIT_SCU] = { "scu", 155 { VRIP_INTR_SCU, }, 156 0, 157 SCUINT_REG_W, MSCUINT_REG_W }, 158 [VRIP_UNIT_CSI] = { "csi", 159 { VRIP_INTR_CSI, }, 160 CMUMASK_CSI, 161 CSIINT_REG_W, MCSIINT_REG_W }, 162 [VRIP_UNIT_BCU] = { "bcu", 163 { VRIP_INTR_BCU, }, 164 0, 165 BCUINT_REG_W, MBCUINT_REG_W }, 166 }; 167 168 int 169 vripmatch(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct mainbus_attach_args *ma = aux; 172 173 #ifdef TX39XX 174 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 175 return (0); 176 #endif /* TX39XX */ 177 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 178 return (0); 179 180 return (1); 181 } 182 183 void 184 vripattach(struct device *parent, struct device *self, void *aux) 185 { 186 struct vrip_softc *sc = (struct vrip_softc*)self; 187 188 printf("\n"); 189 190 sc->sc_units = vrip_units; 191 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit); 192 sc->sc_icu_addr = VRIP_ICU_ADDR; 193 sc->sc_sysint2 = SYSINT2_REG_W; 194 sc->sc_msysint2 = MSYSINT2_REG_W; 195 196 vripattach_common(parent, self, aux); 197 } 198 #endif /* SINGLE_VRIP_BASE */ 199 200 void 201 vripattach_common(struct device *parent, struct device *self, void *aux) 202 { 203 struct mainbus_attach_args *ma = aux; 204 struct vrip_softc *sc = (struct vrip_softc*)self; 205 206 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */ 207 sc->sc_chipset.vc_sc = sc; 208 209 /* 210 * Map ICU (Interrupt Control Unit) register space. 211 */ 212 sc->sc_iot = ma->ma_iot; 213 if (bus_space_map(sc->sc_iot, sc->sc_icu_addr, 214 0x20 /*XXX lower area only*/, 215 0, /* no flags */ 216 &sc->sc_ioh)) { 217 printf("vripattach: can't map ICU register.\n"); 218 return; 219 } 220 221 /* 222 * Disable all Level 1 interrupts. 223 */ 224 sc->sc_intrmask = 0; 225 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 226 bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_msysint2, 0x0000); 227 /* 228 * Level 1 interrupts are redirected to HwInt0 229 */ 230 vr_intr_establish(VR_INTR0, vrip_intr, self); 231 the_vrip_sc = sc; 232 /* 233 * Attach each devices 234 * GIU CMU DMAAU DCU interface interface is used by other system 235 * device. so attach first 236 */ 237 sc->sc_pri = 2; 238 config_search(vrip_search, self, vrip_print); 239 /* Other system devices. */ 240 sc->sc_pri = 1; 241 config_search(vrip_search, self, vrip_print); 242 } 243 244 int 245 vrip_print(void *aux, const char *hoge) 246 { 247 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 248 249 if (va->va_addr) 250 printf(" addr 0x%lx", va->va_addr); 251 if (va->va_size > 1) 252 printf("-0x%lx", va->va_addr + va->va_size - 1); 253 254 return (UNCONF); 255 } 256 257 int 258 vrip_search(struct device *parent, struct cfdata *cf, void *aux) 259 { 260 struct vrip_softc *sc = (struct vrip_softc *)parent; 261 struct vrip_attach_args va; 262 263 va.va_vc = &sc->sc_chipset; 264 va.va_iot = sc->sc_iot; 265 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 266 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 267 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 268 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 269 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 270 va.va_gpio_chips = sc->sc_gpio_chips; 271 va.va_cc = sc->sc_chipset.vc_cc; 272 va.va_ac = sc->sc_chipset.vc_ac; 273 va.va_dc = sc->sc_chipset.vc_dc; 274 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 275 config_attach(parent, cf, &va, vrip_print); 276 277 return (0); 278 } 279 280 int 281 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff) 282 { 283 struct vrip_softc *sc = vc->vc_sc; 284 const struct vrip_unit *vu; 285 286 if (sc->sc_chipset.vc_cc == NULL) 287 return (0); /* You have no clock mask unit yet. */ 288 if (!VALID_UNIT(sc, unit)) 289 return (0); 290 vu = &sc->sc_units[unit]; 291 292 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 293 vu->vu_clkmask, onoff); 294 } 295 296 vrip_intr_handle_t 297 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level, 298 int (*ih_fun)(void *), void *ih_arg) 299 { 300 struct vrip_softc *sc = vc->vc_sc; 301 const struct vrip_unit *vu; 302 struct intrhand *ih; 303 304 if (!VALID_UNIT(sc, unit)) 305 return (NULL); 306 vu = &sc->sc_units[unit]; 307 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 308 if (ih->ih_fun) /* Can't share level 1 interrupt */ 309 return (NULL); 310 ih->ih_fun = ih_fun; 311 ih->ih_arg = ih_arg; 312 ih->ih_unit = vu; 313 314 /* Mask level 2 interrupt mask register. (disable interrupt) */ 315 vrip_intr_setmask2(vc, ih, ~0, 0); 316 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 317 vrip_intr_setmask1(vc, ih, 1); 318 319 return ((void *)ih); 320 } 321 322 void 323 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 324 { 325 struct intrhand *ih = handle; 326 327 ih->ih_fun = NULL; 328 ih->ih_arg = NULL; 329 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 330 vrip_intr_setmask2(vc, ih, ~0, 0); 331 /* Mask Level 1 interrupt mask register (disable interrupt) */ 332 vrip_intr_setmask1(vc, ih, 0); 333 } 334 335 void 336 vrip_intr_suspend() 337 { 338 struct vrip_softc *sc = the_vrip_sc; 339 bus_space_tag_t iot = sc->sc_iot; 340 bus_space_handle_t ioh = sc->sc_ioh; 341 342 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 343 bus_space_write_2 (iot, ioh, sc->sc_msysint2, 0); 344 } 345 346 void 347 vrip_intr_resume() 348 { 349 struct vrip_softc *sc = the_vrip_sc; 350 u_int32_t reg = sc->sc_intrmask; 351 bus_space_tag_t iot = sc->sc_iot; 352 bus_space_handle_t ioh = sc->sc_ioh; 353 354 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 355 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 356 } 357 358 /* Set level 1 interrupt mask. */ 359 void 360 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 361 int enable) 362 { 363 struct vrip_softc *sc = vc->vc_sc; 364 struct intrhand *ih = handle; 365 int level1 = ih - sc->sc_intrhands; 366 bus_space_tag_t iot = sc->sc_iot; 367 bus_space_handle_t ioh = sc->sc_ioh; 368 u_int32_t reg = sc->sc_intrmask; 369 370 DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n", 371 enable ? "enable" : "disable", level1)); 372 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 373 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2) << 16)&0xffff0000); 374 if (enable) 375 reg |= (1 << level1); 376 else { 377 reg &= ~(1 << level1); 378 } 379 sc->sc_intrmask = reg; 380 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 381 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 382 DBG_BIT_PRINT(reg); 383 384 return; 385 } 386 387 void 388 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 389 { 390 struct vrip_softc *sc = vc->vc_sc; 391 struct intrhand *ih = handle; 392 const struct vrip_unit *vu = ih->ih_unit; 393 u_int32_t reg; 394 395 if (vu->vu_mlreg) { 396 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 397 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 398 if (vu->vu_mhreg) { /* GIU [16:31] case only */ 399 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 400 vu->vu_mhreg) << 16); 401 dbg_bit_print(reg); 402 } else 403 dbg_bit_print(reg); 404 } 405 } 406 407 /* Get level 2 interrupt status */ 408 void 409 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 410 u_int32_t *mask /* Level 2 mask */) 411 { 412 struct vrip_softc *sc = vc->vc_sc; 413 struct intrhand *ih = handle; 414 const struct vrip_unit *vu = ih->ih_unit; 415 u_int32_t reg; 416 417 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 418 vu->vu_lreg); 419 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 420 vu->vu_hreg) << 16)&0xffff0000); 421 /* dbg_bit_print(reg);*/ 422 *mask = reg; 423 } 424 425 /* Set level 2 interrupt mask. */ 426 void 427 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 428 u_int32_t mask /* Level 2 mask */, int onoff) 429 { 430 struct vrip_softc *sc = vc->vc_sc; 431 struct intrhand *ih = handle; 432 const struct vrip_unit *vu = ih->ih_unit; 433 u_int16_t reg; 434 435 DPRINTF(("vrip_intr_setmask2:\n")); 436 DUMP_LEVEL2MASK(vc, handle); 437 #ifdef WINCE_DEFAULT_SETTING 438 #warning WINCE_DEFAULT_SETTING 439 #else 440 if (vu->vu_mlreg) { 441 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 442 if (onoff) 443 reg |= (mask&0xffff); 444 else 445 reg &= ~(mask&0xffff); 446 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 447 if (vu->vu_mhreg != -1) { /* GIU [16:31] case only */ 448 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 449 vu->vu_mhreg); 450 if (onoff) 451 reg |= ((mask >> 16) & 0xffff); 452 else 453 reg &= ~((mask >> 16) & 0xffff); 454 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 455 vu->vu_mhreg, reg); 456 } 457 } 458 #endif /* WINCE_DEFAULT_SETTING */ 459 DUMP_LEVEL2MASK(vc, handle); 460 461 return; 462 } 463 464 int 465 vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 466 { 467 struct vrip_softc *sc = (struct vrip_softc*)arg; 468 bus_space_tag_t iot = sc->sc_iot; 469 bus_space_handle_t ioh = sc->sc_ioh; 470 int i; 471 u_int32_t reg, mask; 472 /* 473 * Read level1 interrupt status. 474 */ 475 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 476 ((bus_space_read_2 (iot, ioh, sc->sc_sysint2)<< 16)&0xffff0000); 477 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 478 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2)<< 16)&0xffff0000); 479 reg &= mask; 480 481 /* 482 * Dispatch each handler. 483 */ 484 for (i = 0; i < 32; i++) { 485 register struct intrhand *ih = &sc->sc_intrhands[i]; 486 if (ih->ih_fun && (reg & (1 << i))) { 487 ih->ih_fun(ih->ih_arg); 488 } 489 } 490 491 return (1); 492 } 493 494 void 495 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 496 { 497 struct vrip_softc *sc = vc->vc_sc; 498 499 sc->sc_chipset.vc_cc = cmu; 500 } 501 502 void 503 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 504 { 505 struct vrip_softc *sc = vc->vc_sc; 506 507 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 508 panic("%s: '%s' has unknown id, %d", __FUNCTION__, 509 chip->hc_name, chip->hc_chipid); 510 sc->sc_gpio_chips[chip->hc_chipid] = chip; 511 } 512 513 void 514 __vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 515 { 516 struct vrip_softc *sc = vc->vc_sc; 517 518 sc->sc_chipset.vc_ac = dmaau; 519 } 520 521 void 522 __vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 523 { 524 struct vrip_softc *sc = vc->vc_sc; 525 526 sc->sc_chipset.vc_dc = dcu; 527 } 528
Indexes created Sun Sep 28 16:09:52 GMT 2025