vrip.c revision 1.24
1 /* $NetBSD: vrip.c,v 1.24 2002/09/27 02:24:15 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the project nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include "opt_vr41xx.h" 33 #include "opt_tx39xx.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/reboot.h> 39 40 #include <machine/cpu.h> 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/platid.h> 44 #include <machine/platid_mask.h> 45 46 #include <hpcmips/vr/vr.h> 47 #include <hpcmips/vr/vrcpudef.h> 48 #include <hpcmips/vr/vripunit.h> 49 #include <hpcmips/vr/vripif.h> 50 #include <hpcmips/vr/vripreg.h> 51 #include <hpcmips/vr/vripvar.h> 52 #include <hpcmips/vr/icureg.h> 53 #include <hpcmips/vr/cmureg.h> 54 #include "locators.h" 55 56 #ifdef VRIP_DEBUG 57 #define DPRINTF_ENABLE 58 #define DPRINTF_DEBUG vrip_debug 59 #endif 60 #define USE_HPC_DPRINTF 61 #include <machine/debug.h> 62 63 #ifdef VRIP_DEBUG 64 #define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg); 65 #define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg) 66 #else 67 #define DBG_BIT_PRINT(arg) 68 #define DUMP_LEVEL2MASK(sc,arg) 69 #endif 70 71 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 72 73 #ifdef SINGLE_VRIP_BASE 74 int vripmatch(struct device *, struct cfdata *, void *); 75 void vripattach(struct device *, struct device *, void *); 76 #endif 77 int vrip_print(void *, const char *); 78 int vrip_search(struct device *, struct cfdata *, void *); 79 int vrip_intr(void *, u_int32_t, u_int32_t); 80 81 int __vrip_power(vrip_chipset_tag_t, int, int); 82 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int, 83 int, int(*)(void*), void*); 84 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 85 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 86 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 87 u_int32_t, int); 88 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 89 u_int32_t*); 90 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 91 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 92 void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 93 void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 94 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *); 95 96 struct vrip_softc *the_vrip_sc = NULL; 97 98 static const struct vrip_chipset_tag vrip_chipset_methods = { 99 .vc_power = __vrip_power, 100 .vc_intr_establish = __vrip_intr_establish, 101 .vc_intr_disestablish = __vrip_intr_disestablish, 102 .vc_intr_setmask1 = __vrip_intr_setmask1, 103 .vc_intr_setmask2 = __vrip_intr_setmask2, 104 .vc_intr_getstatus2 = __vrip_intr_getstatus2, 105 .vc_register_cmu = __vrip_register_cmu, 106 .vc_register_gpio = __vrip_register_gpio, 107 .vc_register_dmaau = __vrip_register_dmaau, 108 .vc_register_dcu = __vrip_register_dcu, 109 }; 110 111 #ifdef SINGLE_VRIP_BASE 112 struct cfattach vrip_ca = { 113 sizeof(struct vrip_softc), vripmatch, vripattach 114 }; 115 116 static const struct vrip_unit vrip_units[] = { 117 [VRIP_UNIT_PMU] = { "pmu", 118 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, }, 119 [VRIP_UNIT_RTC] = { "rtc", 120 { VRIP_INTR_RTCL1, }, }, 121 [VRIP_UNIT_PIU] = { "piu", 122 { VRIP_INTR_PIU, }, 123 CMUMASK_PIU, 124 ICUPIUINT_REG_W, MPIUINT_REG_W }, 125 [VRIP_UNIT_KIU] = { "kiu", 126 { VRIP_INTR_KIU, }, 127 CMUMASK_KIU, 128 KIUINT_REG_W, MKIUINT_REG_W }, 129 [VRIP_UNIT_SIU] = { "siu", 130 { VRIP_INTR_SIU, }, }, 131 [VRIP_UNIT_GIU] = { "giu", 132 { VRIP_INTR_GIU, }, 133 0, 134 GIUINT_L_REG_W,MGIUINT_L_REG_W, 135 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 136 [VRIP_UNIT_LED] = { "led", 137 { VRIP_INTR_LED, }, }, 138 [VRIP_UNIT_AIU] = { "aiu", 139 { VRIP_INTR_AIU, }, 140 CMUMASK_AIU, 141 AIUINT_REG_W, MAIUINT_REG_W }, 142 [VRIP_UNIT_FIR] = { "fir", 143 { VRIP_INTR_FIR, }, 144 CMUMASK_FIR, 145 FIRINT_REG_W, MFIRINT_REG_W }, 146 [VRIP_UNIT_DSIU]= { "dsiu", 147 { VRIP_INTR_DSIU, }, 148 CMUMASK_DSIU, 149 DSIUINT_REG_W, MDSIUINT_REG_W }, 150 [VRIP_UNIT_PCIU]= { "pciu", 151 { VRIP_INTR_PCI, }, 152 CMUMASK_PCIU, 153 PCIINT_REG_W, MPCIINT_REG_W }, 154 [VRIP_UNIT_SCU] = { "scu", 155 { VRIP_INTR_SCU, }, 156 0, 157 SCUINT_REG_W, MSCUINT_REG_W }, 158 [VRIP_UNIT_CSI] = { "csi", 159 { VRIP_INTR_CSI, }, 160 CMUMASK_CSI, 161 CSIINT_REG_W, MCSIINT_REG_W }, 162 [VRIP_UNIT_BCU] = { "bcu", 163 { VRIP_INTR_BCU, }, 164 0, 165 BCUINT_REG_W, MBCUINT_REG_W }, 166 }; 167 168 void 169 vripattach(struct device *parent, struct device *self, void *aux) 170 { 171 struct vrip_softc *sc = (struct vrip_softc*)self; 172 173 printf("\n"); 174 175 sc->sc_units = vrip_units; 176 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit); 177 sc->sc_icu_addr = VRIP_ICU_ADDR; 178 sc->sc_sysint2 = SYSINT2_REG_W; 179 sc->sc_msysint2 = MSYSINT2_REG_W; 180 181 vripattach_common(parent, self, aux); 182 } 183 #endif /* SINGLE_VRIP_BASE */ 184 185 int 186 vripmatch(struct device *parent, struct cfdata *match, void *aux) 187 { 188 struct mainbus_attach_args *ma = aux; 189 190 #if defined(SINGLE_VRIP_BASE) && defined(TX39XX) 191 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 192 return (0); 193 #endif /* SINGLE_VRIP_BASE && TX39XX */ 194 if (strcmp(ma->ma_name, match->cf_name)) 195 return (0); 196 197 return (1); 198 } 199 200 void 201 vripattach_common(struct device *parent, struct device *self, void *aux) 202 { 203 struct mainbus_attach_args *ma = aux; 204 struct vrip_softc *sc = (struct vrip_softc*)self; 205 206 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */ 207 sc->sc_chipset.vc_sc = sc; 208 209 #ifdef DIAGNOSTIC 210 if (sc->sc_icu_addr == 0 || 211 sc->sc_sysint2 == 0 || 212 sc->sc_msysint2 == 0) 213 panic("vripattach: missing register info."); 214 #endif /* DIAGNOSTIC */ 215 216 /* 217 * Map ICU (Interrupt Control Unit) register space. 218 */ 219 sc->sc_iot = ma->ma_iot; 220 if (bus_space_map(sc->sc_iot, sc->sc_icu_addr, 221 0x20 /*XXX lower area only*/, 222 0, /* no flags */ 223 &sc->sc_ioh)) { 224 printf("vripattach: can't map ICU register.\n"); 225 return; 226 } 227 228 /* 229 * Disable all Level 1 interrupts. 230 */ 231 sc->sc_intrmask = 0; 232 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 233 bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_msysint2, 0x0000); 234 /* 235 * Level 1 interrupts are redirected to HwInt0 236 */ 237 vr_intr_establish(VR_INTR0, vrip_intr, self); 238 the_vrip_sc = sc; 239 /* 240 * Attach each devices 241 * GIU CMU DMAAU DCU interface interface is used by other system 242 * device. so attach first 243 */ 244 sc->sc_pri = 2; 245 config_search(vrip_search, self, vrip_print); 246 /* Other system devices. */ 247 sc->sc_pri = 1; 248 config_search(vrip_search, self, vrip_print); 249 } 250 251 int 252 vrip_print(void *aux, const char *hoge) 253 { 254 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 255 bus_addr_t endaddr, mask; 256 257 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT) 258 printf(" addr 0x%08lx", va->va_addr); 259 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) { 260 endaddr = (va->va_addr + va->va_size - 1); 261 mask = ((va->va_addr ^ endaddr) & 0xff0000) ? 0xffffff:0xffff; 262 printf("-%04lx", endaddr & mask); 263 } 264 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT) 265 printf(", 0x%08lx", va->va_addr2); 266 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT) 267 printf("-%04lx", (va->va_addr2 + va->va_size2 - 1) & 0xffff); 268 269 return (UNCONF); 270 } 271 272 int 273 vrip_search(struct device *parent, struct cfdata *cf, void *aux) 274 { 275 struct vrip_softc *sc = (struct vrip_softc *)parent; 276 struct vrip_attach_args va; 277 platid_mask_t mask; 278 279 if (cf->cf_loc[VRIPIFCF_PLATFORM] != VRIPIFCF_PLATFORM_DEFAULT) { 280 mask = PLATID_DEREF(cf->cf_loc[VRIPIFCF_PLATFORM]); 281 if (platid_match(&platid, &mask) == 0) 282 return (0); 283 } 284 285 memset(&va, 0, sizeof(va)); 286 va.va_vc = &sc->sc_chipset; 287 va.va_iot = sc->sc_iot; 288 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 289 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 290 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 291 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 292 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 293 va.va_gpio_chips = sc->sc_gpio_chips; 294 va.va_cc = sc->sc_chipset.vc_cc; 295 va.va_ac = sc->sc_chipset.vc_ac; 296 va.va_dc = sc->sc_chipset.vc_dc; 297 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 298 config_attach(parent, cf, &va, vrip_print); 299 300 return (0); 301 } 302 303 int 304 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff) 305 { 306 struct vrip_softc *sc = vc->vc_sc; 307 const struct vrip_unit *vu; 308 309 if (sc->sc_chipset.vc_cc == NULL) 310 return (0); /* You have no clock mask unit yet. */ 311 if (!VALID_UNIT(sc, unit)) 312 return (0); 313 vu = &sc->sc_units[unit]; 314 315 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 316 vu->vu_clkmask, onoff); 317 } 318 319 vrip_intr_handle_t 320 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level, 321 int (*ih_fun)(void *), void *ih_arg) 322 { 323 struct vrip_softc *sc = vc->vc_sc; 324 const struct vrip_unit *vu; 325 struct intrhand *ih; 326 327 if (!VALID_UNIT(sc, unit)) 328 return (NULL); 329 vu = &sc->sc_units[unit]; 330 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 331 if (ih->ih_fun) /* Can't share level 1 interrupt */ 332 return (NULL); 333 ih->ih_fun = ih_fun; 334 ih->ih_arg = ih_arg; 335 ih->ih_unit = vu; 336 337 /* Mask level 2 interrupt mask register. (disable interrupt) */ 338 vrip_intr_setmask2(vc, ih, ~0, 0); 339 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 340 vrip_intr_setmask1(vc, ih, 1); 341 342 return ((void *)ih); 343 } 344 345 void 346 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 347 { 348 struct intrhand *ih = handle; 349 350 ih->ih_fun = NULL; 351 ih->ih_arg = NULL; 352 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 353 vrip_intr_setmask2(vc, ih, ~0, 0); 354 /* Mask Level 1 interrupt mask register (disable interrupt) */ 355 vrip_intr_setmask1(vc, ih, 0); 356 } 357 358 void 359 vrip_intr_suspend() 360 { 361 struct vrip_softc *sc = the_vrip_sc; 362 bus_space_tag_t iot = sc->sc_iot; 363 bus_space_handle_t ioh = sc->sc_ioh; 364 365 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 366 bus_space_write_2 (iot, ioh, sc->sc_msysint2, 0); 367 } 368 369 void 370 vrip_intr_resume() 371 { 372 struct vrip_softc *sc = the_vrip_sc; 373 u_int32_t reg = sc->sc_intrmask; 374 bus_space_tag_t iot = sc->sc_iot; 375 bus_space_handle_t ioh = sc->sc_ioh; 376 377 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 378 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 379 } 380 381 /* Set level 1 interrupt mask. */ 382 void 383 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 384 int enable) 385 { 386 struct vrip_softc *sc = vc->vc_sc; 387 struct intrhand *ih = handle; 388 int level1 = ih - sc->sc_intrhands; 389 bus_space_tag_t iot = sc->sc_iot; 390 bus_space_handle_t ioh = sc->sc_ioh; 391 u_int32_t reg = sc->sc_intrmask; 392 393 DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n", 394 enable ? "enable" : "disable", level1)); 395 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 396 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2) << 16)&0xffff0000); 397 if (enable) 398 reg |= (1 << level1); 399 else { 400 reg &= ~(1 << level1); 401 } 402 sc->sc_intrmask = reg; 403 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 404 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 405 DBG_BIT_PRINT(reg); 406 407 return; 408 } 409 410 void 411 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 412 { 413 struct vrip_softc *sc = vc->vc_sc; 414 struct intrhand *ih = handle; 415 const struct vrip_unit *vu = ih->ih_unit; 416 u_int32_t reg; 417 418 if (vu->vu_mlreg) { 419 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 420 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 421 if (vu->vu_mhreg) { /* GIU [16:31] case only */ 422 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 423 vu->vu_mhreg) << 16); 424 dbg_bit_print(reg); 425 } else 426 dbg_bit_print(reg); 427 } 428 } 429 430 /* Get level 2 interrupt status */ 431 void 432 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 433 u_int32_t *mask /* Level 2 mask */) 434 { 435 struct vrip_softc *sc = vc->vc_sc; 436 struct intrhand *ih = handle; 437 const struct vrip_unit *vu = ih->ih_unit; 438 u_int32_t reg; 439 440 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 441 vu->vu_lreg); 442 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 443 vu->vu_hreg) << 16)&0xffff0000); 444 /* dbg_bit_print(reg);*/ 445 *mask = reg; 446 } 447 448 /* Set level 2 interrupt mask. */ 449 void 450 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 451 u_int32_t mask /* Level 2 mask */, int onoff) 452 { 453 struct vrip_softc *sc = vc->vc_sc; 454 struct intrhand *ih = handle; 455 const struct vrip_unit *vu = ih->ih_unit; 456 u_int16_t reg; 457 458 DPRINTF(("vrip_intr_setmask2:\n")); 459 DUMP_LEVEL2MASK(vc, handle); 460 #ifdef WINCE_DEFAULT_SETTING 461 #warning WINCE_DEFAULT_SETTING 462 #else 463 if (vu->vu_mlreg) { 464 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 465 if (onoff) 466 reg |= (mask&0xffff); 467 else 468 reg &= ~(mask&0xffff); 469 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 470 if (vu->vu_mhreg != 0) { /* GIU [16:31] case only */ 471 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 472 vu->vu_mhreg); 473 if (onoff) 474 reg |= ((mask >> 16) & 0xffff); 475 else 476 reg &= ~((mask >> 16) & 0xffff); 477 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 478 vu->vu_mhreg, reg); 479 } 480 } 481 #endif /* WINCE_DEFAULT_SETTING */ 482 DUMP_LEVEL2MASK(vc, handle); 483 484 return; 485 } 486 487 int 488 vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 489 { 490 struct vrip_softc *sc = (struct vrip_softc*)arg; 491 bus_space_tag_t iot = sc->sc_iot; 492 bus_space_handle_t ioh = sc->sc_ioh; 493 int i; 494 u_int32_t reg, mask; 495 /* 496 * Read level1 interrupt status. 497 */ 498 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 499 ((bus_space_read_2 (iot, ioh, sc->sc_sysint2)<< 16)&0xffff0000); 500 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 501 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2)<< 16)&0xffff0000); 502 reg &= mask; 503 504 /* 505 * Dispatch each handler. 506 */ 507 for (i = 0; i < 32; i++) { 508 register struct intrhand *ih = &sc->sc_intrhands[i]; 509 if (ih->ih_fun && (reg & (1 << i))) { 510 ih->ih_fun(ih->ih_arg); 511 } 512 } 513 514 return (1); 515 } 516 517 void 518 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 519 { 520 struct vrip_softc *sc = vc->vc_sc; 521 522 sc->sc_chipset.vc_cc = cmu; 523 } 524 525 void 526 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 527 { 528 struct vrip_softc *sc = vc->vc_sc; 529 530 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 531 panic("%s: '%s' has unknown id, %d", __FUNCTION__, 532 chip->hc_name, chip->hc_chipid); 533 sc->sc_gpio_chips[chip->hc_chipid] = chip; 534 } 535 536 void 537 __vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 538 { 539 struct vrip_softc *sc = vc->vc_sc; 540 541 sc->sc_chipset.vc_ac = dmaau; 542 } 543 544 void 545 __vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 546 { 547 struct vrip_softc *sc = vc->vc_sc; 548 549 sc->sc_chipset.vc_dc = dcu; 550 } 551
Indexes created Sun Sep 28 16:09:52 GMT 2025