vrip.c revision 1.27
1 /* $NetBSD: vrip.c,v 1.27 2002/10/02 05:26:55 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the project nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include "opt_vr41xx.h" 33 #include "opt_tx39xx.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/reboot.h> 39 40 #include <machine/cpu.h> 41 #include <machine/bus.h> 42 #include <machine/autoconf.h> 43 #include <machine/platid.h> 44 #include <machine/platid_mask.h> 45 46 #include <hpcmips/vr/vr.h> 47 #include <hpcmips/vr/vrcpudef.h> 48 #include <hpcmips/vr/vripunit.h> 49 #include <hpcmips/vr/vripif.h> 50 #include <hpcmips/vr/vripreg.h> 51 #include <hpcmips/vr/vripvar.h> 52 #include <hpcmips/vr/icureg.h> 53 #include <hpcmips/vr/cmureg.h> 54 #include "locators.h" 55 56 #ifdef VRIP_DEBUG 57 #define DPRINTF_ENABLE 58 #define DPRINTF_DEBUG vrip_debug 59 #endif 60 #define USE_HPC_DPRINTF 61 #include <machine/debug.h> 62 63 #ifdef VRIP_DEBUG 64 #define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg); 65 #define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg) 66 #else 67 #define DBG_BIT_PRINT(arg) 68 #define DUMP_LEVEL2MASK(sc,arg) 69 #endif 70 71 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 72 73 #ifdef SINGLE_VRIP_BASE 74 int vripmatch(struct device *, struct cfdata *, void *); 75 void vripattach(struct device *, struct device *, void *); 76 #endif 77 int vrip_print(void *, const char *); 78 int vrip_search(struct device *, struct cfdata *, void *); 79 int vrip_intr(void *, u_int32_t, u_int32_t); 80 81 int __vrip_power(vrip_chipset_tag_t, int, int); 82 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int, 83 int, int(*)(void*), void*); 84 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 85 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 86 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 87 u_int32_t, int); 88 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 89 u_int32_t*); 90 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 91 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 92 void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 93 void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 94 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *); 95 96 struct vrip_softc *the_vrip_sc = NULL; 97 98 static const struct vrip_chipset_tag vrip_chipset_methods = { 99 .vc_power = __vrip_power, 100 .vc_intr_establish = __vrip_intr_establish, 101 .vc_intr_disestablish = __vrip_intr_disestablish, 102 .vc_intr_setmask1 = __vrip_intr_setmask1, 103 .vc_intr_setmask2 = __vrip_intr_setmask2, 104 .vc_intr_getstatus2 = __vrip_intr_getstatus2, 105 .vc_register_cmu = __vrip_register_cmu, 106 .vc_register_gpio = __vrip_register_gpio, 107 .vc_register_dmaau = __vrip_register_dmaau, 108 .vc_register_dcu = __vrip_register_dcu, 109 }; 110 111 #ifdef SINGLE_VRIP_BASE 112 CFATTACH_DECL(vrip, sizeof(struct vrip_softc), 113 vripmatch, vripattach, NULL, NULL); 114 115 static const struct vrip_unit vrip_units[] = { 116 [VRIP_UNIT_PMU] = { "pmu", 117 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, }, 118 [VRIP_UNIT_RTC] = { "rtc", 119 { VRIP_INTR_RTCL1, }, }, 120 [VRIP_UNIT_PIU] = { "piu", 121 { VRIP_INTR_PIU, }, 122 CMUMASK_PIU, 123 ICUPIUINT_REG_W, MPIUINT_REG_W }, 124 [VRIP_UNIT_KIU] = { "kiu", 125 { VRIP_INTR_KIU, }, 126 CMUMASK_KIU, 127 KIUINT_REG_W, MKIUINT_REG_W }, 128 [VRIP_UNIT_SIU] = { "siu", 129 { VRIP_INTR_SIU, }, }, 130 [VRIP_UNIT_GIU] = { "giu", 131 { VRIP_INTR_GIU, }, 132 0, 133 GIUINT_L_REG_W,MGIUINT_L_REG_W, 134 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 135 [VRIP_UNIT_LED] = { "led", 136 { VRIP_INTR_LED, }, }, 137 [VRIP_UNIT_AIU] = { "aiu", 138 { VRIP_INTR_AIU, }, 139 CMUMASK_AIU, 140 AIUINT_REG_W, MAIUINT_REG_W }, 141 [VRIP_UNIT_FIR] = { "fir", 142 { VRIP_INTR_FIR, }, 143 CMUMASK_FIR, 144 FIRINT_REG_W, MFIRINT_REG_W }, 145 [VRIP_UNIT_DSIU]= { "dsiu", 146 { VRIP_INTR_DSIU, }, 147 CMUMASK_DSIU, 148 DSIUINT_REG_W, MDSIUINT_REG_W }, 149 [VRIP_UNIT_PCIU]= { "pciu", 150 { VRIP_INTR_PCI, }, 151 CMUMASK_PCIU, 152 PCIINT_REG_W, MPCIINT_REG_W }, 153 [VRIP_UNIT_SCU] = { "scu", 154 { VRIP_INTR_SCU, }, 155 0, 156 SCUINT_REG_W, MSCUINT_REG_W }, 157 [VRIP_UNIT_CSI] = { "csi", 158 { VRIP_INTR_CSI, }, 159 CMUMASK_CSI, 160 CSIINT_REG_W, MCSIINT_REG_W }, 161 [VRIP_UNIT_BCU] = { "bcu", 162 { VRIP_INTR_BCU, }, 163 0, 164 BCUINT_REG_W, MBCUINT_REG_W }, 165 }; 166 167 void 168 vripattach(struct device *parent, struct device *self, void *aux) 169 { 170 struct vrip_softc *sc = (struct vrip_softc*)self; 171 172 printf("\n"); 173 174 sc->sc_units = vrip_units; 175 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit); 176 sc->sc_icu_addr = VRIP_ICU_ADDR; 177 sc->sc_sysint2 = SYSINT2_REG_W; 178 sc->sc_msysint2 = MSYSINT2_REG_W; 179 180 vripattach_common(parent, self, aux); 181 } 182 #endif /* SINGLE_VRIP_BASE */ 183 184 int 185 vripmatch(struct device *parent, struct cfdata *match, void *aux) 186 { 187 struct mainbus_attach_args *ma = aux; 188 189 #if defined(SINGLE_VRIP_BASE) && defined(TX39XX) 190 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 191 return (0); 192 #endif /* SINGLE_VRIP_BASE && TX39XX */ 193 if (strcmp(ma->ma_name, match->cf_name)) 194 return (0); 195 196 return (1); 197 } 198 199 void 200 vripattach_common(struct device *parent, struct device *self, void *aux) 201 { 202 struct mainbus_attach_args *ma = aux; 203 struct vrip_softc *sc = (struct vrip_softc*)self; 204 205 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */ 206 sc->sc_chipset.vc_sc = sc; 207 208 #ifdef DIAGNOSTIC 209 if (sc->sc_icu_addr == 0 || 210 sc->sc_sysint2 == 0 || 211 sc->sc_msysint2 == 0) 212 panic("vripattach: missing register info."); 213 #endif /* DIAGNOSTIC */ 214 215 /* 216 * Map ICU (Interrupt Control Unit) register space. 217 */ 218 sc->sc_iot = ma->ma_iot; 219 if (bus_space_map(sc->sc_iot, sc->sc_icu_addr, 220 0x20 /*XXX lower area only*/, 221 0, /* no flags */ 222 &sc->sc_ioh)) { 223 printf("vripattach: can't map ICU register.\n"); 224 return; 225 } 226 227 /* 228 * Disable all Level 1 interrupts. 229 */ 230 sc->sc_intrmask = 0; 231 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 232 bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_msysint2, 0x0000); 233 /* 234 * Level 1 interrupts are redirected to HwInt0 235 */ 236 vr_intr_establish(VR_INTR0, vrip_intr, self); 237 the_vrip_sc = sc; 238 /* 239 * Attach each devices 240 * GIU CMU DMAAU DCU interface interface is used by other system 241 * device. so attach first 242 */ 243 sc->sc_pri = 2; 244 config_search(vrip_search, self, vrip_print); 245 /* Other system devices. */ 246 sc->sc_pri = 1; 247 config_search(vrip_search, self, vrip_print); 248 } 249 250 int 251 vrip_print(void *aux, const char *hoge) 252 { 253 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 254 bus_addr_t endaddr, mask; 255 256 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT) 257 printf(" addr 0x%08lx", va->va_addr); 258 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) { 259 endaddr = (va->va_addr + va->va_size - 1); 260 mask = ((va->va_addr ^ endaddr) & 0xff0000) ? 0xffffff:0xffff; 261 printf("-%04lx", endaddr & mask); 262 } 263 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT) 264 printf(", 0x%08lx", va->va_addr2); 265 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT) 266 printf("-%04lx", (va->va_addr2 + va->va_size2 - 1) & 0xffff); 267 268 return (UNCONF); 269 } 270 271 int 272 vrip_search(struct device *parent, struct cfdata *cf, void *aux) 273 { 274 struct vrip_softc *sc = (struct vrip_softc *)parent; 275 struct vrip_attach_args va; 276 platid_mask_t mask; 277 278 if (cf->cf_loc[VRIPIFCF_PLATFORM] != VRIPIFCF_PLATFORM_DEFAULT) { 279 mask = PLATID_DEREF(cf->cf_loc[VRIPIFCF_PLATFORM]); 280 if (platid_match(&platid, &mask) == 0) 281 return (0); 282 } 283 284 memset(&va, 0, sizeof(va)); 285 va.va_vc = &sc->sc_chipset; 286 va.va_iot = sc->sc_iot; 287 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 288 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 289 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 290 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 291 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 292 va.va_gpio_chips = sc->sc_gpio_chips; 293 va.va_cc = sc->sc_chipset.vc_cc; 294 va.va_ac = sc->sc_chipset.vc_ac; 295 va.va_dc = sc->sc_chipset.vc_dc; 296 if ((config_match(parent, cf, &va) == sc->sc_pri)) 297 config_attach(parent, cf, &va, vrip_print); 298 299 return (0); 300 } 301 302 int 303 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff) 304 { 305 struct vrip_softc *sc = vc->vc_sc; 306 const struct vrip_unit *vu; 307 308 if (sc->sc_chipset.vc_cc == NULL) 309 return (0); /* You have no clock mask unit yet. */ 310 if (!VALID_UNIT(sc, unit)) 311 return (0); 312 vu = &sc->sc_units[unit]; 313 314 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 315 vu->vu_clkmask, onoff); 316 } 317 318 vrip_intr_handle_t 319 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level, 320 int (*ih_fun)(void *), void *ih_arg) 321 { 322 struct vrip_softc *sc = vc->vc_sc; 323 const struct vrip_unit *vu; 324 struct intrhand *ih; 325 326 if (!VALID_UNIT(sc, unit)) 327 return (NULL); 328 vu = &sc->sc_units[unit]; 329 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 330 if (ih->ih_fun) /* Can't share level 1 interrupt */ 331 return (NULL); 332 ih->ih_fun = ih_fun; 333 ih->ih_arg = ih_arg; 334 ih->ih_unit = vu; 335 336 /* Mask level 2 interrupt mask register. (disable interrupt) */ 337 vrip_intr_setmask2(vc, ih, ~0, 0); 338 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 339 vrip_intr_setmask1(vc, ih, 1); 340 341 return ((void *)ih); 342 } 343 344 void 345 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 346 { 347 struct intrhand *ih = handle; 348 349 ih->ih_fun = NULL; 350 ih->ih_arg = NULL; 351 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 352 vrip_intr_setmask2(vc, ih, ~0, 0); 353 /* Mask Level 1 interrupt mask register (disable interrupt) */ 354 vrip_intr_setmask1(vc, ih, 0); 355 } 356 357 void 358 vrip_intr_suspend() 359 { 360 struct vrip_softc *sc = the_vrip_sc; 361 bus_space_tag_t iot = sc->sc_iot; 362 bus_space_handle_t ioh = sc->sc_ioh; 363 364 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 365 bus_space_write_2 (iot, ioh, sc->sc_msysint2, 0); 366 } 367 368 void 369 vrip_intr_resume() 370 { 371 struct vrip_softc *sc = the_vrip_sc; 372 u_int32_t reg = sc->sc_intrmask; 373 bus_space_tag_t iot = sc->sc_iot; 374 bus_space_handle_t ioh = sc->sc_ioh; 375 376 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 377 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 378 } 379 380 /* Set level 1 interrupt mask. */ 381 void 382 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 383 int enable) 384 { 385 struct vrip_softc *sc = vc->vc_sc; 386 struct intrhand *ih = handle; 387 int level1 = ih - sc->sc_intrhands; 388 bus_space_tag_t iot = sc->sc_iot; 389 bus_space_handle_t ioh = sc->sc_ioh; 390 u_int32_t reg = sc->sc_intrmask; 391 392 DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n", 393 enable ? "enable" : "disable", level1)); 394 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 395 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2) << 16)&0xffff0000); 396 if (enable) 397 reg |= (1 << level1); 398 else { 399 reg &= ~(1 << level1); 400 } 401 sc->sc_intrmask = reg; 402 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 403 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 404 DBG_BIT_PRINT(reg); 405 406 return; 407 } 408 409 void 410 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 411 { 412 struct vrip_softc *sc = vc->vc_sc; 413 struct intrhand *ih = handle; 414 const struct vrip_unit *vu = ih->ih_unit; 415 u_int32_t reg; 416 417 if (vu->vu_mlreg) { 418 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 419 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 420 if (vu->vu_mhreg) { /* GIU [16:31] case only */ 421 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 422 vu->vu_mhreg) << 16); 423 dbg_bit_print(reg); 424 } else 425 dbg_bit_print(reg); 426 } 427 } 428 429 /* Get level 2 interrupt status */ 430 void 431 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 432 u_int32_t *mask /* Level 2 mask */) 433 { 434 struct vrip_softc *sc = vc->vc_sc; 435 struct intrhand *ih = handle; 436 const struct vrip_unit *vu = ih->ih_unit; 437 u_int32_t reg; 438 439 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 440 vu->vu_lreg); 441 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 442 vu->vu_hreg) << 16)&0xffff0000); 443 /* dbg_bit_print(reg);*/ 444 *mask = reg; 445 } 446 447 /* Set level 2 interrupt mask. */ 448 void 449 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 450 u_int32_t mask /* Level 2 mask */, int onoff) 451 { 452 struct vrip_softc *sc = vc->vc_sc; 453 struct intrhand *ih = handle; 454 const struct vrip_unit *vu = ih->ih_unit; 455 u_int16_t reg; 456 457 DPRINTF(("vrip_intr_setmask2:\n")); 458 DUMP_LEVEL2MASK(vc, handle); 459 #ifdef WINCE_DEFAULT_SETTING 460 #warning WINCE_DEFAULT_SETTING 461 #else 462 if (vu->vu_mlreg) { 463 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 464 if (onoff) 465 reg |= (mask&0xffff); 466 else 467 reg &= ~(mask&0xffff); 468 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 469 if (vu->vu_mhreg != 0) { /* GIU [16:31] case only */ 470 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 471 vu->vu_mhreg); 472 if (onoff) 473 reg |= ((mask >> 16) & 0xffff); 474 else 475 reg &= ~((mask >> 16) & 0xffff); 476 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 477 vu->vu_mhreg, reg); 478 } 479 } 480 #endif /* WINCE_DEFAULT_SETTING */ 481 DUMP_LEVEL2MASK(vc, handle); 482 483 return; 484 } 485 486 int 487 vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg) 488 { 489 struct vrip_softc *sc = (struct vrip_softc*)arg; 490 bus_space_tag_t iot = sc->sc_iot; 491 bus_space_handle_t ioh = sc->sc_ioh; 492 int i; 493 u_int32_t reg, mask; 494 /* 495 * Read level1 interrupt status. 496 */ 497 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 498 ((bus_space_read_2 (iot, ioh, sc->sc_sysint2)<< 16)&0xffff0000); 499 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 500 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2)<< 16)&0xffff0000); 501 reg &= mask; 502 503 /* 504 * Dispatch each handler. 505 */ 506 for (i = 0; i < 32; i++) { 507 register struct intrhand *ih = &sc->sc_intrhands[i]; 508 if (ih->ih_fun && (reg & (1 << i))) { 509 ih->ih_fun(ih->ih_arg); 510 } 511 } 512 513 return (1); 514 } 515 516 void 517 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 518 { 519 struct vrip_softc *sc = vc->vc_sc; 520 521 sc->sc_chipset.vc_cc = cmu; 522 } 523 524 void 525 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 526 { 527 struct vrip_softc *sc = vc->vc_sc; 528 529 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 530 panic("%s: '%s' has unknown id, %d", __FUNCTION__, 531 chip->hc_name, chip->hc_chipid); 532 sc->sc_gpio_chips[chip->hc_chipid] = chip; 533 } 534 535 void 536 __vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 537 { 538 struct vrip_softc *sc = vc->vc_sc; 539 540 sc->sc_chipset.vc_ac = dmaau; 541 } 542 543 void 544 __vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 545 { 546 struct vrip_softc *sc = vc->vc_sc; 547 548 sc->sc_chipset.vc_dc = dcu; 549 } 550
Indexes created Mon Sep 29 21:09:56 GMT 2025