vrip.c revision 1.37
1 /* $NetBSD: vrip.c,v 1.37 2012/10/27 17:17:56 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the project nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: vrip.c,v 1.37 2012/10/27 17:17:56 chs Exp $"); 35 36 #include "opt_vr41xx.h" 37 #include "opt_tx39xx.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/reboot.h> 43 44 #include <machine/cpu.h> 45 #include <machine/bus.h> 46 #include <machine/autoconf.h> 47 #include <machine/platid.h> 48 #include <machine/platid_mask.h> 49 50 #include <hpcmips/vr/vr.h> 51 #include <hpcmips/vr/vrcpudef.h> 52 #include <hpcmips/vr/vripunit.h> 53 #include <hpcmips/vr/vripif.h> 54 #include <hpcmips/vr/vripreg.h> 55 #include <hpcmips/vr/vripvar.h> 56 #include <hpcmips/vr/icureg.h> 57 #include <hpcmips/vr/cmureg.h> 58 #include "locators.h" 59 60 #ifdef VRIP_DEBUG 61 #define DPRINTF_ENABLE 62 #define DPRINTF_DEBUG vrip_debug 63 #endif 64 #define USE_HPC_DPRINTF 65 #include <machine/debug.h> 66 67 #ifdef VRIP_DEBUG 68 #define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg); 69 #define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg) 70 #else 71 #define DBG_BIT_PRINT(arg) 72 #define DUMP_LEVEL2MASK(sc,arg) 73 #endif 74 75 #define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits) 76 77 #ifdef SINGLE_VRIP_BASE 78 int vripmatch(device_t, cfdata_t, void *); 79 void vripattach(device_t, device_t, void *); 80 #endif 81 int vrip_print(void *, const char *); 82 int vrip_search(device_t, cfdata_t, const int *, void *); 83 int vrip_intr(void *, vaddr_t, u_int32_t); 84 85 int __vrip_power(vrip_chipset_tag_t, int, int); 86 vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int, 87 int, int(*)(void*), void*); 88 void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t); 89 void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int); 90 void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t, 91 u_int32_t, int); 92 void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t, 93 u_int32_t*); 94 void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t); 95 void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t); 96 void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t); 97 void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t); 98 void __vrip_dump_level2mask(vrip_chipset_tag_t, void *); 99 100 struct vrip_softc *the_vrip_sc = NULL; 101 102 static const struct vrip_chipset_tag vrip_chipset_methods = { 103 .vc_power = __vrip_power, 104 .vc_intr_establish = __vrip_intr_establish, 105 .vc_intr_disestablish = __vrip_intr_disestablish, 106 .vc_intr_setmask1 = __vrip_intr_setmask1, 107 .vc_intr_setmask2 = __vrip_intr_setmask2, 108 .vc_intr_getstatus2 = __vrip_intr_getstatus2, 109 .vc_register_cmu = __vrip_register_cmu, 110 .vc_register_gpio = __vrip_register_gpio, 111 .vc_register_dmaau = __vrip_register_dmaau, 112 .vc_register_dcu = __vrip_register_dcu, 113 }; 114 115 #ifdef SINGLE_VRIP_BASE 116 CFATTACH_DECL_NEW(vrip, sizeof(struct vrip_softc), 117 vripmatch, vripattach, NULL, NULL); 118 119 static const struct vrip_unit vrip_units[] = { 120 [VRIP_UNIT_PMU] = { "pmu", 121 { VRIP_INTR_POWER, VRIP_INTR_BAT, }, }, 122 [VRIP_UNIT_RTC] = { "rtc", 123 { VRIP_INTR_RTCL1, }, }, 124 [VRIP_UNIT_PIU] = { "piu", 125 { VRIP_INTR_PIU, }, 126 CMUMASK_PIU, 127 ICUPIUINT_REG_W, MPIUINT_REG_W }, 128 [VRIP_UNIT_KIU] = { "kiu", 129 { VRIP_INTR_KIU, }, 130 CMUMASK_KIU, 131 KIUINT_REG_W, MKIUINT_REG_W }, 132 [VRIP_UNIT_SIU] = { "siu", 133 { VRIP_INTR_SIU, }, }, 134 [VRIP_UNIT_GIU] = { "giu", 135 { VRIP_INTR_GIU, }, 136 0, 137 GIUINT_L_REG_W,MGIUINT_L_REG_W, 138 GIUINT_H_REG_W, MGIUINT_H_REG_W }, 139 [VRIP_UNIT_LED] = { "led", 140 { VRIP_INTR_LED, }, }, 141 [VRIP_UNIT_AIU] = { "aiu", 142 { VRIP_INTR_AIU, }, 143 CMUMASK_AIU, 144 AIUINT_REG_W, MAIUINT_REG_W }, 145 [VRIP_UNIT_FIR] = { "fir", 146 { VRIP_INTR_FIR, }, 147 CMUMASK_FIR, 148 FIRINT_REG_W, MFIRINT_REG_W }, 149 [VRIP_UNIT_DSIU]= { "dsiu", 150 { VRIP_INTR_DSIU, }, 151 CMUMASK_DSIU, 152 DSIUINT_REG_W, MDSIUINT_REG_W }, 153 [VRIP_UNIT_PCIU]= { "pciu", 154 { VRIP_INTR_PCI, }, 155 CMUMASK_PCIU, 156 PCIINT_REG_W, MPCIINT_REG_W }, 157 [VRIP_UNIT_SCU] = { "scu", 158 { VRIP_INTR_SCU, }, 159 0, 160 SCUINT_REG_W, MSCUINT_REG_W }, 161 [VRIP_UNIT_CSI] = { "csi", 162 { VRIP_INTR_CSI, }, 163 CMUMASK_CSI, 164 CSIINT_REG_W, MCSIINT_REG_W }, 165 [VRIP_UNIT_BCU] = { "bcu", 166 { VRIP_INTR_BCU, }, 167 0, 168 BCUINT_REG_W, MBCUINT_REG_W }, 169 }; 170 171 void 172 vripattach(device_t parent, device_t self, void *aux) 173 { 174 struct vrip_softc *sc = device_private(self); 175 176 printf("\n"); 177 178 sc->sc_units = vrip_units; 179 sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit); 180 sc->sc_icu_addr = VRIP_ICU_ADDR; 181 sc->sc_sysint2 = SYSINT2_REG_W; 182 sc->sc_msysint2 = MSYSINT2_REG_W; 183 184 vripattach_common(parent, self, aux); 185 } 186 #endif /* SINGLE_VRIP_BASE */ 187 188 int 189 vripmatch(device_t parent, cfdata_t match, void *aux) 190 { 191 struct mainbus_attach_args *ma = aux; 192 193 #if defined(SINGLE_VRIP_BASE) && defined(TX39XX) 194 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 195 return (0); 196 #endif /* SINGLE_VRIP_BASE && TX39XX */ 197 if (strcmp(ma->ma_name, match->cf_name)) 198 return (0); 199 200 return (1); 201 } 202 203 void 204 vripattach_common(device_t parent, device_t self, void *aux) 205 { 206 struct mainbus_attach_args *ma = aux; 207 struct vrip_softc *sc = device_private(self); 208 209 sc->sc_chipset = vrip_chipset_methods; /* structure assignment */ 210 sc->sc_chipset.vc_sc = sc; 211 212 #ifdef DIAGNOSTIC 213 if (sc->sc_icu_addr == 0 || 214 sc->sc_sysint2 == 0 || 215 sc->sc_msysint2 == 0) 216 panic("vripattach: missing register info."); 217 #endif /* DIAGNOSTIC */ 218 219 /* 220 * Map ICU (Interrupt Control Unit) register space. 221 */ 222 sc->sc_iot = ma->ma_iot; 223 if (bus_space_map(sc->sc_iot, sc->sc_icu_addr, 224 0x20 /*XXX lower area only*/, 225 0, /* no flags */ 226 &sc->sc_ioh)) { 227 printf("vripattach: can't map ICU register.\n"); 228 return; 229 } 230 231 /* 232 * Disable all Level 1 interrupts. 233 */ 234 sc->sc_intrmask = 0; 235 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 236 bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_msysint2, 0x0000); 237 /* 238 * Level 1 interrupts are redirected to HwInt0 239 */ 240 vr_intr_establish(VR_INTR0, vrip_intr, sc); 241 the_vrip_sc = sc; 242 /* 243 * Attach each devices 244 * GIU CMU DMAAU DCU interface interface is used by other system 245 * device. so attach first 246 */ 247 sc->sc_pri = 2; 248 config_search_ia(vrip_search, self, "vripif", vrip_print); 249 /* Other system devices. */ 250 sc->sc_pri = 1; 251 config_search_ia(vrip_search, self, "vripif", vrip_print); 252 } 253 254 int 255 vrip_print(void *aux, const char *hoge) 256 { 257 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 258 bus_addr_t endaddr, mask; 259 260 if (va->va_addr != VRIPIFCF_ADDR_DEFAULT) 261 aprint_normal(" addr 0x%08lx", va->va_addr); 262 if (va->va_size != VRIPIFCF_SIZE_DEFAULT) { 263 endaddr = (va->va_addr + va->va_size - 1); 264 mask = ((va->va_addr ^ endaddr) & 0xff0000) ? 0xffffff:0xffff; 265 aprint_normal("-%04lx", endaddr & mask); 266 } 267 if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT) 268 aprint_normal(", 0x%08lx", va->va_addr2); 269 if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT) 270 aprint_normal("-%04lx", 271 (va->va_addr2 + va->va_size2 - 1) & 0xffff); 272 273 return (UNCONF); 274 } 275 276 int 277 vrip_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 278 { 279 struct vrip_softc *sc = device_private(parent); 280 struct vrip_attach_args va; 281 platid_mask_t mask; 282 283 if (cf->cf_loc[VRIPIFCF_PLATFORM] != VRIPIFCF_PLATFORM_DEFAULT) { 284 mask = PLATID_DEREF(cf->cf_loc[VRIPIFCF_PLATFORM]); 285 if (platid_match(&platid, &mask) == 0) 286 return (0); 287 } 288 289 memset(&va, 0, sizeof(va)); 290 va.va_vc = &sc->sc_chipset; 291 va.va_iot = sc->sc_iot; 292 va.va_unit = cf->cf_loc[VRIPIFCF_UNIT]; 293 va.va_addr = cf->cf_loc[VRIPIFCF_ADDR]; 294 va.va_size = cf->cf_loc[VRIPIFCF_SIZE]; 295 va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2]; 296 va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2]; 297 va.va_gpio_chips = sc->sc_gpio_chips; 298 va.va_cc = sc->sc_chipset.vc_cc; 299 va.va_ac = sc->sc_chipset.vc_ac; 300 va.va_dc = sc->sc_chipset.vc_dc; 301 if ((config_match(parent, cf, &va) == sc->sc_pri)) 302 config_attach(parent, cf, &va, vrip_print); 303 304 return (0); 305 } 306 307 int 308 __vrip_power(vrip_chipset_tag_t vc, int unit, int onoff) 309 { 310 struct vrip_softc *sc = vc->vc_sc; 311 const struct vrip_unit *vu; 312 313 if (sc->sc_chipset.vc_cc == NULL) 314 return (0); /* You have no clock mask unit yet. */ 315 if (!VALID_UNIT(sc, unit)) 316 return (0); 317 vu = &sc->sc_units[unit]; 318 319 return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc, 320 vu->vu_clkmask, onoff); 321 } 322 323 vrip_intr_handle_t 324 __vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level, 325 int (*ih_fun)(void *), void *ih_arg) 326 { 327 struct vrip_softc *sc = vc->vc_sc; 328 const struct vrip_unit *vu; 329 struct intrhand *ih; 330 331 if (!VALID_UNIT(sc, unit)) 332 return (NULL); 333 vu = &sc->sc_units[unit]; 334 ih = &sc->sc_intrhands[vu->vu_intr[line]]; 335 if (ih->ih_fun) /* Can't share level 1 interrupt */ 336 return (NULL); 337 ih->ih_fun = ih_fun; 338 ih->ih_arg = ih_arg; 339 ih->ih_unit = vu; 340 341 /* Mask level 2 interrupt mask register. (disable interrupt) */ 342 vrip_intr_setmask2(vc, ih, ~0, 0); 343 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 344 vrip_intr_setmask1(vc, ih, 1); 345 346 return ((void *)ih); 347 } 348 349 void 350 __vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 351 { 352 struct intrhand *ih = handle; 353 354 ih->ih_fun = NULL; 355 ih->ih_arg = NULL; 356 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 357 vrip_intr_setmask2(vc, ih, ~0, 0); 358 /* Mask Level 1 interrupt mask register (disable interrupt) */ 359 vrip_intr_setmask1(vc, ih, 0); 360 } 361 362 void 363 vrip_intr_suspend(void) 364 { 365 struct vrip_softc *sc = the_vrip_sc; 366 bus_space_tag_t iot = sc->sc_iot; 367 bus_space_handle_t ioh = sc->sc_ioh; 368 369 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 370 bus_space_write_2 (iot, ioh, sc->sc_msysint2, 0); 371 } 372 373 void 374 vrip_intr_resume(void) 375 { 376 struct vrip_softc *sc = the_vrip_sc; 377 u_int32_t reg = sc->sc_intrmask; 378 bus_space_tag_t iot = sc->sc_iot; 379 bus_space_handle_t ioh = sc->sc_ioh; 380 381 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 382 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 383 } 384 385 /* Set level 1 interrupt mask. */ 386 void 387 __vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 388 int enable) 389 { 390 struct vrip_softc *sc = vc->vc_sc; 391 struct intrhand *ih = handle; 392 int level1 = ih - sc->sc_intrhands; 393 bus_space_tag_t iot = sc->sc_iot; 394 bus_space_handle_t ioh = sc->sc_ioh; 395 u_int32_t reg = sc->sc_intrmask; 396 397 DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n", 398 enable ? "enable" : "disable", level1)); 399 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 400 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2) << 16)&0xffff0000); 401 if (enable) 402 reg |= (1 << level1); 403 else { 404 reg &= ~(1 << level1); 405 } 406 sc->sc_intrmask = reg; 407 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 408 bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff); 409 DBG_BIT_PRINT(reg); 410 411 return; 412 } 413 414 void 415 __vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle) 416 { 417 struct vrip_softc *sc = vc->vc_sc; 418 struct intrhand *ih = handle; 419 const struct vrip_unit *vu = ih->ih_unit; 420 u_int32_t reg; 421 422 if (vu->vu_mlreg) { 423 DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0])); 424 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 425 if (vu->vu_mhreg) { /* GIU [16:31] case only */ 426 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 427 vu->vu_mhreg) << 16); 428 dbg_bit_print(reg); 429 } else 430 dbg_bit_print(reg); 431 } 432 } 433 434 /* Get level 2 interrupt status */ 435 void 436 __vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 437 u_int32_t *mask /* Level 2 mask */) 438 { 439 struct vrip_softc *sc = vc->vc_sc; 440 struct intrhand *ih = handle; 441 const struct vrip_unit *vu = ih->ih_unit; 442 u_int32_t reg; 443 444 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 445 vu->vu_lreg); 446 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 447 vu->vu_hreg) << 16)&0xffff0000); 448 /* dbg_bit_print(reg);*/ 449 *mask = reg; 450 } 451 452 /* Set level 2 interrupt mask. */ 453 void 454 __vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle, 455 u_int32_t mask /* Level 2 mask */, int onoff) 456 { 457 struct vrip_softc *sc = vc->vc_sc; 458 struct intrhand *ih = handle; 459 const struct vrip_unit *vu = ih->ih_unit; 460 u_int16_t reg; 461 462 DPRINTF(("vrip_intr_setmask2:\n")); 463 DUMP_LEVEL2MASK(vc, handle); 464 #ifdef WINCE_DEFAULT_SETTING 465 #warning WINCE_DEFAULT_SETTING 466 #else 467 if (vu->vu_mlreg) { 468 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg); 469 if (onoff) 470 reg |= (mask&0xffff); 471 else 472 reg &= ~(mask&0xffff); 473 bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg); 474 if (vu->vu_mhreg != 0) { /* GIU [16:31] case only */ 475 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 476 vu->vu_mhreg); 477 if (onoff) 478 reg |= ((mask >> 16) & 0xffff); 479 else 480 reg &= ~((mask >> 16) & 0xffff); 481 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 482 vu->vu_mhreg, reg); 483 } 484 } 485 #endif /* WINCE_DEFAULT_SETTING */ 486 DUMP_LEVEL2MASK(vc, handle); 487 488 return; 489 } 490 491 int 492 vrip_intr(void *arg, vaddr_t pc, u_int32_t status) 493 { 494 struct vrip_softc *sc = (struct vrip_softc *)arg; 495 bus_space_tag_t iot = sc->sc_iot; 496 bus_space_handle_t ioh = sc->sc_ioh; 497 int i; 498 u_int32_t reg, mask; 499 /* 500 * Read level1 interrupt status. 501 */ 502 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 503 ((bus_space_read_2 (iot, ioh, sc->sc_sysint2)<< 16)&0xffff0000); 504 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 505 ((bus_space_read_2 (iot, ioh, sc->sc_msysint2)<< 16)&0xffff0000); 506 reg &= mask; 507 508 /* 509 * Dispatch each handler. 510 */ 511 for (i = 0; i < 32; i++) { 512 register struct intrhand *ih = &sc->sc_intrhands[i]; 513 if (ih->ih_fun && (reg & (1 << i))) { 514 ih->ih_fun(ih->ih_arg); 515 } 516 } 517 518 return (1); 519 } 520 521 void 522 __vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu) 523 { 524 struct vrip_softc *sc = vc->vc_sc; 525 526 sc->sc_chipset.vc_cc = cmu; 527 } 528 529 void 530 __vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip) 531 { 532 struct vrip_softc *sc = vc->vc_sc; 533 534 if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid) 535 panic("%s: '%s' has unknown id, %d", __func__, 536 chip->hc_name, chip->hc_chipid); 537 sc->sc_gpio_chips[chip->hc_chipid] = chip; 538 } 539 540 void 541 __vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau) 542 { 543 struct vrip_softc *sc = vc->vc_sc; 544 545 sc->sc_chipset.vc_ac = dmaau; 546 } 547 548 void 549 __vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu) 550 { 551 struct vrip_softc *sc = vc->vc_sc; 552 553 sc->sc_chipset.vc_dc = dcu; 554 } 555
Indexes created Mon Sep 29 21:09:56 GMT 2025