vrip.c revision 1.6
1 /* $NetBSD: vrip.c,v 1.6 2000/03/10 09:18:00 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/reboot.h> 40 41 #include <machine/cpu.h> 42 #include <machine/bus.h> 43 #include <machine/autoconf.h> 44 45 #include <hpcmips/vr/vr.h> 46 #include <hpcmips/vr/vripreg.h> 47 #include <hpcmips/vr/vripvar.h> 48 #include <hpcmips/vr/icureg.h> 49 #include "locators.h" 50 51 #define VRIPDEBUG 52 #ifdef VRIPDEBUG 53 #ifndef VRIPDEBUG_CONF 54 #define VRIPDEBUG_CONF 0 55 #endif /* VRIPDEBUG_CONF */ 56 int vrip_debug = VRIPDEBUG_CONF; 57 #define DPRINTF(arg) if (vrip_debug) printf arg; 58 #define DBITDISP32(reg) if (vrip_debug) bitdisp32(reg); 59 #define DDUMP_LEVEL2MASK(sc,arg) if (vrip_debug) vrip_dump_level2mask(sc,arg) 60 #else 61 #define DPRINTF(arg) 62 #define DBITDISP32(arg) 63 #define DDUMP_LEVEL2MASK(sc,arg) 64 #endif 65 66 int vripmatch __P((struct device*, struct cfdata*, void*)); 67 void vripattach __P((struct device*, struct device*, void*)); 68 int vrip_print __P((void*, const char*)); 69 int vrip_search __P((struct device*, struct cfdata*, void*)); 70 int vrip_intr __P((void*, u_int32_t, u_int32_t)); 71 72 static void vrip_dump_level2mask __P((vrip_chipset_tag_t, void*)); 73 74 struct cfattach vrip_ca = { 75 sizeof(struct vrip_softc), vripmatch, vripattach 76 }; 77 78 #define MAX_LEVEL1 32 79 80 struct vrip_softc *the_vrip_sc = NULL; 81 82 static struct intrhand { 83 int (*ih_fun) __P((void *)); 84 void *ih_arg; 85 int ih_l1line; 86 int ih_ipl; 87 bus_addr_t ih_lreg; 88 bus_addr_t ih_mlreg; 89 bus_addr_t ih_hreg; 90 bus_addr_t ih_mhreg; 91 } intrhand[MAX_LEVEL1] = { 92 [5] = { 0, 0, 0, 0, ICUPIUINT_REG_W, MPIUINT_REG_W }, 93 [6] = { 0, 0, 0, 0, AIUINT_REG_W, MAIUINT_REG_W }, 94 [7] = { 0, 0, 0, 0, KIUINT_REG_W, MKIUINT_REG_W }, 95 [8] = { 0, 0, 0, 0, GIUINT_L_REG_W, MGIUINT_L_REG_W, GIUINT_H_REG_W, MGIUINT_H_REG_W }, 96 [20] = { 0, 0, 0, 0, FIRINT_REG_W, MFIRINT_REG_W }, 97 [21] = { 0, 0, 0, 0, DSIUINT_REG_W, MDSIUINT_REG_W } 98 }; 99 #define LEGAL_LEVEL1(x) ((x) >= 0 && (x) < MAX_LEVEL1) 100 101 void 102 bitdisp16 (u_int16_t a) 103 { 104 u_int16_t j; 105 for (j = 0x8000; j > 0; j >>=1) 106 printf ("%c", a&j ?'|':'.'); 107 printf ("\n"); 108 } 109 110 void 111 bitdisp32 (u_int32_t a) 112 { 113 u_int32_t j; 114 for (j = 0x80000000; j > 0; j >>=1) 115 printf ("%c" , a&j ? '|' : '.'); 116 printf ("\n"); 117 } 118 119 void 120 bitdisp64(u_int32_t a[2]) 121 { 122 u_int32_t j; 123 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 124 printf("%c" , a[1]&j ?';':',' ); 125 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 126 printf("%c" , a[0]&j ?'|':'.' ); 127 printf("\n"); 128 } 129 130 int 131 vripmatch(parent, match, aux) 132 struct device *parent; 133 struct cfdata *match; 134 void *aux; 135 { 136 struct mainbus_attach_args *ma = aux; 137 138 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 139 return 0; 140 return 1; 141 } 142 143 void 144 vripattach(parent, self, aux) 145 struct device *parent; 146 struct device *self; 147 void *aux; 148 { 149 struct mainbus_attach_args *ma = aux; 150 struct vrip_softc *sc = (struct vrip_softc*)self; 151 152 printf("\n"); 153 /* 154 * Map ICU (Interrupt Control Unit) register space. 155 */ 156 sc->sc_iot = ma->ma_iot; 157 if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR, 0x20/*XXX lower area only*/, 158 0, /* no flags */ 159 &sc->sc_ioh)) { 160 printf("vripattach: can't map ICU register.\n"); 161 return; 162 } 163 164 /* 165 * Disable all Level 1 interrupts. 166 */ 167 sc->sc_intrmask = 0; 168 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 169 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000); 170 /* 171 * Level 1 interrupts are redirected to HwInt0 172 */ 173 vr_intr_establish(VR_INTR0, vrip_intr, self); 174 the_vrip_sc = sc; 175 /* 176 * Attach each devices 177 */ 178 /* GIU CMU interface interface is used by other system device. so attach first */ 179 sc->sc_pri = 2; 180 config_search(vrip_search, self, vrip_print); 181 /* Other system devices. */ 182 sc->sc_pri = 1; 183 config_search(vrip_search, self, vrip_print); 184 } 185 186 int 187 vrip_print(aux, hoge) 188 void *aux; 189 const char *hoge; 190 { 191 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 192 193 if (va->va_addr) 194 printf(" addr 0x%lx", va->va_addr); 195 if (va->va_size > 1) 196 printf("-0x%lx", va->va_addr + va->va_size - 1); 197 if (va->va_intr != VRIPCF_INTR_DEFAULT) 198 printf(" intr %d", va->va_intr); 199 return (UNCONF); 200 } 201 202 int 203 vrip_search(parent, cf, aux) 204 struct device *parent; 205 struct cfdata *cf; 206 void *aux; 207 { 208 struct vrip_softc *sc = (struct vrip_softc *)parent; 209 struct vrip_attach_args va; 210 211 va.va_vc = sc; 212 va.va_iot = sc->sc_iot; 213 va.va_addr = cf->cf_loc[VRIPCF_ADDR]; 214 va.va_size = cf->cf_loc[VRIPCF_SIZE]; 215 va.va_intr = cf->cf_loc[VRIPCF_INTR]; 216 va.va_addr2 = cf->cf_loc[VRIPCF_ADDR2]; 217 va.va_size2 = cf->cf_loc[VRIPCF_SIZE2]; 218 va.va_gc = sc->sc_gc; 219 va.va_gf = sc->sc_gf; 220 va.va_cc = sc->sc_cc; 221 va.va_cf = sc->sc_cf; 222 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 223 config_attach(parent, cf, &va, vrip_print); 224 225 return 0; 226 } 227 228 void * 229 vrip_intr_establish(vc, intr, level, ih_fun, ih_arg) 230 vrip_chipset_tag_t vc; 231 int intr; 232 int level; /* XXX not yet */ 233 int (*ih_fun) __P((void *)); 234 void *ih_arg; 235 { 236 struct intrhand *ih; 237 238 if (!LEGAL_LEVEL1(intr)) 239 return 0; 240 ih = &intrhand[intr]; 241 if (ih->ih_fun) /* Can't share level 1 interrupt */ 242 return 0; 243 ih->ih_l1line = intr; 244 ih->ih_fun = ih_fun; 245 ih->ih_arg = ih_arg; 246 247 /* Mask level 2 interrupt mask register. (disable interrupt) */ 248 vrip_intr_setmask2(vc, ih, ~0, 0); 249 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 250 vrip_intr_setmask1(vc, ih, 1); 251 252 return (void *)ih; 253 } 254 255 void 256 vrip_intr_disestablish(vc, arg) 257 vrip_chipset_tag_t vc; 258 void *arg; 259 { 260 struct intrhand *ih = arg; 261 ih->ih_fun = NULL; 262 ih->ih_arg = NULL; 263 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 264 vrip_intr_setmask2(vc, ih, ~0, 0); 265 /* Mask Level 1 interrupt mask register (disable interrupt) */ 266 vrip_intr_setmask1(vc, ih, 0); 267 } 268 269 void 270 vrip_intr_suspend() 271 { 272 bus_space_tag_t iot = the_vrip_sc->sc_iot; 273 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 274 275 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 276 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0); 277 } 278 279 void 280 vrip_intr_resume() 281 { 282 u_int32_t reg = the_vrip_sc->sc_intrmask; 283 bus_space_tag_t iot = the_vrip_sc->sc_iot; 284 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 285 286 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 287 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 288 } 289 290 /* Set level 1 interrupt mask. */ 291 void 292 vrip_intr_setmask1(vc, arg, enable) 293 vrip_chipset_tag_t vc; 294 void *arg; 295 int enable; 296 { 297 struct vrip_softc *sc = (void*)vc; 298 struct intrhand *ih = arg; 299 int level1 = ih->ih_l1line; 300 bus_space_tag_t iot = sc->sc_iot; 301 bus_space_handle_t ioh = sc->sc_ioh; 302 u_int32_t reg = sc->sc_intrmask; 303 304 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 305 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 306 if (enable) 307 reg |= (1 << level1); 308 else { 309 reg &= ~(1 << level1); 310 } 311 sc->sc_intrmask = reg; 312 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 313 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 314 DBITDISP32(reg); 315 316 return; 317 } 318 319 static void 320 vrip_dump_level2mask (vc, arg) 321 vrip_chipset_tag_t vc; 322 void *arg; 323 { 324 struct vrip_softc *sc = (void*)vc; 325 struct intrhand *ih = arg; 326 u_int32_t reg; 327 328 if (ih->ih_mlreg) { 329 printf ("level1[%d] level2 mask:", ih->ih_l1line); 330 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 331 if (ih->ih_mhreg) { /* GIU [16:31] case only */ 332 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg) << 16); 333 bitdisp32(reg); 334 } else 335 bitdisp16(reg); 336 } 337 } 338 339 /* Get level 2 interrupt status */ 340 void 341 vrip_intr_get_status2(vc, arg, mask) 342 vrip_chipset_tag_t vc; 343 void *arg; 344 u_int32_t *mask; /* Level 2 mask */ 345 { 346 struct vrip_softc *sc = (void*)vc; 347 struct intrhand *ih = arg; 348 u_int32_t reg; 349 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 350 ih->ih_lreg); 351 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 352 ih->ih_hreg) << 16)&0xffff0000); 353 /* bitdisp32(reg);*/ 354 *mask = reg; 355 } 356 357 /* Set level 2 interrupt mask. */ 358 void 359 vrip_intr_setmask2(vc, arg, mask, onoff) 360 vrip_chipset_tag_t vc; 361 void *arg; 362 u_int32_t mask; /* Level 2 mask */ 363 { 364 struct vrip_softc *sc = (void*)vc; 365 struct intrhand *ih = arg; 366 u_int16_t reg; 367 368 DPRINTF(("vrip_intr_setmask2:\n")); 369 DDUMP_LEVEL2MASK(vc, arg); 370 #ifdef WINCE_DEFAULT_SETTING 371 #warning WINCE_DEFAULT_SETTING 372 #else 373 if (ih->ih_mlreg) { 374 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 375 if (onoff) 376 reg |= (mask&0xffff); 377 else 378 reg &= ~(mask&0xffff); 379 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg, reg); 380 if (ih->ih_mhreg != -1) { /* GIU [16:31] case only */ 381 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg); 382 if (onoff) 383 reg |= ((mask >> 16) & 0xffff); 384 else 385 reg &= ~((mask >> 16) & 0xffff); 386 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 387 ih->ih_mhreg, reg); 388 } 389 } 390 #endif /* WINCE_DEFAULT_SETTING */ 391 DDUMP_LEVEL2MASK(vc, arg); 392 393 return; 394 } 395 396 int 397 vrip_intr(arg, pc, statusReg) 398 void *arg; 399 u_int32_t pc; 400 u_int32_t statusReg; 401 { 402 struct vrip_softc *sc = (struct vrip_softc*)arg; 403 bus_space_tag_t iot = sc->sc_iot; 404 bus_space_handle_t ioh = sc->sc_ioh; 405 int i; 406 u_int32_t reg, mask; 407 /* 408 * Read level1 interrupt status. 409 */ 410 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 411 ((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000); 412 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 413 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 414 reg &= mask; 415 416 /* 417 * Dispatch each handler. 418 */ 419 for (i = 0; i < 32; i++) { 420 register struct intrhand *ih = &intrhand[i]; 421 if (ih->ih_fun && (reg & (1 << i))) { 422 ih->ih_fun(ih->ih_arg); 423 } 424 } 425 return 1; 426 } 427 428 void 429 vrip_cmu_function_register(vc, func, arg) 430 vrip_chipset_tag_t vc; 431 vrcmu_function_tag_t func; 432 vrcmu_chipset_tag_t arg; 433 { 434 struct vrip_softc *sc = (void*)vc; 435 sc->sc_cf = func; 436 sc->sc_cc = arg; 437 } 438 439 void 440 vrip_giu_function_register(vc, func, arg) 441 vrip_chipset_tag_t vc; 442 vrgiu_function_tag_t func; 443 vrgiu_chipset_tag_t arg; 444 { 445 struct vrip_softc *sc = (void*)vc; 446 sc->sc_gf = func; 447 sc->sc_gc = arg; 448 } 449 450
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