vrip.c revision 1.7
1 /* $NetBSD: vrip.c,v 1.7 2001/04/18 10:46:00 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 #include "opt_vr41xx.h" 37 #include "opt_tx39xx.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/reboot.h> 43 44 #include <machine/cpu.h> 45 #include <machine/bus.h> 46 #include <machine/autoconf.h> 47 48 #include <hpcmips/vr/vr.h> 49 #include <hpcmips/vr/vripreg.h> 50 #include <hpcmips/vr/vripvar.h> 51 #include <hpcmips/vr/icureg.h> 52 #include "locators.h" 53 54 #define VRIPDEBUG 55 #ifdef VRIPDEBUG 56 #ifndef VRIPDEBUG_CONF 57 #define VRIPDEBUG_CONF 0 58 #endif /* VRIPDEBUG_CONF */ 59 int vrip_debug = VRIPDEBUG_CONF; 60 #define DPRINTF(arg) if (vrip_debug) printf arg; 61 #define DBITDISP32(reg) if (vrip_debug) bitdisp32(reg); 62 #define DDUMP_LEVEL2MASK(sc,arg) if (vrip_debug) vrip_dump_level2mask(sc,arg) 63 #else 64 #define DPRINTF(arg) 65 #define DBITDISP32(arg) 66 #define DDUMP_LEVEL2MASK(sc,arg) 67 #endif 68 69 int vripmatch __P((struct device*, struct cfdata*, void*)); 70 void vripattach __P((struct device*, struct device*, void*)); 71 int vrip_print __P((void*, const char*)); 72 int vrip_search __P((struct device*, struct cfdata*, void*)); 73 int vrip_intr __P((void*, u_int32_t, u_int32_t)); 74 75 static void vrip_dump_level2mask __P((vrip_chipset_tag_t, void*)); 76 77 struct cfattach vrip_ca = { 78 sizeof(struct vrip_softc), vripmatch, vripattach 79 }; 80 81 #define MAX_LEVEL1 32 82 83 struct vrip_softc *the_vrip_sc = NULL; 84 85 static struct intrhand { 86 int (*ih_fun) __P((void *)); 87 void *ih_arg; 88 int ih_l1line; 89 int ih_ipl; 90 bus_addr_t ih_lreg; 91 bus_addr_t ih_mlreg; 92 bus_addr_t ih_hreg; 93 bus_addr_t ih_mhreg; 94 } intrhand[MAX_LEVEL1] = { 95 [5] = { 0, 0, 0, 0, ICUPIUINT_REG_W, MPIUINT_REG_W }, 96 [6] = { 0, 0, 0, 0, AIUINT_REG_W, MAIUINT_REG_W }, 97 [7] = { 0, 0, 0, 0, KIUINT_REG_W, MKIUINT_REG_W }, 98 [8] = { 0, 0, 0, 0, GIUINT_L_REG_W, MGIUINT_L_REG_W, GIUINT_H_REG_W, MGIUINT_H_REG_W }, 99 [20] = { 0, 0, 0, 0, FIRINT_REG_W, MFIRINT_REG_W }, 100 [21] = { 0, 0, 0, 0, DSIUINT_REG_W, MDSIUINT_REG_W } 101 }; 102 #define LEGAL_LEVEL1(x) ((x) >= 0 && (x) < MAX_LEVEL1) 103 104 void 105 bitdisp16 (u_int16_t a) 106 { 107 u_int16_t j; 108 for (j = 0x8000; j > 0; j >>=1) 109 printf ("%c", a&j ?'|':'.'); 110 printf ("\n"); 111 } 112 113 void 114 bitdisp32 (u_int32_t a) 115 { 116 u_int32_t j; 117 for (j = 0x80000000; j > 0; j >>=1) 118 printf ("%c" , a&j ? '|' : '.'); 119 printf ("\n"); 120 } 121 122 void 123 bitdisp64(u_int32_t a[2]) 124 { 125 u_int32_t j; 126 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 127 printf("%c" , a[1]&j ?';':',' ); 128 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 129 printf("%c" , a[0]&j ?'|':'.' ); 130 printf("\n"); 131 } 132 133 int 134 vripmatch(parent, match, aux) 135 struct device *parent; 136 struct cfdata *match; 137 void *aux; 138 { 139 struct mainbus_attach_args *ma = aux; 140 141 #ifdef TX39XX 142 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 143 return 1; 144 #endif /* !TX39XX */ 145 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 146 return 0; 147 return 1; 148 } 149 150 void 151 vripattach(parent, self, aux) 152 struct device *parent; 153 struct device *self; 154 void *aux; 155 { 156 struct mainbus_attach_args *ma = aux; 157 struct vrip_softc *sc = (struct vrip_softc*)self; 158 159 printf("\n"); 160 /* 161 * Map ICU (Interrupt Control Unit) register space. 162 */ 163 sc->sc_iot = ma->ma_iot; 164 if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR, 0x20/*XXX lower area only*/, 165 0, /* no flags */ 166 &sc->sc_ioh)) { 167 printf("vripattach: can't map ICU register.\n"); 168 return; 169 } 170 171 /* 172 * Disable all Level 1 interrupts. 173 */ 174 sc->sc_intrmask = 0; 175 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 176 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000); 177 /* 178 * Level 1 interrupts are redirected to HwInt0 179 */ 180 vr_intr_establish(VR_INTR0, vrip_intr, self); 181 the_vrip_sc = sc; 182 /* 183 * Attach each devices 184 */ 185 /* GIU CMU interface interface is used by other system device. so attach first */ 186 sc->sc_pri = 2; 187 config_search(vrip_search, self, vrip_print); 188 /* Other system devices. */ 189 sc->sc_pri = 1; 190 config_search(vrip_search, self, vrip_print); 191 } 192 193 int 194 vrip_print(aux, hoge) 195 void *aux; 196 const char *hoge; 197 { 198 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 199 200 if (va->va_addr) 201 printf(" addr 0x%lx", va->va_addr); 202 if (va->va_size > 1) 203 printf("-0x%lx", va->va_addr + va->va_size - 1); 204 if (va->va_intr != VRIPCF_INTR_DEFAULT) 205 printf(" intr %d", va->va_intr); 206 return (UNCONF); 207 } 208 209 int 210 vrip_search(parent, cf, aux) 211 struct device *parent; 212 struct cfdata *cf; 213 void *aux; 214 { 215 struct vrip_softc *sc = (struct vrip_softc *)parent; 216 struct vrip_attach_args va; 217 218 va.va_vc = sc; 219 va.va_iot = sc->sc_iot; 220 va.va_addr = cf->cf_loc[VRIPCF_ADDR]; 221 va.va_size = cf->cf_loc[VRIPCF_SIZE]; 222 va.va_intr = cf->cf_loc[VRIPCF_INTR]; 223 va.va_addr2 = cf->cf_loc[VRIPCF_ADDR2]; 224 va.va_size2 = cf->cf_loc[VRIPCF_SIZE2]; 225 va.va_gc = sc->sc_gc; 226 va.va_gf = sc->sc_gf; 227 va.va_cc = sc->sc_cc; 228 va.va_cf = sc->sc_cf; 229 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 230 config_attach(parent, cf, &va, vrip_print); 231 232 return 0; 233 } 234 235 void * 236 vrip_intr_establish(vc, intr, level, ih_fun, ih_arg) 237 vrip_chipset_tag_t vc; 238 int intr; 239 int level; /* XXX not yet */ 240 int (*ih_fun) __P((void *)); 241 void *ih_arg; 242 { 243 struct intrhand *ih; 244 245 if (!LEGAL_LEVEL1(intr)) 246 return 0; 247 ih = &intrhand[intr]; 248 if (ih->ih_fun) /* Can't share level 1 interrupt */ 249 return 0; 250 ih->ih_l1line = intr; 251 ih->ih_fun = ih_fun; 252 ih->ih_arg = ih_arg; 253 254 /* Mask level 2 interrupt mask register. (disable interrupt) */ 255 vrip_intr_setmask2(vc, ih, ~0, 0); 256 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 257 vrip_intr_setmask1(vc, ih, 1); 258 259 return (void *)ih; 260 } 261 262 void 263 vrip_intr_disestablish(vc, arg) 264 vrip_chipset_tag_t vc; 265 void *arg; 266 { 267 struct intrhand *ih = arg; 268 ih->ih_fun = NULL; 269 ih->ih_arg = NULL; 270 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 271 vrip_intr_setmask2(vc, ih, ~0, 0); 272 /* Mask Level 1 interrupt mask register (disable interrupt) */ 273 vrip_intr_setmask1(vc, ih, 0); 274 } 275 276 void 277 vrip_intr_suspend() 278 { 279 bus_space_tag_t iot = the_vrip_sc->sc_iot; 280 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 281 282 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 283 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0); 284 } 285 286 void 287 vrip_intr_resume() 288 { 289 u_int32_t reg = the_vrip_sc->sc_intrmask; 290 bus_space_tag_t iot = the_vrip_sc->sc_iot; 291 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 292 293 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 294 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 295 } 296 297 /* Set level 1 interrupt mask. */ 298 void 299 vrip_intr_setmask1(vc, arg, enable) 300 vrip_chipset_tag_t vc; 301 void *arg; 302 int enable; 303 { 304 struct vrip_softc *sc = (void*)vc; 305 struct intrhand *ih = arg; 306 int level1 = ih->ih_l1line; 307 bus_space_tag_t iot = sc->sc_iot; 308 bus_space_handle_t ioh = sc->sc_ioh; 309 u_int32_t reg = sc->sc_intrmask; 310 311 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 312 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 313 if (enable) 314 reg |= (1 << level1); 315 else { 316 reg &= ~(1 << level1); 317 } 318 sc->sc_intrmask = reg; 319 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 320 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 321 DBITDISP32(reg); 322 323 return; 324 } 325 326 static void 327 vrip_dump_level2mask (vc, arg) 328 vrip_chipset_tag_t vc; 329 void *arg; 330 { 331 struct vrip_softc *sc = (void*)vc; 332 struct intrhand *ih = arg; 333 u_int32_t reg; 334 335 if (ih->ih_mlreg) { 336 printf ("level1[%d] level2 mask:", ih->ih_l1line); 337 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 338 if (ih->ih_mhreg) { /* GIU [16:31] case only */ 339 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg) << 16); 340 bitdisp32(reg); 341 } else 342 bitdisp16(reg); 343 } 344 } 345 346 /* Get level 2 interrupt status */ 347 void 348 vrip_intr_get_status2(vc, arg, mask) 349 vrip_chipset_tag_t vc; 350 void *arg; 351 u_int32_t *mask; /* Level 2 mask */ 352 { 353 struct vrip_softc *sc = (void*)vc; 354 struct intrhand *ih = arg; 355 u_int32_t reg; 356 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 357 ih->ih_lreg); 358 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 359 ih->ih_hreg) << 16)&0xffff0000); 360 /* bitdisp32(reg);*/ 361 *mask = reg; 362 } 363 364 /* Set level 2 interrupt mask. */ 365 void 366 vrip_intr_setmask2(vc, arg, mask, onoff) 367 vrip_chipset_tag_t vc; 368 void *arg; 369 u_int32_t mask; /* Level 2 mask */ 370 { 371 struct vrip_softc *sc = (void*)vc; 372 struct intrhand *ih = arg; 373 u_int16_t reg; 374 375 DPRINTF(("vrip_intr_setmask2:\n")); 376 DDUMP_LEVEL2MASK(vc, arg); 377 #ifdef WINCE_DEFAULT_SETTING 378 #warning WINCE_DEFAULT_SETTING 379 #else 380 if (ih->ih_mlreg) { 381 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 382 if (onoff) 383 reg |= (mask&0xffff); 384 else 385 reg &= ~(mask&0xffff); 386 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg, reg); 387 if (ih->ih_mhreg != -1) { /* GIU [16:31] case only */ 388 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg); 389 if (onoff) 390 reg |= ((mask >> 16) & 0xffff); 391 else 392 reg &= ~((mask >> 16) & 0xffff); 393 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 394 ih->ih_mhreg, reg); 395 } 396 } 397 #endif /* WINCE_DEFAULT_SETTING */ 398 DDUMP_LEVEL2MASK(vc, arg); 399 400 return; 401 } 402 403 int 404 vrip_intr(arg, pc, statusReg) 405 void *arg; 406 u_int32_t pc; 407 u_int32_t statusReg; 408 { 409 struct vrip_softc *sc = (struct vrip_softc*)arg; 410 bus_space_tag_t iot = sc->sc_iot; 411 bus_space_handle_t ioh = sc->sc_ioh; 412 int i; 413 u_int32_t reg, mask; 414 /* 415 * Read level1 interrupt status. 416 */ 417 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 418 ((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000); 419 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 420 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 421 reg &= mask; 422 423 /* 424 * Dispatch each handler. 425 */ 426 for (i = 0; i < 32; i++) { 427 register struct intrhand *ih = &intrhand[i]; 428 if (ih->ih_fun && (reg & (1 << i))) { 429 ih->ih_fun(ih->ih_arg); 430 } 431 } 432 return 1; 433 } 434 435 void 436 vrip_cmu_function_register(vc, func, arg) 437 vrip_chipset_tag_t vc; 438 vrcmu_function_tag_t func; 439 vrcmu_chipset_tag_t arg; 440 { 441 struct vrip_softc *sc = (void*)vc; 442 sc->sc_cf = func; 443 sc->sc_cc = arg; 444 } 445 446 void 447 vrip_giu_function_register(vc, func, arg) 448 vrip_chipset_tag_t vc; 449 vrgiu_function_tag_t func; 450 vrgiu_chipset_tag_t arg; 451 { 452 struct vrip_softc *sc = (void*)vc; 453 sc->sc_gf = func; 454 sc->sc_gc = arg; 455 } 456 457
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