vrip.c revision 1.9
1 /* $NetBSD: vrip.c,v 1.9 2001/04/18 11:07:28 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the PocketBSD project 18 * and its contributors. 19 * 4. Neither the name of the project nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 #include "opt_vr41xx.h" 37 #include "opt_tx39xx.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/reboot.h> 43 44 #include <machine/cpu.h> 45 #include <machine/bus.h> 46 #include <machine/autoconf.h> 47 #include <machine/platid.h> 48 #include <machine/platid_mask.h> 49 50 #include <hpcmips/vr/vr.h> 51 #include <hpcmips/vr/vrcpudef.h> 52 #include <hpcmips/vr/vripreg.h> 53 #include <hpcmips/vr/vripvar.h> 54 #include <hpcmips/vr/icureg.h> 55 #include "locators.h" 56 57 #define VRIPDEBUG 58 #ifdef VRIPDEBUG 59 #ifndef VRIPDEBUG_CONF 60 #define VRIPDEBUG_CONF 0 61 #endif /* VRIPDEBUG_CONF */ 62 int vrip_debug = VRIPDEBUG_CONF; 63 #define DPRINTF(arg) if (vrip_debug) printf arg; 64 #define DBITDISP32(reg) if (vrip_debug) bitdisp32(reg); 65 #define DDUMP_LEVEL2MASK(sc,arg) if (vrip_debug) vrip_dump_level2mask(sc,arg) 66 #else 67 #define DPRINTF(arg) 68 #define DBITDISP32(arg) 69 #define DDUMP_LEVEL2MASK(sc,arg) 70 #endif 71 72 int vripmatch __P((struct device*, struct cfdata*, void*)); 73 void vripattach __P((struct device*, struct device*, void*)); 74 int vrip_print __P((void*, const char*)); 75 int vrip_search __P((struct device*, struct cfdata*, void*)); 76 int vrip_intr __P((void*, u_int32_t, u_int32_t)); 77 78 static void vrip_dump_level2mask __P((vrip_chipset_tag_t, void*)); 79 80 struct cfattach vrip_ca = { 81 sizeof(struct vrip_softc), vripmatch, vripattach 82 }; 83 84 #define MAX_LEVEL1 32 85 86 struct vrip_softc *the_vrip_sc = NULL; 87 88 static struct intrhand { 89 int (*ih_fun) __P((void *)); 90 void *ih_arg; 91 int ih_l1line; 92 int ih_ipl; 93 bus_addr_t ih_lreg; 94 bus_addr_t ih_mlreg; 95 bus_addr_t ih_hreg; 96 bus_addr_t ih_mhreg; 97 } intrhand[MAX_LEVEL1] = { 98 [VRIP_INTR_PIU] = { 0, 0, 0, 0, ICUPIUINT_REG_W, MPIUINT_REG_W }, 99 [VRIP_INTR_AIU] = { 0, 0, 0, 0, AIUINT_REG_W, MAIUINT_REG_W }, 100 [VRIP_INTR_KIU] = { 0, 0, 0, 0, KIUINT_REG_W, MKIUINT_REG_W }, 101 [VRIP_INTR_GIU] = { 0, 0, 0, 0, GIUINT_L_REG_W, MGIUINT_L_REG_W, GIUINT_H_REG_W, MGIUINT_H_REG_W }, 102 [VRIP_INTR_FIR] = { 0, 0, 0, 0, FIRINT_REG_W, MFIRINT_REG_W }, 103 [VRIP_INTR_DSIU] = { 0, 0, 0, 0, DSIUINT_REG_W, MDSIUINT_REG_W }, 104 [VRIP_INTR_PCI] = { 0, 0, 0, 0, PCIINT_REG_W, MPCIINT_REG_W }, 105 [VRIP_INTR_SCU] = { 0, 0, 0, 0, SCUINT_REG_W, MSCUINT_REG_W }, 106 [VRIP_INTR_CSI] = { 0, 0, 0, 0, CSIINT_REG_W, MCSIINT_REG_W }, 107 [VRIP_INTR_BCU] = { 0, 0, 0, 0, BCUINT_REG_W, MBCUINT_REG_W } 108 }; 109 110 #define LEGAL_LEVEL1(x) ((x) >= 0 && (x) < MAX_LEVEL1) 111 112 void 113 bitdisp16 (u_int16_t a) 114 { 115 u_int16_t j; 116 for (j = 0x8000; j > 0; j >>=1) 117 printf ("%c", a&j ?'|':'.'); 118 printf ("\n"); 119 } 120 121 void 122 bitdisp32 (u_int32_t a) 123 { 124 u_int32_t j; 125 for (j = 0x80000000; j > 0; j >>=1) 126 printf ("%c" , a&j ? '|' : '.'); 127 printf ("\n"); 128 } 129 130 void 131 bitdisp64(u_int32_t a[2]) 132 { 133 u_int32_t j; 134 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 135 printf("%c" , a[1]&j ?';':',' ); 136 for( j = 0x80000000 ; j > 0 ; j >>=1 ) 137 printf("%c" , a[0]&j ?'|':'.' ); 138 printf("\n"); 139 } 140 141 int 142 vripmatch(parent, match, aux) 143 struct device *parent; 144 struct cfdata *match; 145 void *aux; 146 { 147 struct mainbus_attach_args *ma = aux; 148 149 #ifdef TX39XX 150 if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX)) 151 return 1; 152 #endif /* !TX39XX */ 153 if (strcmp(ma->ma_name, match->cf_driver->cd_name)) 154 return 0; 155 return 1; 156 } 157 158 void 159 vripattach(parent, self, aux) 160 struct device *parent; 161 struct device *self; 162 void *aux; 163 { 164 struct mainbus_attach_args *ma = aux; 165 struct vrip_softc *sc = (struct vrip_softc*)self; 166 167 printf("\n"); 168 /* 169 * Map ICU (Interrupt Control Unit) register space. 170 */ 171 sc->sc_iot = ma->ma_iot; 172 if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR, 0x20/*XXX lower area only*/, 173 0, /* no flags */ 174 &sc->sc_ioh)) { 175 printf("vripattach: can't map ICU register.\n"); 176 return; 177 } 178 179 /* 180 * Disable all Level 1 interrupts. 181 */ 182 sc->sc_intrmask = 0; 183 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000); 184 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000); 185 /* 186 * Level 1 interrupts are redirected to HwInt0 187 */ 188 vr_intr_establish(VR_INTR0, vrip_intr, self); 189 the_vrip_sc = sc; 190 /* 191 * Attach each devices 192 */ 193 /* GIU CMU interface interface is used by other system device. so attach first */ 194 sc->sc_pri = 2; 195 config_search(vrip_search, self, vrip_print); 196 /* Other system devices. */ 197 sc->sc_pri = 1; 198 config_search(vrip_search, self, vrip_print); 199 } 200 201 int 202 vrip_print(aux, hoge) 203 void *aux; 204 const char *hoge; 205 { 206 struct vrip_attach_args *va = (struct vrip_attach_args*)aux; 207 208 if (va->va_addr) 209 printf(" addr 0x%lx", va->va_addr); 210 if (va->va_size > 1) 211 printf("-0x%lx", va->va_addr + va->va_size - 1); 212 if (va->va_intr != VRIPCF_INTR_DEFAULT) 213 printf(" intr %d", va->va_intr); 214 return (UNCONF); 215 } 216 217 int 218 vrip_search(parent, cf, aux) 219 struct device *parent; 220 struct cfdata *cf; 221 void *aux; 222 { 223 struct vrip_softc *sc = (struct vrip_softc *)parent; 224 struct vrip_attach_args va; 225 226 va.va_vc = sc; 227 va.va_iot = sc->sc_iot; 228 va.va_addr = cf->cf_loc[VRIPCF_ADDR]; 229 va.va_size = cf->cf_loc[VRIPCF_SIZE]; 230 va.va_intr = cf->cf_loc[VRIPCF_INTR]; 231 va.va_addr2 = cf->cf_loc[VRIPCF_ADDR2]; 232 va.va_size2 = cf->cf_loc[VRIPCF_SIZE2]; 233 va.va_gc = sc->sc_gc; 234 va.va_gf = sc->sc_gf; 235 va.va_cc = sc->sc_cc; 236 va.va_cf = sc->sc_cf; 237 if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri)) 238 config_attach(parent, cf, &va, vrip_print); 239 240 return 0; 241 } 242 243 void * 244 vrip_intr_establish(vc, intr, level, ih_fun, ih_arg) 245 vrip_chipset_tag_t vc; 246 int intr; 247 int level; /* XXX not yet */ 248 int (*ih_fun) __P((void *)); 249 void *ih_arg; 250 { 251 struct intrhand *ih; 252 253 if (!LEGAL_LEVEL1(intr)) 254 return 0; 255 ih = &intrhand[intr]; 256 if (ih->ih_fun) /* Can't share level 1 interrupt */ 257 return 0; 258 ih->ih_l1line = intr; 259 ih->ih_fun = ih_fun; 260 ih->ih_arg = ih_arg; 261 262 /* Mask level 2 interrupt mask register. (disable interrupt) */ 263 vrip_intr_setmask2(vc, ih, ~0, 0); 264 /* Unmask Level 1 interrupt mask register (enable interrupt) */ 265 vrip_intr_setmask1(vc, ih, 1); 266 267 return (void *)ih; 268 } 269 270 void 271 vrip_intr_disestablish(vc, arg) 272 vrip_chipset_tag_t vc; 273 void *arg; 274 { 275 struct intrhand *ih = arg; 276 ih->ih_fun = NULL; 277 ih->ih_arg = NULL; 278 /* Mask level 2 interrupt mask register(if any). (disable interrupt) */ 279 vrip_intr_setmask2(vc, ih, ~0, 0); 280 /* Mask Level 1 interrupt mask register (disable interrupt) */ 281 vrip_intr_setmask1(vc, ih, 0); 282 } 283 284 void 285 vrip_intr_suspend() 286 { 287 bus_space_tag_t iot = the_vrip_sc->sc_iot; 288 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 289 290 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER)); 291 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0); 292 } 293 294 void 295 vrip_intr_resume() 296 { 297 u_int32_t reg = the_vrip_sc->sc_intrmask; 298 bus_space_tag_t iot = the_vrip_sc->sc_iot; 299 bus_space_handle_t ioh = the_vrip_sc->sc_ioh; 300 301 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 302 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 303 } 304 305 /* Set level 1 interrupt mask. */ 306 void 307 vrip_intr_setmask1(vc, arg, enable) 308 vrip_chipset_tag_t vc; 309 void *arg; 310 int enable; 311 { 312 struct vrip_softc *sc = (void*)vc; 313 struct intrhand *ih = arg; 314 int level1 = ih->ih_l1line; 315 bus_space_tag_t iot = sc->sc_iot; 316 bus_space_handle_t ioh = sc->sc_ioh; 317 u_int32_t reg = sc->sc_intrmask; 318 319 reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 320 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 321 if (enable) 322 reg |= (1 << level1); 323 else { 324 reg &= ~(1 << level1); 325 } 326 sc->sc_intrmask = reg; 327 bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff); 328 bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff); 329 DBITDISP32(reg); 330 331 return; 332 } 333 334 static void 335 vrip_dump_level2mask (vc, arg) 336 vrip_chipset_tag_t vc; 337 void *arg; 338 { 339 struct vrip_softc *sc = (void*)vc; 340 struct intrhand *ih = arg; 341 u_int32_t reg; 342 343 if (ih->ih_mlreg) { 344 printf ("level1[%d] level2 mask:", ih->ih_l1line); 345 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 346 if (ih->ih_mhreg) { /* GIU [16:31] case only */ 347 reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg) << 16); 348 bitdisp32(reg); 349 } else 350 bitdisp16(reg); 351 } 352 } 353 354 /* Get level 2 interrupt status */ 355 void 356 vrip_intr_get_status2(vc, arg, mask) 357 vrip_chipset_tag_t vc; 358 void *arg; 359 u_int32_t *mask; /* Level 2 mask */ 360 { 361 struct vrip_softc *sc = (void*)vc; 362 struct intrhand *ih = arg; 363 u_int32_t reg; 364 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 365 ih->ih_lreg); 366 reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh, 367 ih->ih_hreg) << 16)&0xffff0000); 368 /* bitdisp32(reg);*/ 369 *mask = reg; 370 } 371 372 /* Set level 2 interrupt mask. */ 373 void 374 vrip_intr_setmask2(vc, arg, mask, onoff) 375 vrip_chipset_tag_t vc; 376 void *arg; 377 u_int32_t mask; /* Level 2 mask */ 378 { 379 struct vrip_softc *sc = (void*)vc; 380 struct intrhand *ih = arg; 381 u_int16_t reg; 382 383 DPRINTF(("vrip_intr_setmask2:\n")); 384 DDUMP_LEVEL2MASK(vc, arg); 385 #ifdef WINCE_DEFAULT_SETTING 386 #warning WINCE_DEFAULT_SETTING 387 #else 388 if (ih->ih_mlreg) { 389 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg); 390 if (onoff) 391 reg |= (mask&0xffff); 392 else 393 reg &= ~(mask&0xffff); 394 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg, reg); 395 if (ih->ih_mhreg != -1) { /* GIU [16:31] case only */ 396 reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg); 397 if (onoff) 398 reg |= ((mask >> 16) & 0xffff); 399 else 400 reg &= ~((mask >> 16) & 0xffff); 401 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 402 ih->ih_mhreg, reg); 403 } 404 } 405 #endif /* WINCE_DEFAULT_SETTING */ 406 DDUMP_LEVEL2MASK(vc, arg); 407 408 return; 409 } 410 411 int 412 vrip_intr(arg, pc, statusReg) 413 void *arg; 414 u_int32_t pc; 415 u_int32_t statusReg; 416 { 417 struct vrip_softc *sc = (struct vrip_softc*)arg; 418 bus_space_tag_t iot = sc->sc_iot; 419 bus_space_handle_t ioh = sc->sc_ioh; 420 int i; 421 u_int32_t reg, mask; 422 /* 423 * Read level1 interrupt status. 424 */ 425 reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) | 426 ((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000); 427 mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) | 428 ((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000); 429 reg &= mask; 430 431 /* 432 * Dispatch each handler. 433 */ 434 for (i = 0; i < 32; i++) { 435 register struct intrhand *ih = &intrhand[i]; 436 if (ih->ih_fun && (reg & (1 << i))) { 437 ih->ih_fun(ih->ih_arg); 438 } 439 } 440 return 1; 441 } 442 443 void 444 vrip_cmu_function_register(vc, func, arg) 445 vrip_chipset_tag_t vc; 446 vrcmu_function_tag_t func; 447 vrcmu_chipset_tag_t arg; 448 { 449 struct vrip_softc *sc = (void*)vc; 450 sc->sc_cf = func; 451 sc->sc_cc = arg; 452 } 453 454 void 455 vrip_giu_function_register(vc, func, arg) 456 vrip_chipset_tag_t vc; 457 vrgiu_function_tag_t func; 458 vrgiu_chipset_tag_t arg; 459 { 460 struct vrip_softc *sc = (void*)vc; 461 sc->sc_gf = func; 462 sc->sc_gc = arg; 463 } 464
Indexes created Fri Sep 26 20:09:58 GMT 2025