1 1.8 igy /* $NetBSD: vripreg.h,v 1.8 2003/04/01 02:33:52 igy Exp $ */ 2 1.1 takemura 3 1.1 takemura /*- 4 1.1 takemura * Copyright (c) 1999 5 1.1 takemura * Shin Takemura and PocketBSD Project. All rights reserved. 6 1.2 sato * Copyright (c) 2001 SATO Kazumi, All rights reserved. 7 1.1 takemura * 8 1.1 takemura * Redistribution and use in source and binary forms, with or without 9 1.1 takemura * modification, are permitted provided that the following conditions 10 1.1 takemura * are met: 11 1.1 takemura * 1. Redistributions of source code must retain the above copyright 12 1.1 takemura * notice, this list of conditions and the following disclaimer. 13 1.1 takemura * 2. Redistributions in binary form must reproduce the above copyright 14 1.1 takemura * notice, this list of conditions and the following disclaimer in the 15 1.1 takemura * documentation and/or other materials provided with the distribution. 16 1.1 takemura * 3. All advertising materials mentioning features or use of this software 17 1.1 takemura * must display the following acknowledgement: 18 1.1 takemura * This product includes software developed by the PocketBSD project 19 1.1 takemura * and its contributors. 20 1.1 takemura * 4. Neither the name of the project nor the names of its contributors 21 1.1 takemura * may be used to endorse or promote products derived from this software 22 1.1 takemura * without specific prior written permission. 23 1.1 takemura * 24 1.1 takemura * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 1.1 takemura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 1.1 takemura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 1.1 takemura * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 1.1 takemura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 1.1 takemura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 1.1 takemura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 1.1 takemura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 1.1 takemura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 1.1 takemura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 1.1 takemura * SUCH DAMAGE. 35 1.1 takemura * 36 1.1 takemura */ 37 1.1 takemura 38 1.2 sato #define VRIP_NO_ADDR 0x00000000 39 1.2 sato /* 40 1.3 sato * VR4181 registers 41 1.3 sato */ 42 1.3 sato #define VR4181_BCU_ADDR 0x0a000000 43 1.3 sato #define VR4181_DMAAU_ADDR VRIP_NO_ADDR 44 1.3 sato #define VR4181_DCU_ADDR VRIP_NO_ADDR 45 1.3 sato #define VR4181_CMU_ADDR 0x0a000004 46 1.3 sato #define VR4181_ICU_ADDR 0x0a000080 47 1.3 sato #define VR4181_PMU_ADDR 0x0a0000a0 48 1.3 sato #define VR4181_RTC_ADDR 0x0a0000c0 49 1.3 sato #define VR4181_DSU_ADDR 0x0a0000e0 50 1.3 sato #define VR4181_GIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 51 1.3 sato #define VR4181_PIU_ADDR 0x0a000122 52 1.3 sato #define VR4181_AIU_ADDR 0x0a000160 53 1.3 sato #define VR4181_KIU_ADDR 0x0a000180 54 1.3 sato #define VR4181_DSIU_ADDR 0x0a0001a0 55 1.3 sato #define VR4181_LED_ADDR 0x0a000240 56 1.6 sato #define VR4181_SIU_ADDR 0x0c000010 57 1.3 sato #define VR4181_HSP_ADDR 0x0a000020 58 1.3 sato #define VR4181_FIR_ADDR 0x0a000000 /* XXX */ 59 1.3 sato #define VR4181_MEMCON_ADDR 0x0a000300 60 1.3 sato #define VR4181_ISABRG_ADDR 0x0b0002c0 61 1.8 igy #define VR4181_ECU_ADDR 0x0b0008e0 62 1.3 sato #define VR4181_DCU81_ADDR 0x0a000020 63 1.3 sato #define VR4181_CSI81_ADDR 0x0b000900 64 1.3 sato #define VR4181_GIU81_ADDR 0x0b000300 65 1.3 sato #define VR4181_LCD_ADDR 0x0a000400 66 1.6 sato #define VR4181_SIU1_ADDR 0x0c000000 67 1.3 sato #define VR4181_SCU_ARR VRIP_NO_ADDR /* XXX: no register */ 68 1.3 sato #define VR4181_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */ 69 1.3 sato #define VR4181_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */ 70 1.3 sato #define VR4181_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */ 71 1.3 sato #define VR4181_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */ 72 1.3 sato 73 1.3 sato /* 74 1.2 sato * VR4101-4121 registers 75 1.2 sato */ 76 1.2 sato #define VR4102_BCU_ADDR 0x0b000000 77 1.2 sato #define VR4102_DMAAU_ADDR 0x0b000020 78 1.2 sato #define VR4102_DCU_ADDR 0x0b000040 79 1.2 sato #define VR4102_CMU_ADDR 0x0b000060 80 1.2 sato #define VR4102_ICU_ADDR 0x0b000080 81 1.2 sato #define VR4102_PMU_ADDR 0x0b0000a0 82 1.2 sato #define VR4102_RTC_ADDR 0x0b0000c0 83 1.2 sato #define VR4102_DSU_ADDR 0x0b0000e0 84 1.2 sato #define VR4102_GIU_ADDR 0x0b000100 85 1.2 sato #define VR4102_PIU_ADDR 0x0b000120 86 1.3 sato #define VR4102_AIU_ADDR 0x0b000160 87 1.2 sato #define VR4102_KIU_ADDR 0x0b000180 88 1.2 sato #define VR4102_DSIU_ADDR 0x0b0001a0 89 1.2 sato #define VR4102_LED_ADDR 0x0b000240 90 1.2 sato #define VR4102_SIU_ADDR 0x0c000000 91 1.2 sato #define VR4102_HSP_ADDR 0x0c000020 92 1.2 sato #define VR4102_FIR_ADDR 0x0b000000 /* XXX */ 93 1.3 sato #define VR4102_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */ 94 1.3 sato #define VR4102_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */ 95 1.3 sato #define VR4102_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */ 96 1.3 sato #define VR4102_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */ 97 1.3 sato #define VR4102_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */ 98 1.3 sato #define VR4102_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */ 99 1.3 sato #define VR4102_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */ 100 1.2 sato #define VR4102_SCU_ARR VRIP_NO_ADDR /* XXX: no register */ 101 1.2 sato #define VR4102_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */ 102 1.2 sato #define VR4102_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */ 103 1.2 sato #define VR4102_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */ 104 1.2 sato #define VR4102_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */ 105 1.2 sato /* 106 1.2 sato * VR4122 registers 107 1.2 sato */ 108 1.2 sato #define VR4122_BCU_ADDR 0x0f000000 109 1.2 sato #define VR4122_DMAAU_ADDR 0x0f000020 110 1.2 sato #define VR4122_DCU_ADDR 0x0f000040 111 1.2 sato #define VR4122_CMU_ADDR 0x0f000060 112 1.2 sato #define VR4122_ICU_ADDR 0x0f000080 113 1.4 sato #define VR4122_PMU_ADDR 0x0f0000c0 114 1.4 sato #define VR4122_RTC_ADDR 0x0f000100 115 1.2 sato #define VR4122_DSU_ADDR VRIP_NO_ADDR /* XXX: no register */ 116 1.2 sato #define VR4122_GIU_ADDR 0x0f000140 117 1.2 sato #define VR4122_PIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 118 1.2 sato #define VR4122_AIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 119 1.2 sato #define VR4122_KIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 120 1.2 sato #define VR4122_DSIU_ADDR 0x0f000820 121 1.2 sato #define VR4122_LED_ADDR 0x0f000180 122 1.2 sato #define VR4122_SIU_ADDR 0x0f000800 123 1.2 sato #define VR4122_HSP_ADDR VRIP_NO_ADDR /* XXX: no register */ 124 1.2 sato #define VR4122_FIR_ADDR 0x0f000840 /* XXX */ 125 1.3 sato #define VR4122_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */ 126 1.3 sato #define VR4122_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */ 127 1.3 sato #define VR4122_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */ 128 1.3 sato #define VR4122_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */ 129 1.3 sato #define VR4122_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */ 130 1.3 sato #define VR4122_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */ 131 1.3 sato #define VR4122_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */ 132 1.2 sato #define VR4122_SCU_ARR 0x0f001000 133 1.4 sato #define VR4122_SDRAMU_ADDR 0x0f000400 134 1.4 sato #define VR4122_PCI_ADDR 0x0f000c00 135 1.4 sato #define VR4122_PCICONF_ADDR 0x0f000d00 136 1.4 sato #define VR4122_CSI_ADDR 0x0f0001a0 137 1.1 takemura 138 1.2 sato /* 139 1.2 sato * VRIP base address 140 1.2 sato * 141 1.2 sato * REQUIRE: opt_vr41xx.h, vrcpudef.h 142 1.2 sato */ 143 1.2 sato #include "opt_vr41xx.h" 144 1.2 sato #include <hpcmips/vr/vrcpudef.h> 145 1.1 takemura 146 1.7 takemura #if defined SINGLE_VRIP_BASE 147 1.2 sato 148 1.2 sato #if defined VRGROUP_4181 149 1.2 sato #define VRIP_BASE_ADDR 0x0a000000 150 1.3 sato 151 1.3 sato #define VRIP_BCU_ADDR VR4181_BCU_ADDR 152 1.3 sato #define VRIP_DMAAU_ADDR VR4181_DMAAU_ADDR 153 1.3 sato #define VRIP_DCU_ADDR VR4181_DCU_ADDR 154 1.3 sato #define VRIP_CMU_ADDR VR4181_CMU_ADDR 155 1.3 sato #define VRIP_ICU_ADDR VR4181_ICU_ADDR 156 1.3 sato #define VRIP_PMU_ADDR VR4181_PMU_ADDR 157 1.3 sato #define VRIP_RTC_ADDR VR4181_RTC_ADDR 158 1.3 sato #define VRIP_DSU_ADDR VR4181_DSU_ADDR 159 1.3 sato #define VRIP_GIU_ADDR VR4181_GIU_ADDR 160 1.3 sato #define VRIP_PIU_ADDR VR4181_PIU_ADDR 161 1.3 sato #define VRIP_AIU_ADDR VR4181_AIU_ADDR 162 1.3 sato #define VRIP_KIU_ADDR VR4181_KIU_ADDR 163 1.3 sato #define VRIP_DSIU_ADDR VR4181_DSIU_ADDR 164 1.3 sato #define VRIP_LED_ADDR VR4181_LED_ADDR 165 1.3 sato #define VRIP_SIU_ADDR VR4181_SIU_ADDR 166 1.3 sato #define VRIP_HSP_ADDR VR4181_HSP_ADDR 167 1.3 sato #define VRIP_FIR_ADDR VR4181_FIR_ADDR 168 1.3 sato #define VRIP_MEMCON_ADDR VR4181_MEMCON_ADDR 169 1.3 sato #define VRIP_ISABRG_ADDR VR4181_ISABRG_ADDR 170 1.3 sato #define VRIP_ECU_ADDR VR4181_ECU_ADDR 171 1.3 sato #define VRIP_DCU81_ADDR VR4181_DCU81_ADDR 172 1.3 sato #define VRIP_CSI81_ADDR VR4181_CSI81_ADDR 173 1.3 sato #define VRIP_GIU81_ADDR VR4181_GIU81_ADDR 174 1.3 sato #define VRIP_LCD_ADDR VR4181_LCD_ADDR 175 1.3 sato #define VRIP_SIU1_ADDR VR4181_SIU1_ADDR 176 1.3 sato #define VRIP_SCU_ARR VR4181_SCU_ARR /* XXX: no register */ 177 1.3 sato #define VRIP_SDRAMU_ADDR VR4181_SDRAMU_ADDR /* XXX: no register */ 178 1.3 sato #define VRIP_PCI_ADDR VR4181_PCI_ADDR /* XXX: no register */ 179 1.3 sato #define VRIP_PCICONF_ADDR VR4181_PCICONF_ADDR /* XXX: no register */ 180 1.3 sato #define VRIP_CSI_ADDR VR4181_CSI_ADDR /* XXX: no register */ 181 1.3 sato 182 1.2 sato #endif /* VRGROUP_4181 */ 183 1.2 sato 184 1.5 sato #if defined VRGROUP_4122_4131 185 1.2 sato #define VRIP_BASE_ADDR 0x0f000000 186 1.2 sato 187 1.2 sato #define VRIP_BCU_ADDR VR4122_BCU_ADDR 188 1.2 sato #define VRIP_DMAAU_ADDR VR4122_DMAAU_ADDR 189 1.2 sato #define VRIP_DCU_ADDR VR4122_DCU_ADDR 190 1.2 sato #define VRIP_CMU_ADDR VR4122_CMU_ADDR 191 1.2 sato #define VRIP_ICU_ADDR VR4122_ICU_ADDR 192 1.2 sato #define VRIP_PMU_ADDR VR4122_PMU_ADDR 193 1.2 sato #define VRIP_RTC_ADDR VR4122_RTC_ADDR 194 1.2 sato #define VRIP_DSU_ADDR VR4122_DSU_ADDR 195 1.2 sato #define VRIP_GIU_ADDR VR4122_GIU_ADDR 196 1.2 sato #define VRIP_PIU_ADDR VR4122_PIU_ADDR 197 1.2 sato #define VRIP_AIU_ADDR VR4122_AIU_ADDR 198 1.2 sato #define VRIP_KIU_ADDR VR4122_KIU_ADDR 199 1.2 sato #define VRIP_DSIU_ADDR VR4122_DSIU_ADDR 200 1.2 sato #define VRIP_LED_ADDR VR4122_LED_ADDR 201 1.2 sato #define VRIP_SIU_ADDR VR4122_SIU_ADDR 202 1.2 sato #define VRIP_HSP_ADDR VR4122_HSP_ADDR 203 1.2 sato #define VRIP_FIR_ADDR VR4122_FIR_ADDR 204 1.3 sato #define VRIP_MEMCON_ADDR VR4122_MEMCON_ADDR /* XXX: no register */ 205 1.3 sato #define VRIP_ISABRG_ADDR VR4122_ISABRG_ADDR /* XXX: no register */ 206 1.3 sato #define VRIP_ECU_ADDR VR4122_ECU_ADDR /* XXX: no register */ 207 1.3 sato #define VRIP_DCU81_ADDR VR4122_DCU81_ADDR /* XXX: no register */ 208 1.3 sato #define VRIP_CSI81_ADDR VR4122_CSI81_ADDR /* XXX: no register */ 209 1.3 sato #define VRIP_GIU81_ADDR VR4122_CSI81_ADDR /* XXX: no register */ 210 1.3 sato #define VRIP_SIU1_ADDR VR4122_SIU1_ADDR /* XXX: no register */ 211 1.2 sato #define VRIP_SCU_ARR VR4122_SCU_ARR /* XXX: no register */ 212 1.2 sato #define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR /* XXX: no register */ 213 1.2 sato #define VRIP_PCI_ADDR VR4122_PCI_ADDR /* XXX: no register */ 214 1.2 sato #define VRIP_PCICONF_ADDR VR4122_PCICONF_ADDR /* XXX: no register */ 215 1.2 sato #define VRIP_CSI_ADDR VR4122_CSI_ADDR /* XXX: no register */ 216 1.2 sato 217 1.5 sato #endif /* VRGROUP_4122_4131 */ 218 1.2 sato 219 1.2 sato #if defined VRGROUP_4102_4121 220 1.2 sato #define VRIP_BASE_ADDR 0x0b000000 221 1.2 sato 222 1.2 sato #define VRIP_BCU_ADDR VR4102_BCU_ADDR 223 1.2 sato #define VRIP_DMAAU_ADDR VR4102_DMAAU_ADDR 224 1.2 sato #define VRIP_DCU_ADDR VR4102_DCU_ADDR 225 1.2 sato #define VRIP_CMU_ADDR VR4102_CMU_ADDR 226 1.2 sato #define VRIP_ICU_ADDR VR4102_ICU_ADDR 227 1.2 sato #define VRIP_PMU_ADDR VR4102_PMU_ADDR 228 1.2 sato #define VRIP_RTC_ADDR VR4102_RTC_ADDR 229 1.2 sato #define VRIP_DSU_ADDR VR4102_DSU_ADDR 230 1.2 sato #define VRIP_GIU_ADDR VR4102_GIU_ADDR 231 1.2 sato #define VRIP_PIU_ADDR VR4102_PIU_ADDR 232 1.2 sato #define VRIP_AIU_ADDR VR4102_AIU_ADDR 233 1.2 sato #define VRIP_KIU_ADDR VR4102_KIU_ADDR 234 1.2 sato #define VRIP_DSIU_ADDR VR4102_DSIU_ADDR 235 1.2 sato #define VRIP_LED_ADDR VR4102_LED_ADDR 236 1.2 sato #define VRIP_SIU_ADDR VR4102_SIU_ADDR 237 1.2 sato #define VRIP_HSP_ADDR VR4102_HSP_ADDR 238 1.2 sato #define VRIP_FIR_ADDR VR4102_FIR_ADDR 239 1.3 sato #define VRIP_MEMCON_ADDR VR4102_MEMCON_ADDR /* XXX: no register */ 240 1.3 sato #define VRIP_ISABRG_ADDR VR4102_ISABRG_ADDR /* XXX: no register */ 241 1.3 sato #define VRIP_ECU_ADDR VR4102_ECU_ADDR /* XXX: no register */ 242 1.3 sato #define VRIP_DCU81_ADDR VR4102_DCU81_ADDR /* XXX: no register */ 243 1.3 sato #define VRIP_CSI81_ADDR VR4102_CSI81_ADDR /* XXX: no register */ 244 1.6 sato #define VRIP_GIU81_ADDR VR4102_GIU81_ADDR /* XXX: no register */ 245 1.3 sato #define VRIP_SIU1_ADDR VR4102_SIU1_ADDR /* XXX: no register */ 246 1.2 sato #define VRIP_SCU_ARR VR4102_SCU_ARR /* XXX: no register */ 247 1.2 sato #define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR /* XXX: no register */ 248 1.2 sato #define VRIP_PCI_ADDR VR4102_PCI_ADDR /* XXX: no register */ 249 1.2 sato #define VRIP_PCICONF_ADDR VR4102_PCICONF_ADDR /* XXX: no register */ 250 1.2 sato #define VRIP_CSI_ADDR VR4102_CSI_ADDR /* XXX: no register */ 251 1.1 takemura 252 1.2 sato #endif /* VRGROUP_4102_4121 */ 253 1.1 takemura 254 1.2 sato #endif /* SINGLE_VRIP_BASE */ 255 1.1 takemura 256 1.2 sato /* 257 1.2 sato * ICU interrupt level 258 1.2 sato */ 259 1.2 sato /* reserved 62-31 */ 260 1.2 sato #define VRIP_INTR_BCU 25 261 1.2 sato #define VRIP_INTR_CSI 24 262 1.2 sato #define VRIP_INTR_SCU 23 263 1.2 sato #define VRIP_INTR_PCI 22 264 1.3 sato #define VRIP_INTR_LCD 22 /* 4181 */ 265 1.1 takemura #define VRIP_INTR_DSIU 21 266 1.3 sato #define VRIP_INTR_DCU81 21 /* 4181 */ 267 1.1 takemura #define VRIP_INTR_FIR 20 268 1.1 takemura #define VRIP_INTR_TCLK 19 269 1.3 sato #define VRIP_INTR_CSI81 19 /* 4181 */ 270 1.1 takemura #define VRIP_INTR_HSP 18 271 1.3 sato #define VRIP_INTR_ECU 18 /* 4181 */ 272 1.1 takemura #define VRIP_INTR_LED 17 273 1.1 takemura #define VRIP_INTR_RTCL2 16 274 1.1 takemura /* reserved 15,14 */ 275 1.1 takemura #define VRIP_INTR_DOZEPIU 13 276 1.2 sato #define VRIP_INTR_CLKRUN 12 277 1.1 takemura #define VRIP_INTR_SOFT 11 278 1.1 takemura #define VRIP_INTR_WRBERR 10 279 1.1 takemura #define VRIP_INTR_SIU 9 280 1.1 takemura #define VRIP_INTR_GIU 8 281 1.1 takemura #define VRIP_INTR_KIU 7 282 1.1 takemura #define VRIP_INTR_AIU 6 283 1.1 takemura #define VRIP_INTR_PIU 5 284 1.1 takemura /* reserved 4 VRC4171 use this ??? */ 285 1.1 takemura #define VRIP_INTR_ETIMER 3 286 1.1 takemura #define VRIP_INTR_RTCL1 2 287 1.1 takemura #define VRIP_INTR_POWER 1 288 1.1 takemura #define VRIP_INTR_BAT 0 289
Indexes created Thu Sep 25 16:09:42 GMT 2025