vripreg.h revision 1.2
1 /* $NetBSD: vripreg.h,v 1.2 2001/04/18 11:07:28 sato Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 5 * Shin Takemura and PocketBSD Project. All rights reserved. 6 * Copyright (c) 2001 SATO Kazumi, All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the PocketBSD project 19 * and its contributors. 20 * 4. Neither the name of the project nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #define VRIP_NO_ADDR 0x00000000 39 /* 40 * VR4101-4121 registers 41 */ 42 #define VR4102_BCU_ADDR 0x0b000000 43 #define VR4102_DMAAU_ADDR 0x0b000020 44 #define VR4102_DCU_ADDR 0x0b000040 45 #define VR4102_CMU_ADDR 0x0b000060 46 #define VR4102_ICU_ADDR 0x0b000080 47 #define VR4102_PMU_ADDR 0x0b0000a0 48 #define VR4102_RTC_ADDR 0x0b0000c0 49 #define VR4102_DSU_ADDR 0x0b0000e0 50 #define VR4102_GIU_ADDR 0x0b000100 51 #define VR4102_PIU_ADDR 0x0b000120 52 #define VR4102_AIU_ADDR 0x0b000000 /* XXX */ 53 #define VR4102_KIU_ADDR 0x0b000180 54 #define VR4102_DSIU_ADDR 0x0b0001a0 55 #define VR4102_LED_ADDR 0x0b000240 56 #define VR4102_SIU_ADDR 0x0c000000 57 #define VR4102_HSP_ADDR 0x0c000020 58 #define VR4102_FIR_ADDR 0x0b000000 /* XXX */ 59 #define VR4102_SCU_ARR VRIP_NO_ADDR /* XXX: no register */ 60 #define VR4102_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */ 61 #define VR4102_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */ 62 #define VR4102_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */ 63 #define VR4102_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */ 64 65 /* 66 * VR4122 registers 67 */ 68 #define VR4122_BCU_ADDR 0x0f000000 69 #define VR4122_DMAAU_ADDR 0x0f000020 70 #define VR4122_DCU_ADDR 0x0f000040 71 #define VR4122_CMU_ADDR 0x0f000060 72 #define VR4122_ICU_ADDR 0x0f000080 73 #define VR4122_PMU_ADDR 0x0f000100 74 #define VR4122_RTC_ADDR 0x0f000140 75 #define VR4122_DSU_ADDR VRIP_NO_ADDR /* XXX: no register */ 76 #define VR4122_GIU_ADDR 0x0f000140 77 #define VR4122_PIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 78 #define VR4122_AIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 79 #define VR4122_KIU_ADDR VRIP_NO_ADDR /* XXX: no register */ 80 #define VR4122_DSIU_ADDR 0x0f000820 81 #define VR4122_LED_ADDR 0x0f000180 82 #define VR4122_SIU_ADDR 0x0f000800 83 #define VR4122_HSP_ADDR VRIP_NO_ADDR /* XXX: no register */ 84 #define VR4122_FIR_ADDR 0x0f000840 /* XXX */ 85 #define VR4122_SCU_ARR 0x0f001000 86 #define VR4122_SDRAMU_ADDR 0x00000400 87 #define VR4122_PCI_ADDR 0x00000c00 88 #define VR4122_PCICONF_ADDR 0x00000d00 89 #define VR4122_CSI_ADDR 0x000001a0 90 91 /* 92 * VRIP base address 93 * 94 * REQUIRE: opt_vr41xx.h, vrcpudef.h 95 */ 96 #include "opt_vr41xx.h" 97 #include <hpcmips/vr/vrcpudef.h> 98 99 #if !defined SINGLE_VRIP_BASE 100 101 #error currently missconfiguration. 102 #error NEED switch VRIP_BASE_ADDR by vr cpu type. 103 104 #else 105 106 #if defined VRGROUP_4181 107 #define VRIP_BASE_ADDR 0x0a000000 108 #endif /* VRGROUP_4181 */ 109 110 #if defined VRGROUP_4122 111 #define VRIP_BASE_ADDR 0x0f000000 112 113 #define VRIP_BCU_ADDR VR4122_BCU_ADDR 114 #define VRIP_DMAAU_ADDR VR4122_DMAAU_ADDR 115 #define VRIP_DCU_ADDR VR4122_DCU_ADDR 116 #define VRIP_CMU_ADDR VR4122_CMU_ADDR 117 #define VRIP_ICU_ADDR VR4122_ICU_ADDR 118 #define VRIP_PMU_ADDR VR4122_PMU_ADDR 119 #define VRIP_RTC_ADDR VR4122_RTC_ADDR 120 #define VRIP_DSU_ADDR VR4122_DSU_ADDR 121 #define VRIP_GIU_ADDR VR4122_GIU_ADDR 122 #define VRIP_PIU_ADDR VR4122_PIU_ADDR 123 #define VRIP_AIU_ADDR VR4122_AIU_ADDR 124 #define VRIP_KIU_ADDR VR4122_KIU_ADDR 125 #define VRIP_DSIU_ADDR VR4122_DSIU_ADDR 126 #define VRIP_LED_ADDR VR4122_LED_ADDR 127 #define VRIP_SIU_ADDR VR4122_SIU_ADDR 128 #define VRIP_HSP_ADDR VR4122_HSP_ADDR 129 #define VRIP_FIR_ADDR VR4122_FIR_ADDR 130 #define VRIP_SCU_ARR VR4122_SCU_ARR /* XXX: no register */ 131 #define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR /* XXX: no register */ 132 #define VRIP_PCI_ADDR VR4122_PCI_ADDR /* XXX: no register */ 133 #define VRIP_PCICONF_ADDR VR4122_PCICONF_ADDR /* XXX: no register */ 134 #define VRIP_CSI_ADDR VR4122_CSI_ADDR /* XXX: no register */ 135 136 #endif /* VRGROUP_4122 */ 137 138 #if defined VRGROUP_4102_4121 139 #define VRIP_BASE_ADDR 0x0b000000 140 141 #define VRIP_BCU_ADDR VR4102_BCU_ADDR 142 #define VRIP_DMAAU_ADDR VR4102_DMAAU_ADDR 143 #define VRIP_DCU_ADDR VR4102_DCU_ADDR 144 #define VRIP_CMU_ADDR VR4102_CMU_ADDR 145 #define VRIP_ICU_ADDR VR4102_ICU_ADDR 146 #define VRIP_PMU_ADDR VR4102_PMU_ADDR 147 #define VRIP_RTC_ADDR VR4102_RTC_ADDR 148 #define VRIP_DSU_ADDR VR4102_DSU_ADDR 149 #define VRIP_GIU_ADDR VR4102_GIU_ADDR 150 #define VRIP_PIU_ADDR VR4102_PIU_ADDR 151 #define VRIP_AIU_ADDR VR4102_AIU_ADDR 152 #define VRIP_KIU_ADDR VR4102_KIU_ADDR 153 #define VRIP_DSIU_ADDR VR4102_DSIU_ADDR 154 #define VRIP_LED_ADDR VR4102_LED_ADDR 155 #define VRIP_SIU_ADDR VR4102_SIU_ADDR 156 #define VRIP_HSP_ADDR VR4102_HSP_ADDR 157 #define VRIP_FIR_ADDR VR4102_FIR_ADDR 158 #define VRIP_SCU_ARR VR4102_SCU_ARR /* XXX: no register */ 159 #define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR /* XXX: no register */ 160 #define VRIP_PCI_ADDR VR4102_PCI_ADDR /* XXX: no register */ 161 #define VRIP_PCICONF_ADDR VR4102_PCICONF_ADDR /* XXX: no register */ 162 #define VRIP_CSI_ADDR VR4102_CSI_ADDR /* XXX: no register */ 163 164 #endif /* VRGROUP_4102_4121 */ 165 166 #endif /* SINGLE_VRIP_BASE */ 167 168 /* 169 * ICU interrupt level 170 */ 171 /* reserved 62-31 */ 172 #define VRIP_INTR_BCU 25 173 #define VRIP_INTR_CSI 24 174 #define VRIP_INTR_SCU 23 175 #define VRIP_INTR_PCI 22 176 #define VRIP_INTR_DSIU 21 177 #define VRIP_INTR_FIR 20 178 #define VRIP_INTR_TCLK 19 179 #define VRIP_INTR_HSP 18 180 #define VRIP_INTR_LED 17 181 #define VRIP_INTR_RTCL2 16 182 /* reserved 15,14 */ 183 #define VRIP_INTR_DOZEPIU 13 184 #define VRIP_INTR_CLKRUN 12 185 #define VRIP_INTR_SOFT 11 186 #define VRIP_INTR_WRBERR 10 187 #define VRIP_INTR_SIU 9 188 #define VRIP_INTR_GIU 8 189 #define VRIP_INTR_KIU 7 190 #define VRIP_INTR_AIU 6 191 #define VRIP_INTR_PIU 5 192 /* reserved 4 VRC4171 use this ??? */ 193 #define VRIP_INTR_ETIMER 3 194 #define VRIP_INTR_RTCL1 2 195 #define VRIP_INTR_POWER 1 196 #define VRIP_INTR_BAT 0 197
Indexes created Tue Sep 30 06:09:59 GMT 2025