vrpciu.c revision 1.1.10.6 1 1.1.10.6 nathanw /* $NetBSD: vrpciu.c,v 1.1.10.6 2002/06/20 03:38:57 nathanw Exp $ */
2 1.1.10.2 nathanw
3 1.1.10.2 nathanw /*-
4 1.1.10.2 nathanw * Copyright (c) 2001 Enami Tsugutomo.
5 1.1.10.2 nathanw * All rights reserved.
6 1.1.10.2 nathanw *
7 1.1.10.2 nathanw * Redistribution and use in source and binary forms, with or without
8 1.1.10.2 nathanw * modification, are permitted provided that the following conditions
9 1.1.10.2 nathanw * are met:
10 1.1.10.2 nathanw * 1. Redistributions of source code must retain the above copyright
11 1.1.10.2 nathanw * notice, this list of conditions and the following disclaimer.
12 1.1.10.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
13 1.1.10.2 nathanw * notice, this list of conditions and the following disclaimer in the
14 1.1.10.2 nathanw * documentation and/or other materials provided with the distribution.
15 1.1.10.2 nathanw *
16 1.1.10.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.1.10.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1.10.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1.10.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.1.10.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.1.10.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.1.10.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1.10.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.1.10.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1.10.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1.10.2 nathanw * SUCH DAMAGE.
27 1.1.10.2 nathanw */
28 1.1.10.2 nathanw
29 1.1.10.2 nathanw #include <sys/param.h>
30 1.1.10.2 nathanw #include <sys/systm.h>
31 1.1.10.2 nathanw #include <sys/device.h>
32 1.1.10.2 nathanw
33 1.1.10.2 nathanw #include <machine/bus.h>
34 1.1.10.2 nathanw #include <machine/bus_space_hpcmips.h>
35 1.1.10.2 nathanw #include <machine/bus_dma_hpcmips.h>
36 1.1.10.4 nathanw #include <machine/config_hook.h>
37 1.1.10.3 nathanw #include <machine/platid.h>
38 1.1.10.3 nathanw #include <machine/platid_mask.h>
39 1.1.10.2 nathanw
40 1.1.10.2 nathanw #include <dev/pci/pcivar.h>
41 1.1.10.3 nathanw #include <dev/pci/pcidevs.h>
42 1.1.10.4 nathanw #include <dev/pci/pciidereg.h>
43 1.1.10.2 nathanw
44 1.1.10.2 nathanw #include <hpcmips/vr/icureg.h>
45 1.1.10.4 nathanw #include <hpcmips/vr/vripif.h>
46 1.1.10.2 nathanw #include <hpcmips/vr/vrpciureg.h>
47 1.1.10.2 nathanw
48 1.1.10.2 nathanw #include "pci.h"
49 1.1.10.2 nathanw
50 1.1.10.2 nathanw #ifdef DEBUG
51 1.1.10.2 nathanw #define DPRINTF(args) printf args
52 1.1.10.2 nathanw #else
53 1.1.10.2 nathanw #define DPRINTF(args)
54 1.1.10.2 nathanw #endif
55 1.1.10.2 nathanw
56 1.1.10.2 nathanw struct vrpciu_softc {
57 1.1.10.2 nathanw struct device sc_dev;
58 1.1.10.2 nathanw
59 1.1.10.2 nathanw vrip_chipset_tag_t sc_vc;
60 1.1.10.2 nathanw bus_space_tag_t sc_iot;
61 1.1.10.2 nathanw bus_space_handle_t sc_ioh;
62 1.1.10.2 nathanw void *sc_ih;
63 1.1.10.2 nathanw
64 1.1.10.2 nathanw struct vrc4173bcu_softc *sc_bcu; /* vrc4173bcu */
65 1.1.10.2 nathanw
66 1.1.10.2 nathanw struct hpcmips_pci_chipset sc_pc;
67 1.1.10.2 nathanw };
68 1.1.10.2 nathanw
69 1.1.10.2 nathanw static void vrpciu_write(struct vrpciu_softc *, int, u_int32_t);
70 1.1.10.2 nathanw static u_int32_t
71 1.1.10.2 nathanw vrpciu_read(struct vrpciu_softc *, int);
72 1.1.10.2 nathanw #ifdef DEBUG
73 1.1.10.2 nathanw static void vrpciu_write_2(struct vrpciu_softc *, int, u_int16_t)
74 1.1.10.2 nathanw __attribute__((unused));
75 1.1.10.2 nathanw static u_int16_t
76 1.1.10.2 nathanw vrpciu_read_2(struct vrpciu_softc *, int);
77 1.1.10.2 nathanw #endif
78 1.1.10.2 nathanw static int vrpciu_match(struct device *, struct cfdata *, void *);
79 1.1.10.2 nathanw static void vrpciu_attach(struct device *, struct device *, void *);
80 1.1.10.2 nathanw #if NPCI > 0
81 1.1.10.2 nathanw static int vrpciu_print(void *, const char *);
82 1.1.10.2 nathanw #endif
83 1.1.10.2 nathanw static int vrpciu_intr(void *);
84 1.1.10.2 nathanw static void vrpciu_attach_hook(struct device *, struct device *,
85 1.1.10.2 nathanw struct pcibus_attach_args *);
86 1.1.10.2 nathanw static int vrpciu_bus_maxdevs(pci_chipset_tag_t, int);
87 1.1.10.3 nathanw static int vrpciu_bus_devorder(pci_chipset_tag_t, int, char *);
88 1.1.10.2 nathanw static pcitag_t vrpciu_make_tag(pci_chipset_tag_t, int, int, int);
89 1.1.10.2 nathanw static void vrpciu_decompose_tag(pci_chipset_tag_t, pcitag_t, int *, int *,
90 1.1.10.2 nathanw int *);
91 1.1.10.2 nathanw static pcireg_t vrpciu_conf_read(pci_chipset_tag_t, pcitag_t, int);
92 1.1.10.2 nathanw static void vrpciu_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
93 1.1.10.4 nathanw static int vrpciu_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
94 1.1.10.4 nathanw static const char *vrpciu_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
95 1.1.10.4 nathanw static const struct evcnt *vrpciu_intr_evcnt(pci_chipset_tag_t,
96 1.1.10.4 nathanw pci_intr_handle_t);
97 1.1.10.2 nathanw static void *vrpciu_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
98 1.1.10.2 nathanw int, int (*)(void *), void *);
99 1.1.10.2 nathanw static void vrpciu_intr_disestablish(pci_chipset_tag_t, void *);
100 1.1.10.2 nathanw
101 1.1.10.2 nathanw struct cfattach vrpciu_ca = {
102 1.1.10.2 nathanw sizeof(struct vrpciu_softc), vrpciu_match, vrpciu_attach
103 1.1.10.2 nathanw };
104 1.1.10.2 nathanw
105 1.1.10.2 nathanw static void
106 1.1.10.2 nathanw vrpciu_write(struct vrpciu_softc *sc, int offset, u_int32_t val)
107 1.1.10.2 nathanw {
108 1.1.10.2 nathanw
109 1.1.10.2 nathanw bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, val);
110 1.1.10.2 nathanw }
111 1.1.10.2 nathanw
112 1.1.10.2 nathanw static u_int32_t
113 1.1.10.2 nathanw vrpciu_read(struct vrpciu_softc *sc, int offset)
114 1.1.10.2 nathanw {
115 1.1.10.2 nathanw
116 1.1.10.2 nathanw return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset));
117 1.1.10.2 nathanw }
118 1.1.10.2 nathanw
119 1.1.10.2 nathanw #ifdef DEBUG
120 1.1.10.2 nathanw static void
121 1.1.10.2 nathanw vrpciu_write_2(struct vrpciu_softc *sc, int offset, u_int16_t val)
122 1.1.10.2 nathanw {
123 1.1.10.2 nathanw
124 1.1.10.2 nathanw bus_space_write_2(sc->sc_iot, sc->sc_ioh, offset, val);
125 1.1.10.2 nathanw }
126 1.1.10.2 nathanw
127 1.1.10.2 nathanw static u_int16_t
128 1.1.10.2 nathanw vrpciu_read_2(struct vrpciu_softc *sc, int offset)
129 1.1.10.2 nathanw {
130 1.1.10.2 nathanw
131 1.1.10.2 nathanw return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset));
132 1.1.10.2 nathanw }
133 1.1.10.2 nathanw #endif
134 1.1.10.2 nathanw
135 1.1.10.2 nathanw static int
136 1.1.10.2 nathanw vrpciu_match(struct device *parent, struct cfdata *match, void *aux)
137 1.1.10.2 nathanw {
138 1.1.10.2 nathanw
139 1.1.10.2 nathanw return (1);
140 1.1.10.2 nathanw }
141 1.1.10.2 nathanw
142 1.1.10.2 nathanw static void
143 1.1.10.2 nathanw vrpciu_attach(struct device *parent, struct device *self, void *aux)
144 1.1.10.2 nathanw {
145 1.1.10.2 nathanw struct vrpciu_softc *sc = (struct vrpciu_softc *)self;
146 1.1.10.2 nathanw pci_chipset_tag_t pc = &sc->sc_pc;
147 1.1.10.2 nathanw struct vrip_attach_args *va = aux;
148 1.1.10.4 nathanw #if defined(DEBUG) || NPCI > 0
149 1.1.10.2 nathanw u_int32_t reg;
150 1.1.10.4 nathanw #endif
151 1.1.10.2 nathanw #if NPCI > 0
152 1.1.10.4 nathanw struct bus_space_tag_hpcmips *iot;
153 1.1.10.4 nathanw char tmpbuf[16];
154 1.1.10.2 nathanw struct pcibus_attach_args pba;
155 1.1.10.2 nathanw #endif
156 1.1.10.2 nathanw
157 1.1.10.2 nathanw sc->sc_vc = va->va_vc;
158 1.1.10.2 nathanw sc->sc_iot = va->va_iot;
159 1.1.10.2 nathanw if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size, 0,
160 1.1.10.2 nathanw &sc->sc_ioh)) {
161 1.1.10.2 nathanw printf(": couldn't map io space\n");
162 1.1.10.2 nathanw return;
163 1.1.10.2 nathanw }
164 1.1.10.2 nathanw
165 1.1.10.4 nathanw sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_unit, 0, IPL_TTY,
166 1.1.10.2 nathanw vrpciu_intr, sc);
167 1.1.10.2 nathanw if (sc->sc_ih == NULL) {
168 1.1.10.2 nathanw printf(": couldn't establish interrupt\n");
169 1.1.10.2 nathanw return;
170 1.1.10.2 nathanw }
171 1.1.10.2 nathanw
172 1.1.10.2 nathanw /* Enable level 2 interrupt */
173 1.1.10.2 nathanw vrip_intr_setmask2(va->va_vc, sc->sc_ih, PCIINT_INT0, 1);
174 1.1.10.2 nathanw
175 1.1.10.2 nathanw printf("\n");
176 1.1.10.2 nathanw
177 1.1.10.2 nathanw #ifdef DEBUG
178 1.1.10.2 nathanw #define DUMP_MAW(sc, name, reg) do { \
179 1.1.10.2 nathanw printf("%s: %s =\t0x%08x\n", (sc)->sc_dev.dv_xname, \
180 1.1.10.2 nathanw (name), (reg)); \
181 1.1.10.2 nathanw printf("%s:\tIBA/MASK =\t0x%08x/0x%08x (0x%08x - 0x%08x)\n", \
182 1.1.10.2 nathanw (sc)->sc_dev.dv_xname, \
183 1.1.10.2 nathanw reg & VRPCIU_MAW_IBAMASK, VRPCIU_MAW_ADDRMASK(reg), \
184 1.1.10.2 nathanw VRPCIU_MAW_ADDR(reg), \
185 1.1.10.2 nathanw VRPCIU_MAW_ADDR(reg) + VRPCIU_MAW_SIZE(reg)); \
186 1.1.10.2 nathanw printf("%s:\tWINEN =\t0x%08x\n", (sc)->sc_dev.dv_xname, \
187 1.1.10.2 nathanw reg & VRPCIU_MAW_WINEN); \
188 1.1.10.2 nathanw printf("%s:\tPCIADR =\t0x%08x\n", (sc)->sc_dev.dv_xname, \
189 1.1.10.2 nathanw VRPCIU_MAW_PCIADDR(reg)); \
190 1.1.10.2 nathanw } while (0)
191 1.1.10.2 nathanw #define DUMP_TAW(sc, name, reg) do { \
192 1.1.10.2 nathanw printf("%s: %s =\t\t0x%08x\n", (sc)->sc_dev.dv_xname, \
193 1.1.10.2 nathanw (name), (reg)); \
194 1.1.10.2 nathanw printf("%s:\tMASK =\t0x%08x\n", (sc)->sc_dev.dv_xname, \
195 1.1.10.2 nathanw VRPCIU_TAW_ADDRMASK(reg)); \
196 1.1.10.2 nathanw printf("%s:\tWINEN =\t0x%08x\n", (sc)->sc_dev.dv_xname, \
197 1.1.10.2 nathanw reg & VRPCIU_TAW_WINEN); \
198 1.1.10.2 nathanw printf("%s:\tIBA =\t0x%08x\n", (sc)->sc_dev.dv_xname, \
199 1.1.10.2 nathanw VRPCIU_TAW_IBA(reg)); \
200 1.1.10.2 nathanw } while (0)
201 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_MMAW1REG);
202 1.1.10.2 nathanw DUMP_MAW(sc, "MMAW1", reg);
203 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_MMAW2REG);
204 1.1.10.2 nathanw DUMP_MAW(sc, "MMAW2", reg);
205 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_TAW1REG);
206 1.1.10.2 nathanw DUMP_TAW(sc, "TAW1", reg);
207 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_TAW2REG);
208 1.1.10.2 nathanw DUMP_TAW(sc, "TAW2", reg);
209 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_MIOAWREG);
210 1.1.10.2 nathanw DUMP_MAW(sc, "MIOAW", reg);
211 1.1.10.2 nathanw printf("%s: BUSERRAD =\t0x%08x\n", sc->sc_dev.dv_xname,
212 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_BUSERRADREG));
213 1.1.10.2 nathanw printf("%s: INTCNTSTA =\t0x%08x\n", sc->sc_dev.dv_xname,
214 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_INTCNTSTAREG));
215 1.1.10.2 nathanw printf("%s: EXACC =\t0x%08x\n", sc->sc_dev.dv_xname,
216 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_EXACCREG));
217 1.1.10.2 nathanw printf("%s: RECONT =\t0x%08x\n", sc->sc_dev.dv_xname,
218 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_RECONTREG));
219 1.1.10.2 nathanw printf("%s: PCIEN =\t0x%08x\n", sc->sc_dev.dv_xname,
220 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_ENREG));
221 1.1.10.2 nathanw printf("%s: CLOCKSEL =\t0x%08x\n", sc->sc_dev.dv_xname,
222 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CLKSELREG));
223 1.1.10.2 nathanw printf("%s: TRDYV =\t0x%08x\n", sc->sc_dev.dv_xname,
224 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_TRDYVREG));
225 1.1.10.2 nathanw printf("%s: CLKRUN =\t0x%08x\n", sc->sc_dev.dv_xname,
226 1.1.10.2 nathanw vrpciu_read_2(sc, VRPCIU_CLKRUNREG));
227 1.1.10.2 nathanw printf("%s: IDREG =\t0x%08x\n", sc->sc_dev.dv_xname,
228 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_ID_REG));
229 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_COMMAND_STATUS_REG);
230 1.1.10.2 nathanw printf("%s: CSR =\t\t0x%08x\n", sc->sc_dev.dv_xname, reg);
231 1.1.10.2 nathanw vrpciu_write(sc, VRPCIU_CONF_BASE + PCI_COMMAND_STATUS_REG, reg);
232 1.1.10.2 nathanw printf("%s: CSR =\t\t0x%08x\n", sc->sc_dev.dv_xname,
233 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_COMMAND_STATUS_REG));
234 1.1.10.2 nathanw printf("%s: CLASS =\t0x%08x\n", sc->sc_dev.dv_xname,
235 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_CLASS_REG));
236 1.1.10.2 nathanw printf("%s: BHLC =\t\t0x%08x\n", sc->sc_dev.dv_xname,
237 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_BHLC_REG));
238 1.1.10.2 nathanw printf("%s: MAIL =\t\t0x%08x\n", sc->sc_dev.dv_xname,
239 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + VRPCIU_CONF_MAILREG));
240 1.1.10.2 nathanw printf("%s: MBA1 =\t\t0x%08x\n", sc->sc_dev.dv_xname,
241 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + VRPCIU_CONF_MBA1REG));
242 1.1.10.2 nathanw printf("%s: MBA2 =\t\t0x%08x\n", sc->sc_dev.dv_xname,
243 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + VRPCIU_CONF_MBA2REG));
244 1.1.10.2 nathanw printf("%s: INTR =\t\t0x%08x\n", sc->sc_dev.dv_xname,
245 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_INTERRUPT_REG));
246 1.1.10.2 nathanw #if 0
247 1.1.10.2 nathanw vrpciu_write(sc, VRPCIU_CONF_BASE + PCI_INTERRUPT_REG,
248 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_INTERRUPT_REG) | 0x01);
249 1.1.10.2 nathanw printf("%s: INTR =\t\t0x%08x\n", sc->sc_dev.dv_xname,
250 1.1.10.2 nathanw vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_INTERRUPT_REG));
251 1.1.10.2 nathanw #endif
252 1.1.10.2 nathanw #endif
253 1.1.10.2 nathanw
254 1.1.10.2 nathanw pc->pc_dev = &sc->sc_dev;
255 1.1.10.2 nathanw pc->pc_attach_hook = vrpciu_attach_hook;
256 1.1.10.2 nathanw pc->pc_bus_maxdevs = vrpciu_bus_maxdevs;
257 1.1.10.3 nathanw pc->pc_bus_devorder = vrpciu_bus_devorder;
258 1.1.10.2 nathanw pc->pc_make_tag = vrpciu_make_tag;
259 1.1.10.2 nathanw pc->pc_decompose_tag = vrpciu_decompose_tag;
260 1.1.10.2 nathanw pc->pc_conf_read = vrpciu_conf_read;
261 1.1.10.2 nathanw pc->pc_conf_write = vrpciu_conf_write;
262 1.1.10.4 nathanw pc->pc_intr_map = vrpciu_intr_map;
263 1.1.10.4 nathanw pc->pc_intr_string = vrpciu_intr_string;
264 1.1.10.4 nathanw pc->pc_intr_evcnt = vrpciu_intr_evcnt;
265 1.1.10.2 nathanw pc->pc_intr_establish = vrpciu_intr_establish;
266 1.1.10.2 nathanw pc->pc_intr_disestablish = vrpciu_intr_disestablish;
267 1.1.10.2 nathanw
268 1.1.10.2 nathanw #if 0
269 1.1.10.2 nathanw {
270 1.1.10.2 nathanw int i;
271 1.1.10.2 nathanw
272 1.1.10.2 nathanw for (i = 0; i < 8; i++)
273 1.1.10.2 nathanw printf("%s: ID_REG(0, 0, %d) = 0x%08x\n",
274 1.1.10.2 nathanw sc->sc_dev.dv_xname, i,
275 1.1.10.2 nathanw pci_conf_read(pc, pci_make_tag(pc, 0, 0, i),
276 1.1.10.2 nathanw PCI_ID_REG));
277 1.1.10.2 nathanw }
278 1.1.10.2 nathanw #endif
279 1.1.10.2 nathanw
280 1.1.10.2 nathanw #if NPCI > 0
281 1.1.10.2 nathanw memset(&pba, 0, sizeof(pba));
282 1.1.10.2 nathanw pba.pba_busname = "pci";
283 1.1.10.2 nathanw
284 1.1.10.2 nathanw /* For now, just inherit window mappings set by WinCE. XXX. */
285 1.1.10.2 nathanw
286 1.1.10.2 nathanw iot = hpcmips_alloc_bus_space_tag();
287 1.1.10.2 nathanw reg = vrpciu_read(sc, VRPCIU_MIOAWREG);
288 1.1.10.2 nathanw snprintf(tmpbuf, sizeof(tmpbuf), "%s/iot",
289 1.1.10.2 nathanw sc->sc_dev.dv_xname);
290 1.1.10.2 nathanw hpcmips_init_bus_space(iot, (struct bus_space_tag_hpcmips *)sc->sc_iot,
291 1.1.10.2 nathanw tmpbuf, VRPCIU_MAW_ADDR(reg), VRPCIU_MAW_SIZE(reg));
292 1.1.10.2 nathanw pba.pba_iot = &iot->bst;
293 1.1.10.2 nathanw
294 1.1.10.2 nathanw /*
295 1.1.10.2 nathanw * Just use system bus space tag. It works since WinCE maps
296 1.1.10.2 nathanw * PCI bus space at same offset. But this isn't right thing
297 1.1.10.2 nathanw * of course. XXX.
298 1.1.10.2 nathanw */
299 1.1.10.2 nathanw pba.pba_memt = sc->sc_iot;
300 1.1.10.2 nathanw pba.pba_dmat = &hpcmips_default_bus_dma_tag.bdt;
301 1.1.10.2 nathanw pba.pba_bus = 0;
302 1.1.10.6 nathanw pba.pba_bridgetag = NULL;
303 1.1.10.4 nathanw
304 1.1.10.4 nathanw if (platid_match(&platid, &platid_mask_MACH_LASER5_L_BOARD)) {
305 1.1.10.4 nathanw /*
306 1.1.10.4 nathanw * fix PCI device configration for L-Router.
307 1.1.10.4 nathanw */
308 1.1.10.4 nathanw /* change IDE controller to native mode */
309 1.1.10.4 nathanw reg = pci_conf_read(pc, pci_make_tag(pc, 0, 16, 0),
310 1.1.10.4 nathanw PCI_CLASS_REG);
311 1.1.10.4 nathanw reg |= PCIIDE_INTERFACE_PCI(0) << PCI_INTERFACE_SHIFT;
312 1.1.10.4 nathanw reg |= PCIIDE_INTERFACE_PCI(1) << PCI_INTERFACE_SHIFT;
313 1.1.10.4 nathanw pci_conf_write(pc, pci_make_tag(pc, 0, 16, 0), PCI_CLASS_REG,
314 1.1.10.4 nathanw reg);
315 1.1.10.4 nathanw /* fix broken BAR setting of fxp0, fxp1 */
316 1.1.10.4 nathanw pci_conf_write(pc, pci_make_tag(pc, 0, 0, 0), PCI_MAPREG_START,
317 1.1.10.4 nathanw 0x11100000);
318 1.1.10.4 nathanw pci_conf_write(pc, pci_make_tag(pc, 0, 1, 0), PCI_MAPREG_START,
319 1.1.10.4 nathanw 0x11200000);
320 1.1.10.4 nathanw }
321 1.1.10.4 nathanw
322 1.1.10.2 nathanw pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
323 1.1.10.2 nathanw PCI_FLAGS_MRL_OKAY;
324 1.1.10.2 nathanw pba.pba_pc = pc;
325 1.1.10.2 nathanw
326 1.1.10.2 nathanw config_found(self, &pba, vrpciu_print);
327 1.1.10.2 nathanw #endif
328 1.1.10.2 nathanw }
329 1.1.10.2 nathanw
330 1.1.10.2 nathanw #if NPCI > 0
331 1.1.10.2 nathanw static int
332 1.1.10.2 nathanw vrpciu_print(void *aux, const char *pnp)
333 1.1.10.2 nathanw {
334 1.1.10.2 nathanw struct pcibus_attach_args *pba = aux;
335 1.1.10.2 nathanw
336 1.1.10.2 nathanw if (pnp != NULL)
337 1.1.10.2 nathanw printf("%s at %s", pba->pba_busname, pnp);
338 1.1.10.2 nathanw else
339 1.1.10.2 nathanw printf(" bus %d", pba->pba_bus);
340 1.1.10.2 nathanw
341 1.1.10.2 nathanw return (UNCONF);
342 1.1.10.2 nathanw }
343 1.1.10.2 nathanw #endif
344 1.1.10.2 nathanw
345 1.1.10.2 nathanw /*
346 1.1.10.2 nathanw * Handle PCI error interrupts.
347 1.1.10.2 nathanw */
348 1.1.10.2 nathanw int
349 1.1.10.2 nathanw vrpciu_intr(void *arg)
350 1.1.10.2 nathanw {
351 1.1.10.2 nathanw struct vrpciu_softc *sc = (struct vrpciu_softc *)arg;
352 1.1.10.5 nathanw u_int32_t isr, baddr;
353 1.1.10.2 nathanw
354 1.1.10.2 nathanw isr = vrpciu_read(sc, VRPCIU_INTCNTSTAREG);
355 1.1.10.5 nathanw baddr = vrpciu_read(sc, VRPCIU_BUSERRADREG);
356 1.1.10.5 nathanw printf("%s: status=0x%08x bad addr=0x%08x\n",
357 1.1.10.5 nathanw sc->sc_dev.dv_xname, isr, baddr);
358 1.1.10.2 nathanw return ((isr & 0x0f) ? 1 : 0);
359 1.1.10.2 nathanw }
360 1.1.10.2 nathanw
361 1.1.10.2 nathanw void
362 1.1.10.2 nathanw vrpciu_attach_hook(struct device *parent, struct device *self,
363 1.1.10.2 nathanw struct pcibus_attach_args *pba)
364 1.1.10.2 nathanw {
365 1.1.10.2 nathanw
366 1.1.10.2 nathanw return;
367 1.1.10.2 nathanw }
368 1.1.10.2 nathanw
369 1.1.10.2 nathanw int
370 1.1.10.2 nathanw vrpciu_bus_maxdevs(pci_chipset_tag_t pc, int busno)
371 1.1.10.2 nathanw {
372 1.1.10.2 nathanw
373 1.1.10.2 nathanw return (32);
374 1.1.10.2 nathanw }
375 1.1.10.2 nathanw
376 1.1.10.3 nathanw int
377 1.1.10.3 nathanw vrpciu_bus_devorder(pci_chipset_tag_t pc, int busno, char *devs)
378 1.1.10.3 nathanw {
379 1.1.10.3 nathanw int i, dev;
380 1.1.10.3 nathanw char priorities[32];
381 1.1.10.3 nathanw static pcireg_t ids[] = {
382 1.1.10.3 nathanw /* these devices should be attached first */
383 1.1.10.3 nathanw PCI_ID_CODE(PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VRC4173_BCU),
384 1.1.10.3 nathanw };
385 1.1.10.3 nathanw
386 1.1.10.3 nathanw /* scan PCI devices and check the id table */
387 1.1.10.3 nathanw memset(priorities, 0, sizeof(priorities));
388 1.1.10.3 nathanw for (dev = 0; dev < 32; dev++) {
389 1.1.10.3 nathanw pcireg_t id;
390 1.1.10.3 nathanw id = pci_conf_read(pc, pci_make_tag(pc, 0, dev, 0),PCI_ID_REG);
391 1.1.10.3 nathanw for (i = 0; i < sizeof(ids)/sizeof(*ids); i++)
392 1.1.10.3 nathanw if (id == ids[i])
393 1.1.10.3 nathanw priorities[dev] = 1;
394 1.1.10.3 nathanw }
395 1.1.10.3 nathanw
396 1.1.10.3 nathanw /* fill order array */
397 1.1.10.3 nathanw for (i = 1; 0 <= i; i--)
398 1.1.10.3 nathanw for (dev = 0; dev < 32; dev++)
399 1.1.10.3 nathanw if (priorities[dev] == i)
400 1.1.10.3 nathanw *devs++ = dev;
401 1.1.10.3 nathanw
402 1.1.10.3 nathanw return (32);
403 1.1.10.3 nathanw }
404 1.1.10.3 nathanw
405 1.1.10.2 nathanw pcitag_t
406 1.1.10.2 nathanw vrpciu_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
407 1.1.10.2 nathanw {
408 1.1.10.2 nathanw
409 1.1.10.2 nathanw return ((bus << 16) | (device << 11) | (function << 8));
410 1.1.10.2 nathanw }
411 1.1.10.2 nathanw
412 1.1.10.2 nathanw void
413 1.1.10.2 nathanw vrpciu_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp,
414 1.1.10.2 nathanw int *fp)
415 1.1.10.2 nathanw {
416 1.1.10.2 nathanw
417 1.1.10.2 nathanw if (bp != NULL)
418 1.1.10.2 nathanw *bp = (tag >> 16) & 0xff;
419 1.1.10.2 nathanw if (dp != NULL)
420 1.1.10.2 nathanw *dp = (tag >> 11) & 0x1f;
421 1.1.10.2 nathanw if (fp != NULL)
422 1.1.10.2 nathanw *fp = (tag >> 8) & 0x07;
423 1.1.10.2 nathanw }
424 1.1.10.2 nathanw
425 1.1.10.2 nathanw pcireg_t
426 1.1.10.2 nathanw vrpciu_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
427 1.1.10.2 nathanw {
428 1.1.10.2 nathanw struct vrpciu_softc *sc = (struct vrpciu_softc *)pc->pc_dev;
429 1.1.10.2 nathanw u_int32_t val;
430 1.1.10.2 nathanw int bus, device, function;
431 1.1.10.2 nathanw
432 1.1.10.2 nathanw pci_decompose_tag(pc, tag, &bus, &device, &function);
433 1.1.10.2 nathanw if (bus == 0) {
434 1.1.10.2 nathanw if (device > 21)
435 1.1.10.2 nathanw return ((pcitag_t)-1);
436 1.1.10.2 nathanw tag = (1 << (device + 11)) | (function << 8); /* Type 0 */
437 1.1.10.2 nathanw } else
438 1.1.10.2 nathanw tag |= VRPCIU_CONF_TYPE1;
439 1.1.10.2 nathanw
440 1.1.10.2 nathanw vrpciu_write(sc, VRPCIU_CONFAREG, tag | reg);
441 1.1.10.2 nathanw val = vrpciu_read(sc, VRPCIU_CONFDREG);
442 1.1.10.2 nathanw #if 0
443 1.1.10.2 nathanw printf("%s: conf_read: tag = 0x%08x, reg = 0x%x, val = 0x%08x\n",
444 1.1.10.2 nathanw sc->sc_dev.dv_xname, (u_int32_t)tag, reg, val);
445 1.1.10.2 nathanw #endif
446 1.1.10.2 nathanw return (val);
447 1.1.10.2 nathanw }
448 1.1.10.2 nathanw
449 1.1.10.2 nathanw void
450 1.1.10.2 nathanw vrpciu_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg,
451 1.1.10.2 nathanw pcireg_t data)
452 1.1.10.2 nathanw {
453 1.1.10.2 nathanw struct vrpciu_softc *sc = (struct vrpciu_softc *)pc->pc_dev;
454 1.1.10.2 nathanw int bus, device, function;
455 1.1.10.2 nathanw
456 1.1.10.2 nathanw #if 0
457 1.1.10.2 nathanw printf("%s: conf_write: tag = 0x%08x, reg = 0x%x, val = 0x%08x\n",
458 1.1.10.2 nathanw sc->sc_dev.dv_xname, (u_int32_t)tag, reg, (u_int32_t)data);
459 1.1.10.2 nathanw #endif
460 1.1.10.2 nathanw vrpciu_decompose_tag(pc, tag, &bus, &device, &function);
461 1.1.10.2 nathanw if (bus == 0) {
462 1.1.10.2 nathanw if (device > 21)
463 1.1.10.2 nathanw return;
464 1.1.10.2 nathanw tag = (1 << (device + 11)) | (function << 8); /* Type 0 */
465 1.1.10.2 nathanw } else
466 1.1.10.2 nathanw tag |= VRPCIU_CONF_TYPE1;
467 1.1.10.2 nathanw
468 1.1.10.2 nathanw vrpciu_write(sc, VRPCIU_CONFAREG, tag | reg);
469 1.1.10.2 nathanw vrpciu_write(sc, VRPCIU_CONFDREG, data);
470 1.1.10.2 nathanw }
471 1.1.10.2 nathanw
472 1.1.10.4 nathanw int
473 1.1.10.4 nathanw vrpciu_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
474 1.1.10.2 nathanw {
475 1.1.10.4 nathanw pci_chipset_tag_t pc = pa->pa_pc;
476 1.1.10.4 nathanw pcitag_t intrtag = pa->pa_intrtag;
477 1.1.10.4 nathanw int bus, dev, func;
478 1.1.10.4 nathanw #ifdef DEBUG
479 1.1.10.4 nathanw int line = pa->pa_intrline;
480 1.1.10.4 nathanw int pin = pa->pa_intrpin;
481 1.1.10.4 nathanw #endif
482 1.1.10.2 nathanw
483 1.1.10.4 nathanw pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
484 1.1.10.4 nathanw DPRINTF(("%s(%d, %d, %d): line = %d, pin = %d\n", pc->pc_dev->dv_xname,
485 1.1.10.4 nathanw bus, dev, func, line, pin));
486 1.1.10.4 nathanw
487 1.1.10.4 nathanw *ihp = CONFIG_HOOK_PCIINTR_ID(bus, dev, func);
488 1.1.10.4 nathanw
489 1.1.10.4 nathanw return (0);
490 1.1.10.2 nathanw }
491 1.1.10.2 nathanw
492 1.1.10.4 nathanw const char *
493 1.1.10.4 nathanw vrpciu_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
494 1.1.10.2 nathanw {
495 1.1.10.4 nathanw static char irqstr[sizeof("pciintr") + 16];
496 1.1.10.2 nathanw
497 1.1.10.4 nathanw snprintf(irqstr, sizeof(irqstr), "pciintr %d:%d:%d",
498 1.1.10.4 nathanw CONFIG_HOOK_PCIINTR_BUS((int)ih),
499 1.1.10.4 nathanw CONFIG_HOOK_PCIINTR_DEVICE((int)ih),
500 1.1.10.4 nathanw CONFIG_HOOK_PCIINTR_FUNCTION((int)ih));
501 1.1.10.4 nathanw
502 1.1.10.4 nathanw return (irqstr);
503 1.1.10.2 nathanw }
504 1.1.10.2 nathanw
505 1.1.10.4 nathanw const struct evcnt *
506 1.1.10.4 nathanw vrpciu_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
507 1.1.10.2 nathanw {
508 1.1.10.2 nathanw
509 1.1.10.4 nathanw /* XXX for now, no evcnt parent reported */
510 1.1.10.3 nathanw
511 1.1.10.4 nathanw return (NULL);
512 1.1.10.4 nathanw }
513 1.1.10.3 nathanw
514 1.1.10.4 nathanw void *
515 1.1.10.4 nathanw vrpciu_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
516 1.1.10.4 nathanw int (*func)(void *), void *arg)
517 1.1.10.4 nathanw {
518 1.1.10.2 nathanw
519 1.1.10.4 nathanw if (ih == -1)
520 1.1.10.4 nathanw return (NULL);
521 1.1.10.4 nathanw DPRINTF(("vrpciu_intr_establish: %lx\n", ih));
522 1.1.10.4 nathanw
523 1.1.10.4 nathanw return (config_hook(CONFIG_HOOK_PCIINTR, ih, CONFIG_HOOK_EXCLUSIVE,
524 1.1.10.4 nathanw (int (*)(void *, int, long, void *))func, arg));
525 1.1.10.2 nathanw }
526 1.1.10.2 nathanw
527 1.1.10.2 nathanw void
528 1.1.10.4 nathanw vrpciu_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
529 1.1.10.2 nathanw {
530 1.1.10.2 nathanw
531 1.1.10.4 nathanw DPRINTF(("vrpciu_intr_disestablish: %p\n", cookie));
532 1.1.10.4 nathanw config_unhook(cookie);
533 1.1.10.2 nathanw }
534