hd64461pcmcia.c revision 1.16.2.3
1 1.16.2.3 thorpej /* $NetBSD: hd64461pcmcia.c,v 1.16.2.3 2003/01/03 16:45:10 thorpej Exp $ */ 2 1.16.2.2 nathanw 3 1.16.2.2 nathanw /*- 4 1.16.2.2 nathanw * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 1.16.2.2 nathanw * All rights reserved. 6 1.16.2.2 nathanw * 7 1.16.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.16.2.2 nathanw * by UCHIYAMA Yasushi. 9 1.16.2.2 nathanw * 10 1.16.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.16.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.16.2.2 nathanw * are met: 13 1.16.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.16.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.16.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.16.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.16.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.16.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.16.2.2 nathanw * must display the following acknowledgement: 20 1.16.2.2 nathanw * This product includes software developed by the NetBSD 21 1.16.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.16.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.16.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.16.2.2 nathanw * from this software without specific prior written permission. 25 1.16.2.2 nathanw * 26 1.16.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.16.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.16.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.16.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.16.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.16.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.16.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.16.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.16.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.16.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.16.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.16.2.2 nathanw */ 38 1.16.2.2 nathanw 39 1.16.2.2 nathanw #include "debug_hpcsh.h" 40 1.16.2.2 nathanw 41 1.16.2.2 nathanw #include <sys/param.h> 42 1.16.2.2 nathanw #include <sys/systm.h> 43 1.16.2.2 nathanw #include <sys/device.h> 44 1.16.2.2 nathanw #include <sys/malloc.h> 45 1.16.2.2 nathanw #include <sys/kthread.h> 46 1.16.2.2 nathanw #include <sys/boot_flag.h> 47 1.16.2.2 nathanw 48 1.16.2.2 nathanw #include <machine/bus.h> 49 1.16.2.2 nathanw #include <machine/intr.h> 50 1.16.2.2 nathanw 51 1.16.2.2 nathanw #include <dev/pcmcia/pcmciareg.h> 52 1.16.2.2 nathanw #include <dev/pcmcia/pcmciavar.h> 53 1.16.2.2 nathanw #include <dev/pcmcia/pcmciachip.h> 54 1.16.2.2 nathanw 55 1.16.2.2 nathanw #include <sh3/bscreg.h> 56 1.16.2.2 nathanw 57 1.16.2.2 nathanw #include <hpcsh/dev/hd64461/hd64461reg.h> 58 1.16.2.2 nathanw #include <hpcsh/dev/hd64461/hd64461var.h> 59 1.16.2.2 nathanw #include <hpcsh/dev/hd64461/hd64461intcreg.h> 60 1.16.2.2 nathanw #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 61 1.16.2.2 nathanw #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 62 1.16.2.2 nathanw #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 63 1.16.2.2 nathanw 64 1.16.2.2 nathanw #include "locators.h" 65 1.16.2.2 nathanw 66 1.16.2.2 nathanw #ifdef HD64461PCMCIA_DEBUG 67 1.16.2.2 nathanw #define DPRINTF_ENABLE 68 1.16.2.2 nathanw #define DPRINTF_DEBUG hd64461pcmcia_debug 69 1.16.2.2 nathanw #endif 70 1.16.2.2 nathanw #include <machine/debug.h> 71 1.16.2.2 nathanw 72 1.16.2.2 nathanw enum controller_channel { 73 1.16.2.2 nathanw CHANNEL_0 = 0, 74 1.16.2.2 nathanw CHANNEL_1 = 1, 75 1.16.2.2 nathanw CHANNEL_MAX = 2 76 1.16.2.2 nathanw }; 77 1.16.2.2 nathanw 78 1.16.2.2 nathanw enum memory_window_mode { 79 1.16.2.2 nathanw MEMWIN_16M_MODE, 80 1.16.2.2 nathanw MEMWIN_32M_MODE 81 1.16.2.2 nathanw }; 82 1.16.2.2 nathanw 83 1.16.2.2 nathanw enum memory_window_16 { 84 1.16.2.2 nathanw MEMWIN_16M_COMMON_0, 85 1.16.2.2 nathanw MEMWIN_16M_COMMON_1, 86 1.16.2.2 nathanw MEMWIN_16M_COMMON_2, 87 1.16.2.2 nathanw MEMWIN_16M_COMMON_3, 88 1.16.2.2 nathanw }; 89 1.16.2.2 nathanw #define MEMWIN_16M_MAX 4 90 1.16.2.2 nathanw 91 1.16.2.2 nathanw enum memory_window_32 { 92 1.16.2.2 nathanw MEMWIN_32M_ATTR, 93 1.16.2.2 nathanw MEMWIN_32M_COMMON_0, 94 1.16.2.2 nathanw MEMWIN_32M_COMMON_1, 95 1.16.2.2 nathanw }; 96 1.16.2.2 nathanw #define MEMWIN_32M_MAX 3 97 1.16.2.2 nathanw 98 1.16.2.2 nathanw enum hd64461pcmcia_event_type { 99 1.16.2.2 nathanw EVENT_NONE, 100 1.16.2.2 nathanw EVENT_INSERT, 101 1.16.2.2 nathanw EVENT_REMOVE, 102 1.16.2.2 nathanw }; 103 1.16.2.2 nathanw #define EVENT_QUEUE_MAX 5 104 1.16.2.2 nathanw 105 1.16.2.2 nathanw struct hd64461pcmcia_softc; /* forward declaration */ 106 1.16.2.2 nathanw 107 1.16.2.2 nathanw struct hd64461pcmcia_window_cookie { 108 1.16.2.2 nathanw bus_space_tag_t wc_tag; 109 1.16.2.2 nathanw bus_space_handle_t wc_handle; 110 1.16.2.2 nathanw int wc_size; 111 1.16.2.2 nathanw int wc_window; 112 1.16.2.2 nathanw }; 113 1.16.2.2 nathanw 114 1.16.2.2 nathanw struct hd64461pcmcia_channel { 115 1.16.2.2 nathanw struct hd64461pcmcia_softc *ch_parent; 116 1.16.2.2 nathanw struct device *ch_pcmcia; 117 1.16.2.2 nathanw enum controller_channel ch_channel; 118 1.16.2.2 nathanw 119 1.16.2.2 nathanw /* memory space */ 120 1.16.2.2 nathanw enum memory_window_mode ch_memory_window_mode; 121 1.16.2.2 nathanw bus_space_tag_t ch_memt; 122 1.16.2.2 nathanw bus_space_handle_t ch_memh; 123 1.16.2.2 nathanw bus_addr_t ch_membase_addr; 124 1.16.2.2 nathanw bus_size_t ch_memsize; 125 1.16.2.2 nathanw bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 126 1.16.2.2 nathanw 127 1.16.2.2 nathanw /* I/O space */ 128 1.16.2.2 nathanw bus_space_tag_t ch_iot; 129 1.16.2.2 nathanw bus_addr_t ch_iobase; 130 1.16.2.2 nathanw bus_size_t ch_iosize; 131 1.16.2.2 nathanw 132 1.16.2.2 nathanw /* card interrupt */ 133 1.16.2.2 nathanw int (*ch_ih_card_func)(void *); 134 1.16.2.2 nathanw void *ch_ih_card_arg; 135 1.16.2.2 nathanw int ch_attached; 136 1.16.2.2 nathanw }; 137 1.16.2.2 nathanw 138 1.16.2.2 nathanw struct hd64461pcmcia_event { 139 1.16.2.2 nathanw int __queued; 140 1.16.2.2 nathanw enum hd64461pcmcia_event_type pe_type; 141 1.16.2.2 nathanw struct hd64461pcmcia_channel *pe_ch; 142 1.16.2.2 nathanw SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 143 1.16.2.2 nathanw }; 144 1.16.2.2 nathanw 145 1.16.2.2 nathanw struct hd64461pcmcia_softc { 146 1.16.2.2 nathanw struct device sc_dev; 147 1.16.2.2 nathanw enum hd64461_module_id sc_module_id; 148 1.16.2.2 nathanw int sc_shutdown; 149 1.16.2.2 nathanw 150 1.16.2.2 nathanw /* CSC event */ 151 1.16.2.2 nathanw struct proc *sc_event_thread; 152 1.16.2.2 nathanw struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 153 1.16.2.2 nathanw SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 154 1.16.2.2 nathanw 155 1.16.2.2 nathanw struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 156 1.16.2.2 nathanw }; 157 1.16.2.2 nathanw 158 1.16.2.2 nathanw STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 159 1.16.2.2 nathanw struct pcmcia_mem_handle *); 160 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 161 1.16.2.2 nathanw struct pcmcia_mem_handle *); 162 1.16.2.2 nathanw STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 163 1.16.2.2 nathanw bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 164 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 165 1.16.2.2 nathanw STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 166 1.16.2.2 nathanw bus_size_t, bus_size_t, struct pcmcia_io_handle *); 167 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 168 1.16.2.2 nathanw struct pcmcia_io_handle *); 169 1.16.2.2 nathanw STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 170 1.16.2.2 nathanw bus_size_t, struct pcmcia_io_handle *, int *); 171 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 172 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 173 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 174 1.16.2.2 nathanw STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 1.16.2.2 nathanw struct pcmcia_function *, int, int (*)(void *), void *); 176 1.16.2.2 nathanw STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 1.16.2.2 nathanw void *); 178 1.16.2.2 nathanw 179 1.16.2.2 nathanw STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 1.16.2.2 nathanw hd64461pcmcia_chip_mem_alloc, 181 1.16.2.2 nathanw hd64461pcmcia_chip_mem_free, 182 1.16.2.2 nathanw hd64461pcmcia_chip_mem_map, 183 1.16.2.2 nathanw hd64461pcmcia_chip_mem_unmap, 184 1.16.2.2 nathanw hd64461pcmcia_chip_io_alloc, 185 1.16.2.2 nathanw hd64461pcmcia_chip_io_free, 186 1.16.2.2 nathanw hd64461pcmcia_chip_io_map, 187 1.16.2.2 nathanw hd64461pcmcia_chip_io_unmap, 188 1.16.2.2 nathanw hd64461pcmcia_chip_intr_establish, 189 1.16.2.2 nathanw hd64461pcmcia_chip_intr_disestablish, 190 1.16.2.2 nathanw hd64461pcmcia_chip_socket_enable, 191 1.16.2.2 nathanw hd64461pcmcia_chip_socket_disable, 192 1.16.2.2 nathanw }; 193 1.16.2.2 nathanw 194 1.16.2.2 nathanw STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 195 1.16.2.2 nathanw STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 196 1.16.2.2 nathanw STATIC int hd64461pcmcia_print(void *, const char *); 197 1.16.2.2 nathanw STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 198 1.16.2.2 nathanw 199 1.16.2.2 nathanw CFATTACH_DECL(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 200 1.16.2.2 nathanw hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 201 1.16.2.2 nathanw 202 1.16.2.2 nathanw STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 203 1.16.2.2 nathanw enum controller_channel); 204 1.16.2.2 nathanw /* hot plug */ 205 1.16.2.2 nathanw STATIC void hd64461pcmcia_create_event_thread(void *); 206 1.16.2.2 nathanw STATIC void hd64461pcmcia_event_thread(void *); 207 1.16.2.2 nathanw STATIC void queue_event(struct hd64461pcmcia_channel *, 208 1.16.2.2 nathanw enum hd64461pcmcia_event_type); 209 1.16.2.2 nathanw /* interrupt handler */ 210 1.16.2.2 nathanw STATIC int hd64461pcmcia_channel0_intr(void *); 211 1.16.2.2 nathanw STATIC int hd64461pcmcia_channel1_intr(void *); 212 1.16.2.2 nathanw /* card status */ 213 1.16.2.2 nathanw STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 214 1.16.2.2 nathanw STATIC void hd64461pcmcia_power_off(enum controller_channel) 215 1.16.2.2 nathanw __attribute__((__unused__)); 216 1.16.2.2 nathanw STATIC void hd64461pcmcia_power_on(enum controller_channel) 217 1.16.2.2 nathanw __attribute__((__unused__)); 218 1.16.2.2 nathanw /* memory window access ops */ 219 1.16.2.2 nathanw STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 220 1.16.2.2 nathanw enum memory_window_mode)__attribute__((__unused__)); 221 1.16.2.2 nathanw STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 222 1.16.2.2 nathanw enum memory_window_16); 223 1.16.2.2 nathanw /* bus width */ 224 1.16.2.2 nathanw STATIC void hd64461_set_bus_width(enum controller_channel, int); 225 1.16.2.2 nathanw #ifdef HD64461PCMCIA_DEBUG 226 1.16.2.2 nathanw STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 227 1.16.2.2 nathanw #endif 228 1.16.2.2 nathanw /* fix SH3 Area[56] bug */ 229 1.16.2.2 nathanw STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 230 1.16.2.2 nathanw #define _BUS_SPACE_ACCESS_HOOK() \ 231 1.16.2.2 nathanw do { \ 232 1.16.2.2 nathanw u_int8_t dummy __attribute__((__unused__)) = \ 233 1.16.2.2 nathanw *(volatile u_int8_t *)0xba000000; \ 234 1.16.2.2 nathanw } while (/*CONSTCOND*/0) 235 1.16.2.2 nathanw _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 236 1.16.2.2 nathanw _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 237 1.16.2.2 nathanw _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 238 1.16.2.2 nathanw _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 239 1.16.2.2 nathanw #undef _BUS_SPACE_ACCESS_HOOK 240 1.16.2.2 nathanw 241 1.16.2.2 nathanw #define DELAY_MS(x) delay((x) * 1000) 242 1.16.2.2 nathanw 243 1.16.2.2 nathanw int 244 1.16.2.2 nathanw hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 245 1.16.2.2 nathanw { 246 1.16.2.2 nathanw struct hd64461_attach_args *ha = aux; 247 1.16.2.2 nathanw 248 1.16.2.2 nathanw return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 249 1.16.2.2 nathanw } 250 1.16.2.2 nathanw 251 1.16.2.2 nathanw void 252 1.16.2.2 nathanw hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 253 1.16.2.2 nathanw { 254 1.16.2.2 nathanw struct hd64461_attach_args *ha = aux; 255 1.16.2.2 nathanw struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 256 1.16.2.2 nathanw 257 1.16.2.2 nathanw sc->sc_module_id = ha->ha_module_id; 258 1.16.2.2 nathanw 259 1.16.2.2 nathanw printf("\n"); 260 1.16.2.2 nathanw 261 1.16.2.2 nathanw #ifdef HD64461PCMCIA_DEBUG 262 1.16.2.2 nathanw hd64461pcmcia_info(sc); 263 1.16.2.2 nathanw #endif 264 1.16.2.2 nathanw /* Channel 0/1 common CSC event queue */ 265 1.16.2.2 nathanw SIMPLEQ_INIT (&sc->sc_event_head); 266 1.16.2.2 nathanw kthread_create(hd64461pcmcia_create_event_thread, sc); 267 1.16.2.2 nathanw 268 1.16.2.2 nathanw hd64461pcmcia_attach_channel(sc, CHANNEL_0); 269 1.16.2.2 nathanw hd64461pcmcia_attach_channel(sc, CHANNEL_1); 270 1.16.2.2 nathanw } 271 1.16.2.2 nathanw 272 1.16.2.2 nathanw void 273 1.16.2.2 nathanw hd64461pcmcia_create_event_thread(void *arg) 274 1.16.2.2 nathanw { 275 1.16.2.2 nathanw struct hd64461pcmcia_softc *sc = arg; 276 1.16.2.2 nathanw int error; 277 1.16.2.2 nathanw 278 1.16.2.2 nathanw error = kthread_create1(hd64461pcmcia_event_thread, sc, 279 1.16.2.2 nathanw &sc->sc_event_thread, "%s", 280 1.16.2.2 nathanw sc->sc_dev.dv_xname); 281 1.16.2.2 nathanw KASSERT(error == 0); 282 1.16.2.2 nathanw } 283 1.16.2.2 nathanw 284 1.16.2.2 nathanw void 285 1.16.2.2 nathanw hd64461pcmcia_event_thread(void *arg) 286 1.16.2.2 nathanw { 287 1.16.2.2 nathanw struct hd64461pcmcia_softc *sc = arg; 288 1.16.2.2 nathanw struct hd64461pcmcia_event *pe; 289 1.16.2.2 nathanw int s; 290 1.16.2.2 nathanw 291 1.16.2.2 nathanw while (!sc->sc_shutdown) { 292 1.16.2.2 nathanw tsleep(sc, PWAIT, "CSC wait", 0); 293 1.16.2.2 nathanw s = splhigh(); 294 1.16.2.2 nathanw while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 295 1.16.2.2 nathanw splx(s); 296 1.16.2.2 nathanw switch (pe->pe_type) { 297 1.16.2.2 nathanw default: 298 1.16.2.2 nathanw printf("%s: unknown event.\n", __FUNCTION__); 299 1.16.2.2 nathanw break; 300 1.16.2.2 nathanw case EVENT_INSERT: 301 1.16.2.2 nathanw DPRINTF("insert event.\n"); 302 1.16.2.2 nathanw pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 303 1.16.2.2 nathanw break; 304 1.16.2.2 nathanw case EVENT_REMOVE: 305 1.16.2.2 nathanw DPRINTF("remove event.\n"); 306 1.16.2.2 nathanw pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 307 1.16.2.2 nathanw DETACH_FORCE); 308 1.16.2.2 nathanw break; 309 1.16.2.2 nathanw } 310 1.16.2.2 nathanw s = splhigh(); 311 1.16.2.2 nathanw SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 312 1.16.2.2 nathanw pe->__queued = 0; 313 1.16.2.2 nathanw } 314 1.16.2.2 nathanw splx(s); 315 1.16.2.2 nathanw } 316 1.16.2.2 nathanw /* NOTREACHED */ 317 1.16.2.2 nathanw } 318 1.16.2.2 nathanw 319 1.16.2.2 nathanw int 320 1.16.2.2 nathanw hd64461pcmcia_print(void *arg, const char *pnp) 321 1.16.2.2 nathanw { 322 1.16.2.2 nathanw 323 1.16.2.2 nathanw if (pnp) 324 1.16.2.3 thorpej aprint_normal("pcmcia at %s", pnp); 325 1.16.2.2 nathanw 326 1.16.2.2 nathanw return (UNCONF); 327 1.16.2.2 nathanw } 328 1.16.2.2 nathanw 329 1.16.2.2 nathanw int 330 1.16.2.2 nathanw hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 331 1.16.2.2 nathanw { 332 1.16.2.2 nathanw struct pcmciabus_attach_args *paa = aux; 333 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = 334 1.16.2.2 nathanw (struct hd64461pcmcia_channel *)paa->pch; 335 1.16.2.2 nathanw 336 1.16.2.2 nathanw if (ch->ch_channel == CHANNEL_0) { 337 1.16.2.2 nathanw if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 338 1.16.2.2 nathanw PCMCIABUSCF_CONTROLLER_DEFAULT && 339 1.16.2.2 nathanw cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 340 1.16.2.2 nathanw return 0; 341 1.16.2.2 nathanw } else { 342 1.16.2.2 nathanw if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 343 1.16.2.2 nathanw PCMCIABUSCF_CONTROLLER_DEFAULT && 344 1.16.2.2 nathanw cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 345 1.16.2.2 nathanw return 0; 346 1.16.2.2 nathanw } 347 1.16.2.2 nathanw paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 348 1.16.2.2 nathanw 349 1.16.2.2 nathanw return (config_match(parent, cf, aux)); 350 1.16.2.2 nathanw } 351 1.16.2.2 nathanw 352 1.16.2.2 nathanw void 353 1.16.2.2 nathanw hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 354 1.16.2.2 nathanw enum controller_channel channel) 355 1.16.2.2 nathanw { 356 1.16.2.2 nathanw struct device *parent = (struct device *)sc; 357 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 358 1.16.2.2 nathanw struct pcmciabus_attach_args paa; 359 1.16.2.2 nathanw bus_addr_t membase; 360 1.16.2.2 nathanw int i; 361 1.16.2.2 nathanw 362 1.16.2.2 nathanw ch->ch_parent = sc; 363 1.16.2.2 nathanw ch->ch_channel = channel; 364 1.16.2.2 nathanw 365 1.16.2.2 nathanw /* 366 1.16.2.2 nathanw * Continuous 16-MB Area Mode 367 1.16.2.2 nathanw */ 368 1.16.2.2 nathanw /* Attibute/Common memory extent */ 369 1.16.2.2 nathanw membase = (channel == CHANNEL_0) 370 1.16.2.2 nathanw ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 371 1.16.2.2 nathanw 372 1.16.2.2 nathanw ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 373 1.16.2.2 nathanw membase, 0x01000000); /* 16MB */ 374 1.16.2.2 nathanw bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 375 1.16.2.2 nathanw 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 376 1.16.2.2 nathanw &ch->ch_memh); 377 1.16.2.2 nathanw fixup_sh3_pcmcia_area(ch->ch_memt); 378 1.16.2.2 nathanw 379 1.16.2.2 nathanw /* Common memory space extent */ 380 1.16.2.2 nathanw ch->ch_memsize = 0x01000000; 381 1.16.2.2 nathanw for (i = 0; i < MEMWIN_16M_MAX; i++) { 382 1.16.2.2 nathanw ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 383 1.16.2.2 nathanw membase + 0x01000000, 384 1.16.2.2 nathanw ch->ch_memsize); 385 1.16.2.2 nathanw fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 386 1.16.2.2 nathanw } 387 1.16.2.2 nathanw 388 1.16.2.2 nathanw /* I/O port extent and interrupt staff */ 389 1.16.2.2 nathanw hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 390 1.16.2.2 nathanw 391 1.16.2.2 nathanw if (channel == CHANNEL_0) { 392 1.16.2.2 nathanw ch->ch_iobase = 0; 393 1.16.2.2 nathanw ch->ch_iosize = HD64461_PCC0_IOSIZE; 394 1.16.2.2 nathanw ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 395 1.16.2.2 nathanw HD64461_PCC0_IOBASE, 396 1.16.2.2 nathanw ch->ch_iosize); 397 1.16.2.2 nathanw fixup_sh3_pcmcia_area(ch->ch_iot); 398 1.16.2.2 nathanw 399 1.16.2.2 nathanw hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 400 1.16.2.2 nathanw hd64461pcmcia_channel0_intr, ch); 401 1.16.2.2 nathanw } else { 402 1.16.2.2 nathanw hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 403 1.16.2.2 nathanw hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 404 1.16.2.2 nathanw hd64461pcmcia_channel1_intr, ch); 405 1.16.2.2 nathanw } 406 1.16.2.2 nathanw 407 1.16.2.2 nathanw paa.paa_busname = "pcmcia"; 408 1.16.2.2 nathanw paa.pch = (pcmcia_chipset_handle_t)ch; 409 1.16.2.2 nathanw paa.iobase = ch->ch_iobase; 410 1.16.2.2 nathanw paa.iosize = ch->ch_iosize; 411 1.16.2.2 nathanw 412 1.16.2.2 nathanw ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 413 1.16.2.2 nathanw hd64461pcmcia_submatch); 414 1.16.2.2 nathanw 415 1.16.2.2 nathanw if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 416 1.16.2.2 nathanw ch->ch_attached = 1; 417 1.16.2.2 nathanw pcmcia_card_attach(ch->ch_pcmcia); 418 1.16.2.2 nathanw } 419 1.16.2.2 nathanw } 420 1.16.2.2 nathanw 421 1.16.2.2 nathanw int 422 1.16.2.2 nathanw hd64461pcmcia_channel0_intr(void *arg) 423 1.16.2.2 nathanw { 424 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 425 1.16.2.2 nathanw u_int8_t r; 426 1.16.2.2 nathanw int ret = 0; 427 1.16.2.2 nathanw 428 1.16.2.2 nathanw r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 429 1.16.2.2 nathanw /* clear interrtupt (edge source only) */ 430 1.16.2.2 nathanw hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 431 1.16.2.2 nathanw 432 1.16.2.2 nathanw if (r & HD64461_PCC0CSCR_P0IREQ) { 433 1.16.2.2 nathanw if (ch->ch_ih_card_func) { 434 1.16.2.2 nathanw ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 435 1.16.2.2 nathanw } else 436 1.16.2.2 nathanw DPRINTF("spurious IREQ interrupt.\n"); 437 1.16.2.2 nathanw } 438 1.16.2.2 nathanw 439 1.16.2.2 nathanw if (r & HD64461_PCC0CSCR_P0CDC) 440 1.16.2.2 nathanw queue_event(ch, detect_card(ch->ch_channel)); 441 1.16.2.2 nathanw 442 1.16.2.2 nathanw return ret; 443 1.16.2.2 nathanw } 444 1.16.2.2 nathanw 445 1.16.2.2 nathanw int 446 1.16.2.2 nathanw hd64461pcmcia_channel1_intr(void *arg) 447 1.16.2.2 nathanw { 448 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 449 1.16.2.2 nathanw u_int8_t r; 450 1.16.2.2 nathanw int ret = 0; 451 1.16.2.2 nathanw 452 1.16.2.2 nathanw r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 453 1.16.2.2 nathanw /* clear interrtupt */ 454 1.16.2.2 nathanw hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 455 1.16.2.2 nathanw 456 1.16.2.2 nathanw if (r & HD64461_PCC1CSCR_P1RC) { 457 1.16.2.2 nathanw if (ch->ch_ih_card_func) 458 1.16.2.2 nathanw ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 459 1.16.2.2 nathanw else 460 1.16.2.2 nathanw DPRINTF("spurious READY interrupt.\n"); 461 1.16.2.2 nathanw } 462 1.16.2.2 nathanw 463 1.16.2.2 nathanw if (r & HD64461_PCC1CSCR_P1CDC) 464 1.16.2.2 nathanw queue_event(ch, detect_card(ch->ch_channel)); 465 1.16.2.2 nathanw 466 1.16.2.2 nathanw return ret; 467 1.16.2.2 nathanw } 468 1.16.2.2 nathanw 469 1.16.2.2 nathanw void 470 1.16.2.2 nathanw queue_event(struct hd64461pcmcia_channel *ch, 471 1.16.2.2 nathanw enum hd64461pcmcia_event_type type) 472 1.16.2.2 nathanw { 473 1.16.2.2 nathanw struct hd64461pcmcia_event *pe, *pool; 474 1.16.2.2 nathanw struct hd64461pcmcia_softc *sc = ch->ch_parent; 475 1.16.2.2 nathanw int i; 476 1.16.2.2 nathanw int s = splhigh(); 477 1.16.2.2 nathanw 478 1.16.2.2 nathanw if (type == EVENT_NONE) 479 1.16.2.2 nathanw goto out; 480 1.16.2.2 nathanw 481 1.16.2.2 nathanw pe = 0; 482 1.16.2.2 nathanw pool = sc->sc_event_pool; 483 1.16.2.2 nathanw for (i = 0; i < EVENT_QUEUE_MAX; i++) { 484 1.16.2.2 nathanw if (!pool[i].__queued) { 485 1.16.2.2 nathanw pe = &pool[i]; 486 1.16.2.2 nathanw break; 487 1.16.2.2 nathanw } 488 1.16.2.2 nathanw } 489 1.16.2.2 nathanw 490 1.16.2.2 nathanw if (pe == 0) { 491 1.16.2.2 nathanw printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 492 1.16.2.2 nathanw EVENT_QUEUE_MAX); 493 1.16.2.2 nathanw goto out; 494 1.16.2.2 nathanw } 495 1.16.2.2 nathanw 496 1.16.2.2 nathanw if ((ch->ch_attached && (type == EVENT_INSERT)) || 497 1.16.2.2 nathanw (!ch->ch_attached && (type == EVENT_REMOVE))) { 498 1.16.2.2 nathanw DPRINTF("spurious CSC interrupt.\n"); 499 1.16.2.2 nathanw goto out; 500 1.16.2.2 nathanw } 501 1.16.2.2 nathanw 502 1.16.2.2 nathanw ch->ch_attached = (type == EVENT_INSERT); 503 1.16.2.2 nathanw pe->__queued = 1; 504 1.16.2.2 nathanw pe->pe_type = type; 505 1.16.2.2 nathanw pe->pe_ch = ch; 506 1.16.2.2 nathanw SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 507 1.16.2.2 nathanw wakeup(sc); 508 1.16.2.2 nathanw out: 509 1.16.2.2 nathanw splx(s); 510 1.16.2.2 nathanw } 511 1.16.2.2 nathanw 512 1.16.2.2 nathanw /* 513 1.16.2.2 nathanw * interface for pcmcia driver. 514 1.16.2.2 nathanw */ 515 1.16.2.2 nathanw void * 516 1.16.2.2 nathanw hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 517 1.16.2.2 nathanw struct pcmcia_function *pf, 518 1.16.2.2 nathanw int ipl, int (*ih_func)(void *), void *ih_arg) 519 1.16.2.2 nathanw { 520 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 521 1.16.2.2 nathanw int channel = ch->ch_channel; 522 1.16.2.2 nathanw bus_addr_t cscier = HD64461_PCCCSCIER(channel); 523 1.16.2.2 nathanw int s = splhigh(); 524 1.16.2.2 nathanw u_int8_t r; 525 1.16.2.2 nathanw 526 1.16.2.2 nathanw ch->ch_ih_card_func = ih_func; 527 1.16.2.2 nathanw ch->ch_ih_card_arg = ih_arg; 528 1.16.2.2 nathanw 529 1.16.2.2 nathanw /* enable card interrupt */ 530 1.16.2.2 nathanw r = hd64461_reg_read_1(cscier); 531 1.16.2.2 nathanw if (channel == CHANNEL_0) { 532 1.16.2.2 nathanw /* set level mode */ 533 1.16.2.2 nathanw r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 534 1.16.2.2 nathanw r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 535 1.16.2.2 nathanw hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 536 1.16.2.2 nathanw } else { 537 1.16.2.2 nathanw /* READY-pin LOW to HIGH changes generates interrupt */ 538 1.16.2.2 nathanw r |= HD64461_PCC1CSCIER_P1RE; 539 1.16.2.2 nathanw hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 540 1.16.2.2 nathanw } 541 1.16.2.2 nathanw hd64461_reg_write_1(cscier, r); 542 1.16.2.2 nathanw 543 1.16.2.2 nathanw splx(s); 544 1.16.2.2 nathanw 545 1.16.2.2 nathanw return (void *)ih_func; 546 1.16.2.2 nathanw } 547 1.16.2.2 nathanw 548 1.16.2.2 nathanw void 549 1.16.2.2 nathanw hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 550 1.16.2.2 nathanw { 551 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 552 1.16.2.2 nathanw int channel = ch->ch_channel; 553 1.16.2.2 nathanw bus_addr_t cscier = HD64461_PCCCSCIER(channel); 554 1.16.2.2 nathanw int s = splhigh(); 555 1.16.2.2 nathanw u_int8_t r; 556 1.16.2.2 nathanw 557 1.16.2.2 nathanw /* disable card interrupt */ 558 1.16.2.2 nathanw r = hd64461_reg_read_1(cscier); 559 1.16.2.2 nathanw if (channel == CHANNEL_0) { 560 1.16.2.2 nathanw r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 561 1.16.2.2 nathanw r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 562 1.16.2.2 nathanw hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 563 1.16.2.2 nathanw } else { 564 1.16.2.2 nathanw r &= ~HD64461_PCC1CSCIER_P1RE; 565 1.16.2.2 nathanw hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 566 1.16.2.2 nathanw } 567 1.16.2.2 nathanw hd64461_reg_write_1(cscier, r); 568 1.16.2.2 nathanw 569 1.16.2.2 nathanw ch->ch_ih_card_func = 0; 570 1.16.2.2 nathanw 571 1.16.2.2 nathanw splx(s); 572 1.16.2.2 nathanw } 573 1.16.2.2 nathanw 574 1.16.2.2 nathanw int 575 1.16.2.2 nathanw hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 576 1.16.2.2 nathanw struct pcmcia_mem_handle *pcmhp) 577 1.16.2.2 nathanw { 578 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 579 1.16.2.2 nathanw 580 1.16.2.2 nathanw pcmhp->memt = ch->ch_memt; 581 1.16.2.2 nathanw pcmhp->addr = ch->ch_membase_addr; 582 1.16.2.2 nathanw pcmhp->memh = ch->ch_memh; 583 1.16.2.2 nathanw pcmhp->size = size; 584 1.16.2.2 nathanw pcmhp->realsize = size; 585 1.16.2.2 nathanw 586 1.16.2.2 nathanw DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 587 1.16.2.2 nathanw 588 1.16.2.2 nathanw return (0); 589 1.16.2.2 nathanw } 590 1.16.2.2 nathanw 591 1.16.2.2 nathanw void 592 1.16.2.2 nathanw hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 593 1.16.2.2 nathanw struct pcmcia_mem_handle *pcmhp) 594 1.16.2.2 nathanw { 595 1.16.2.2 nathanw /* nothing to do */ 596 1.16.2.2 nathanw } 597 1.16.2.2 nathanw 598 1.16.2.2 nathanw int 599 1.16.2.2 nathanw hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 600 1.16.2.2 nathanw bus_addr_t card_addr, 601 1.16.2.2 nathanw bus_size_t size, struct pcmcia_mem_handle *pcmhp, 602 1.16.2.2 nathanw bus_size_t *offsetp, int *windowp) 603 1.16.2.2 nathanw { 604 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 605 1.16.2.2 nathanw struct hd64461pcmcia_window_cookie *cookie; 606 1.16.2.2 nathanw bus_addr_t ofs; 607 1.16.2.2 nathanw 608 1.16.2.2 nathanw cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 609 1.16.2.2 nathanw M_DEVBUF, M_NOWAIT); 610 1.16.2.2 nathanw KASSERT(cookie); 611 1.16.2.2 nathanw memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 612 1.16.2.2 nathanw 613 1.16.2.2 nathanw /* Address */ 614 1.16.2.2 nathanw if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 615 1.16.2.2 nathanw cookie->wc_tag = ch->ch_memt; 616 1.16.2.2 nathanw if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 617 1.16.2.2 nathanw size, &cookie->wc_handle) != 0) 618 1.16.2.2 nathanw goto bad; 619 1.16.2.2 nathanw 620 1.16.2.2 nathanw *offsetp = card_addr; 621 1.16.2.2 nathanw cookie->wc_window = -1; 622 1.16.2.2 nathanw } else { 623 1.16.2.2 nathanw int window = card_addr / ch->ch_memsize; 624 1.16.2.2 nathanw KASSERT(window < MEMWIN_16M_MAX); 625 1.16.2.2 nathanw 626 1.16.2.2 nathanw cookie->wc_tag = ch->ch_cmemt[window]; 627 1.16.2.2 nathanw ofs = card_addr - window * ch->ch_memsize; 628 1.16.2.2 nathanw if (bus_space_map(cookie->wc_tag, ofs, size, 0, 629 1.16.2.2 nathanw &cookie->wc_handle) != 0) 630 1.16.2.2 nathanw goto bad; 631 1.16.2.2 nathanw 632 1.16.2.2 nathanw /* XXX bogus. check window per common memory access. */ 633 1.16.2.2 nathanw hd64461pcmcia_memory_window_16(ch->ch_channel, window); 634 1.16.2.2 nathanw *offsetp = ofs + 0x01000000; /* skip attribute area */ 635 1.16.2.2 nathanw cookie->wc_window = window; 636 1.16.2.2 nathanw } 637 1.16.2.2 nathanw cookie->wc_size = size; 638 1.16.2.2 nathanw *windowp = (int)cookie; 639 1.16.2.2 nathanw 640 1.16.2.2 nathanw DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 641 1.16.2.2 nathanw "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 642 1.16.2.2 nathanw size); 643 1.16.2.2 nathanw 644 1.16.2.2 nathanw return (0); 645 1.16.2.2 nathanw bad: 646 1.16.2.2 nathanw DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 647 1.16.2.2 nathanw free(cookie, M_DEVBUF); 648 1.16.2.2 nathanw 649 1.16.2.2 nathanw return (1); 650 1.16.2.2 nathanw } 651 1.16.2.2 nathanw 652 1.16.2.2 nathanw void 653 1.16.2.2 nathanw hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 654 1.16.2.2 nathanw { 655 1.16.2.2 nathanw struct hd64461pcmcia_window_cookie *cookie = (void *)window; 656 1.16.2.2 nathanw 657 1.16.2.2 nathanw if (cookie->wc_window != -1) 658 1.16.2.2 nathanw bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 659 1.16.2.2 nathanw cookie->wc_size); 660 1.16.2.2 nathanw DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 661 1.16.2.2 nathanw free(cookie, M_DEVBUF); 662 1.16.2.2 nathanw } 663 1.16.2.2 nathanw 664 1.16.2.2 nathanw int 665 1.16.2.2 nathanw hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 666 1.16.2.2 nathanw bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 667 1.16.2.2 nathanw { 668 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 669 1.16.2.2 nathanw 670 1.16.2.2 nathanw if (ch->ch_channel == CHANNEL_1) 671 1.16.2.2 nathanw return (1); 672 1.16.2.2 nathanw 673 1.16.2.2 nathanw if (start) { 674 1.16.2.2 nathanw if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 675 1.16.2.2 nathanw DPRINTF("couldn't map %#lx+%#lx\n", start, size); 676 1.16.2.2 nathanw return (1); 677 1.16.2.2 nathanw } 678 1.16.2.2 nathanw DPRINTF("map %#lx+%#lx\n", start, size); 679 1.16.2.2 nathanw } else { 680 1.16.2.2 nathanw if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 681 1.16.2.2 nathanw ch->ch_iobase + ch->ch_iosize - 1, 682 1.16.2.2 nathanw size, align, 0, 0, &pcihp->addr, 683 1.16.2.2 nathanw &pcihp->ioh)) { 684 1.16.2.2 nathanw DPRINTF("couldn't allocate %#lx\n", size); 685 1.16.2.2 nathanw return (1); 686 1.16.2.2 nathanw } 687 1.16.2.2 nathanw pcihp->flags = PCMCIA_IO_ALLOCATED; 688 1.16.2.2 nathanw DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 689 1.16.2.2 nathanw } 690 1.16.2.2 nathanw 691 1.16.2.2 nathanw pcihp->iot = ch->ch_iot; 692 1.16.2.2 nathanw pcihp->size = size; 693 1.16.2.2 nathanw 694 1.16.2.2 nathanw return (0); 695 1.16.2.2 nathanw } 696 1.16.2.2 nathanw 697 1.16.2.2 nathanw int 698 1.16.2.2 nathanw hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 699 1.16.2.2 nathanw bus_addr_t offset, 700 1.16.2.2 nathanw bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 701 1.16.2.2 nathanw { 702 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 703 1.16.2.2 nathanw #ifdef HD64461PCMCIA_DEBUG 704 1.16.2.2 nathanw static char *width_names[] = { "auto", "io8", "io16" }; 705 1.16.2.2 nathanw #endif 706 1.16.2.2 nathanw if (ch->ch_channel == CHANNEL_1) 707 1.16.2.2 nathanw return (1); 708 1.16.2.2 nathanw 709 1.16.2.2 nathanw hd64461_set_bus_width(CHANNEL_0, width); 710 1.16.2.2 nathanw 711 1.16.2.2 nathanw DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 712 1.16.2.2 nathanw width_names[width]); 713 1.16.2.2 nathanw 714 1.16.2.2 nathanw return (0); 715 1.16.2.2 nathanw } 716 1.16.2.2 nathanw 717 1.16.2.2 nathanw void 718 1.16.2.2 nathanw hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 719 1.16.2.2 nathanw struct pcmcia_io_handle *pcihp) 720 1.16.2.2 nathanw { 721 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 722 1.16.2.2 nathanw 723 1.16.2.2 nathanw if (ch->ch_channel == CHANNEL_1) 724 1.16.2.2 nathanw return; 725 1.16.2.2 nathanw 726 1.16.2.2 nathanw if (pcihp->flags & PCMCIA_IO_ALLOCATED) 727 1.16.2.2 nathanw bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 728 1.16.2.2 nathanw else 729 1.16.2.2 nathanw bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 730 1.16.2.2 nathanw 731 1.16.2.2 nathanw DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 732 1.16.2.2 nathanw } 733 1.16.2.2 nathanw 734 1.16.2.2 nathanw void 735 1.16.2.2 nathanw hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 736 1.16.2.2 nathanw { 737 1.16.2.2 nathanw /* nothing to do */ 738 1.16.2.2 nathanw } 739 1.16.2.2 nathanw 740 1.16.2.2 nathanw void 741 1.16.2.2 nathanw hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 742 1.16.2.2 nathanw { 743 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 744 1.16.2.2 nathanw int channel = ch->ch_channel; 745 1.16.2.2 nathanw bus_addr_t isr, gcr; 746 1.16.2.2 nathanw u_int8_t r; 747 1.16.2.2 nathanw int cardtype; 748 1.16.2.2 nathanw 749 1.16.2.2 nathanw DPRINTF("enable channel %d\n", channel); 750 1.16.2.2 nathanw isr = HD64461_PCCISR(channel); 751 1.16.2.2 nathanw gcr = HD64461_PCCGCR(channel); 752 1.16.2.2 nathanw 753 1.16.2.2 nathanw hd64461pcmcia_power_off(channel); 754 1.16.2.2 nathanw hd64461pcmcia_power_on(channel); 755 1.16.2.2 nathanw #if notyet 756 1.16.2.2 nathanw { 757 1.16.2.2 nathanw int i; 758 1.16.2.2 nathanw /* assert reset */ 759 1.16.2.2 nathanw r = hd64461_reg_read_1(gcr); 760 1.16.2.2 nathanw r |= HD64461_PCCGCR_PCCR; 761 1.16.2.2 nathanw hd64461_reg_write_1(gcr, r); 762 1.16.2.2 nathanw 763 1.16.2.2 nathanw /* 764 1.16.2.2 nathanw * hold RESET at least 10us. 765 1.16.2.2 nathanw */ 766 1.16.2.2 nathanw DELAY_MS(20); 767 1.16.2.2 nathanw 768 1.16.2.2 nathanw /* clear the reset flag */ 769 1.16.2.2 nathanw r &= ~HD64461_PCCGCR_PCCR; 770 1.16.2.2 nathanw hd64461_reg_write_1(gcr, r); 771 1.16.2.2 nathanw DELAY_MS(2000); 772 1.16.2.2 nathanw 773 1.16.2.2 nathanw /* wait for the chip to finish initializing */ 774 1.16.2.2 nathanw for (i = 0; i < 10000; i++) { 775 1.16.2.2 nathanw if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 776 1.16.2.2 nathanw goto reset_ok; 777 1.16.2.2 nathanw DELAY_MS(500); 778 1.16.2.2 nathanw 779 1.16.2.2 nathanw if ((i > 5000) && (i % 100 == 99)) 780 1.16.2.2 nathanw printf("."); 781 1.16.2.2 nathanw } 782 1.16.2.2 nathanw printf("reset failed.\n"); 783 1.16.2.2 nathanw hd64461pcmcia_power_off(channel); 784 1.16.2.2 nathanw return; 785 1.16.2.2 nathanw reset_ok: 786 1.16.2.2 nathanw } 787 1.16.2.2 nathanw #endif /* notyet */ 788 1.16.2.2 nathanw /* set Continuous 16-MB Area Mode */ 789 1.16.2.2 nathanw ch->ch_memory_window_mode = MEMWIN_16M_MODE; 790 1.16.2.2 nathanw hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 791 1.16.2.2 nathanw 792 1.16.2.2 nathanw /* 793 1.16.2.2 nathanw * set Common memory area. 794 1.16.2.2 nathanw */ 795 1.16.2.2 nathanw hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 796 1.16.2.2 nathanw 797 1.16.2.2 nathanw /* set the card type */ 798 1.16.2.2 nathanw r = hd64461_reg_read_1(gcr); 799 1.16.2.2 nathanw if (channel == CHANNEL_0) { 800 1.16.2.2 nathanw cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 801 1.16.2.2 nathanw if (cardtype == PCMCIA_IFTYPE_IO) 802 1.16.2.2 nathanw r |= HD64461_PCC0GCR_P0PCCT; 803 1.16.2.2 nathanw else 804 1.16.2.2 nathanw r &= ~HD64461_PCC0GCR_P0PCCT; 805 1.16.2.2 nathanw } else { 806 1.16.2.2 nathanw /* reserved bit must be 0 */ 807 1.16.2.2 nathanw r &= ~HD64461_PCC1GCR_RESERVED; 808 1.16.2.2 nathanw } 809 1.16.2.2 nathanw hd64461_reg_write_1(gcr, r); 810 1.16.2.2 nathanw 811 1.16.2.2 nathanw DPRINTF("OK.\n"); 812 1.16.2.2 nathanw } 813 1.16.2.2 nathanw 814 1.16.2.2 nathanw void 815 1.16.2.2 nathanw hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 816 1.16.2.2 nathanw { 817 1.16.2.2 nathanw struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 818 1.16.2.2 nathanw int channel = ch->ch_channel; 819 1.16.2.2 nathanw 820 1.16.2.2 nathanw /* dont' disable CSC interrupt */ 821 1.16.2.2 nathanw hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 822 1.16.2.2 nathanw hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 823 1.16.2.2 nathanw 824 1.16.2.2 nathanw /* power down the socket */ 825 1.16.2.2 nathanw hd64461pcmcia_power_off(channel); 826 1.16.2.2 nathanw } 827 1.16.2.2 nathanw 828 1.16.2.2 nathanw /* 829 1.16.2.2 nathanw * Card detect 830 1.16.2.2 nathanw */ 831 1.16.2.2 nathanw void 832 1.16.2.2 nathanw hd64461pcmcia_power_off(enum controller_channel channel) 833 1.16.2.2 nathanw { 834 1.16.2.2 nathanw #if notyet 835 1.16.2.2 nathanw u_int8_t r; 836 1.16.2.2 nathanw u_int16_t r16; 837 1.16.2.2 nathanw bus_addr_t scr, gcr; 838 1.16.2.2 nathanw 839 1.16.2.2 nathanw gcr = HD64461_PCCGCR(channel); 840 1.16.2.2 nathanw scr = HD64461_PCCSCR(channel); 841 1.16.2.2 nathanw 842 1.16.2.2 nathanw /* DRV (external buffer) high level */ 843 1.16.2.2 nathanw r = hd64461_reg_read_1(gcr); 844 1.16.2.2 nathanw r &= ~HD64461_PCCGCR_DRVE; 845 1.16.2.2 nathanw hd64461_reg_write_1(gcr, r); 846 1.16.2.2 nathanw 847 1.16.2.2 nathanw /* stop power */ 848 1.16.2.2 nathanw r = hd64461_reg_read_1(scr); 849 1.16.2.2 nathanw r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 850 1.16.2.2 nathanw hd64461_reg_write_1(scr, r); 851 1.16.2.2 nathanw r = hd64461_reg_read_1(gcr); 852 1.16.2.2 nathanw r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 853 1.16.2.2 nathanw hd64461_reg_write_1(gcr, r); 854 1.16.2.2 nathanw /* 855 1.16.2.2 nathanw * wait 300ms until power fails (Tpf). Then, wait 100ms since 856 1.16.2.2 nathanw * we are changing Vcc (Toff). 857 1.16.2.2 nathanw */ 858 1.16.2.2 nathanw DELAY_MS(300 + 100); 859 1.16.2.2 nathanw 860 1.16.2.2 nathanw /* stop clock */ 861 1.16.2.2 nathanw r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 862 1.16.2.2 nathanw r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 863 1.16.2.2 nathanw HD64461_SYSSTBCR_SPC1ST); 864 1.16.2.2 nathanw hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 865 1.16.2.2 nathanw 866 1.16.2.2 nathanw if (channel == CHANNEL_0) { 867 1.16.2.2 nathanw /* GPIO Port A XXX Jornada690 specific? */ 868 1.16.2.2 nathanw r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 869 1.16.2.2 nathanw r16 |= 0xf; 870 1.16.2.2 nathanw hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 871 1.16.2.2 nathanw } 872 1.16.2.2 nathanw 873 1.16.2.2 nathanw #endif /* notyet */ 874 1.16.2.2 nathanw } 875 1.16.2.2 nathanw 876 1.16.2.2 nathanw void 877 1.16.2.2 nathanw hd64461pcmcia_power_on(enum controller_channel channel) 878 1.16.2.2 nathanw { 879 1.16.2.2 nathanw u_int8_t r; 880 1.16.2.2 nathanw u_int16_t r16; 881 1.16.2.2 nathanw bus_addr_t scr, gcr, isr; 882 1.16.2.2 nathanw 883 1.16.2.2 nathanw isr = HD64461_PCCISR(channel); 884 1.16.2.2 nathanw gcr = HD64461_PCCGCR(channel); 885 1.16.2.2 nathanw scr = HD64461_PCCSCR(channel); 886 1.16.2.2 nathanw 887 1.16.2.2 nathanw /* 888 1.16.2.2 nathanw * XXX to access attribute memory, this is required. 889 1.16.2.2 nathanw */ 890 1.16.2.2 nathanw if (channel == CHANNEL_0) { 891 1.16.2.2 nathanw /* GPIO Port A XXX Jonanada690 specific? */ 892 1.16.2.2 nathanw r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 893 1.16.2.2 nathanw r16 &= ~0xf; 894 1.16.2.2 nathanw r16 |= 0x5; 895 1.16.2.2 nathanw hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 896 1.16.2.2 nathanw } 897 1.16.2.2 nathanw 898 1.16.2.2 nathanw if (channel == CHANNEL_1) { 899 1.16.2.2 nathanw /* GPIO Port C, Port D XXX HP620LX specific? */ 900 1.16.2.2 nathanw hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 901 1.16.2.2 nathanw hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 902 1.16.2.2 nathanw } 903 1.16.2.2 nathanw 904 1.16.2.2 nathanw /* supply clock */ 905 1.16.2.2 nathanw r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 906 1.16.2.2 nathanw r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 907 1.16.2.2 nathanw HD64461_SYSSTBCR_SPC1ST); 908 1.16.2.2 nathanw hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 909 1.16.2.2 nathanw DELAY_MS(200); 910 1.16.2.2 nathanw 911 1.16.2.2 nathanw /* detect voltage and supply VCC */ 912 1.16.2.2 nathanw r = hd64461_reg_read_1(isr); 913 1.16.2.2 nathanw 914 1.16.2.2 nathanw switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 915 1.16.2.2 nathanw case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 916 1.16.2.2 nathanw DPRINTF("5V card\n"); 917 1.16.2.2 nathanw hd64461pcmcia_power(channel, V_5, 1); 918 1.16.2.2 nathanw break; 919 1.16.2.2 nathanw case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 920 1.16.2.2 nathanw /* FALLTHROUGH */ 921 1.16.2.2 nathanw case 0: /* x.x / 3.3 / 5 V */ 922 1.16.2.2 nathanw DPRINTF("3.3V card\n"); 923 1.16.2.2 nathanw hd64461pcmcia_power(channel, V_3_3, 1); 924 1.16.2.2 nathanw break; 925 1.16.2.2 nathanw case HD64461_PCCISR_VS1: /* x.x V */ 926 1.16.2.2 nathanw /* FALLTHROUGH */ 927 1.16.2.2 nathanw DPRINTF("x.x V card\n"); 928 1.16.2.2 nathanw hd64461pcmcia_power(channel, V_X_X, 1); 929 1.16.2.2 nathanw return; 930 1.16.2.2 nathanw default: 931 1.16.2.2 nathanw printf("\nunknown Voltage. don't attach.\n"); 932 1.16.2.2 nathanw return; 933 1.16.2.2 nathanw } 934 1.16.2.2 nathanw 935 1.16.2.2 nathanw /* 936 1.16.2.2 nathanw * wait 100ms until power raise (Tpr) and 20ms to become 937 1.16.2.2 nathanw * stable (Tsu(Vcc)). 938 1.16.2.2 nathanw * 939 1.16.2.2 nathanw * some machines require some more time to be settled 940 1.16.2.2 nathanw * (300ms is added here). 941 1.16.2.2 nathanw */ 942 1.16.2.2 nathanw DELAY_MS(100 + 20 + 300); 943 1.16.2.2 nathanw 944 1.16.2.2 nathanw /* DRV (external buffer) low level */ 945 1.16.2.2 nathanw r = hd64461_reg_read_1(gcr); 946 1.16.2.2 nathanw r |= HD64461_PCCGCR_DRVE; 947 1.16.2.2 nathanw hd64461_reg_write_1(gcr, r); 948 1.16.2.2 nathanw 949 1.16.2.2 nathanw /* clear interrupt */ 950 1.16.2.2 nathanw hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 951 1.16.2.2 nathanw HD64461_PCC1CSCR_REG8, 0); 952 1.16.2.2 nathanw } 953 1.16.2.2 nathanw 954 1.16.2.2 nathanw enum hd64461pcmcia_event_type 955 1.16.2.2 nathanw detect_card(enum controller_channel channel) 956 1.16.2.2 nathanw { 957 1.16.2.2 nathanw u_int8_t r; 958 1.16.2.2 nathanw 959 1.16.2.2 nathanw r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 960 1.16.2.2 nathanw (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 961 1.16.2.2 nathanw 962 1.16.2.2 nathanw if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 963 1.16.2.2 nathanw DPRINTF("remove\n"); 964 1.16.2.2 nathanw return EVENT_REMOVE; 965 1.16.2.2 nathanw } 966 1.16.2.2 nathanw if (r == 0) { 967 1.16.2.2 nathanw DPRINTF("insert\n"); 968 1.16.2.2 nathanw return EVENT_INSERT; 969 1.16.2.2 nathanw } 970 1.16.2.2 nathanw DPRINTF("transition\n"); 971 1.16.2.2 nathanw 972 1.16.2.2 nathanw return EVENT_NONE; 973 1.16.2.2 nathanw } 974 1.16.2.2 nathanw 975 1.16.2.2 nathanw /* 976 1.16.2.2 nathanw * Memory window access ops. 977 1.16.2.2 nathanw */ 978 1.16.2.2 nathanw void 979 1.16.2.2 nathanw hd64461pcmcia_memory_window_mode(enum controller_channel channel, 980 1.16.2.2 nathanw enum memory_window_mode mode) 981 1.16.2.2 nathanw { 982 1.16.2.2 nathanw bus_addr_t a = HD64461_PCCGCR(channel); 983 1.16.2.2 nathanw u_int8_t r = hd64461_reg_read_1(a); 984 1.16.2.2 nathanw 985 1.16.2.2 nathanw r &= ~HD64461_PCCGCR_MMOD; 986 1.16.2.2 nathanw r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 987 1.16.2.2 nathanw HD64461_PCCGCR_MMOD_32M; 988 1.16.2.2 nathanw hd64461_reg_write_1(a, r); 989 1.16.2.2 nathanw } 990 1.16.2.2 nathanw 991 1.16.2.2 nathanw void 992 1.16.2.2 nathanw hd64461pcmcia_memory_window_16(enum controller_channel channel, 993 1.16.2.2 nathanw enum memory_window_16 window) 994 1.16.2.2 nathanw { 995 1.16.2.2 nathanw bus_addr_t a = HD64461_PCCGCR(channel); 996 1.16.2.2 nathanw u_int8_t r; 997 1.16.2.2 nathanw 998 1.16.2.2 nathanw r = hd64461_reg_read_1(a); 999 1.16.2.2 nathanw r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1000 1.16.2.2 nathanw 1001 1.16.2.2 nathanw switch (window) { 1002 1.16.2.2 nathanw case MEMWIN_16M_COMMON_0: 1003 1.16.2.2 nathanw break; 1004 1.16.2.2 nathanw case MEMWIN_16M_COMMON_1: 1005 1.16.2.2 nathanw r |= HD64461_PCCGCR_PA24; 1006 1.16.2.2 nathanw break; 1007 1.16.2.2 nathanw case MEMWIN_16M_COMMON_2: 1008 1.16.2.2 nathanw r |= HD64461_PCCGCR_PA25; 1009 1.16.2.2 nathanw break; 1010 1.16.2.2 nathanw case MEMWIN_16M_COMMON_3: 1011 1.16.2.2 nathanw r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1012 1.16.2.2 nathanw break; 1013 1.16.2.2 nathanw } 1014 1.16.2.2 nathanw 1015 1.16.2.2 nathanw hd64461_reg_write_1(a, r); 1016 1.16.2.2 nathanw } 1017 1.16.2.2 nathanw 1018 1.16.2.2 nathanw #if unused 1019 1.16.2.2 nathanw void 1020 1.16.2.2 nathanw memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1021 1.16.2.2 nathanw { 1022 1.16.2.2 nathanw bus_addr_t a = HD64461_PCCGCR(channel); 1023 1.16.2.2 nathanw u_int8_t r; 1024 1.16.2.2 nathanw 1025 1.16.2.2 nathanw r = hd64461_reg_read_1(a); 1026 1.16.2.2 nathanw r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1027 1.16.2.2 nathanw 1028 1.16.2.2 nathanw switch (window) { 1029 1.16.2.2 nathanw case MEMWIN_32M_ATTR: 1030 1.16.2.2 nathanw break; 1031 1.16.2.2 nathanw case MEMWIN_32M_COMMON_0: 1032 1.16.2.2 nathanw r |= HD64461_PCCGCR_PREG; 1033 1.16.2.2 nathanw break; 1034 1.16.2.2 nathanw case MEMWIN_32M_COMMON_1: 1035 1.16.2.2 nathanw r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1036 1.16.2.2 nathanw break; 1037 1.16.2.2 nathanw } 1038 1.16.2.2 nathanw 1039 1.16.2.2 nathanw hd64461_reg_write_1(a, r); 1040 1.16.2.2 nathanw } 1041 1.16.2.2 nathanw #endif 1042 1.16.2.2 nathanw 1043 1.16.2.2 nathanw void 1044 1.16.2.2 nathanw hd64461_set_bus_width(enum controller_channel channel, int width) 1045 1.16.2.2 nathanw { 1046 1.16.2.2 nathanw u_int16_t r16; 1047 1.16.2.2 nathanw 1048 1.16.2.2 nathanw r16 = _reg_read_2(SH3_BCR2); 1049 1.16.2.2 nathanw if (channel == CHANNEL_0) { 1050 1.16.2.2 nathanw r16 &= ~((1 << 13)|(1 << 12)); 1051 1.16.2.2 nathanw r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1052 1.16.2.2 nathanw } else { 1053 1.16.2.2 nathanw r16 &= ~((1 << 11)|(1 << 10)); 1054 1.16.2.2 nathanw r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1055 1.16.2.2 nathanw } 1056 1.16.2.2 nathanw _reg_write_2(SH3_BCR2, r16); 1057 1.16.2.2 nathanw } 1058 1.16.2.2 nathanw 1059 1.16.2.2 nathanw void 1060 1.16.2.2 nathanw fixup_sh3_pcmcia_area(bus_space_tag_t t) 1061 1.16.2.2 nathanw { 1062 1.16.2.2 nathanw struct hpcsh_bus_space *hbs = (void *)t; 1063 1.16.2.2 nathanw 1064 1.16.2.2 nathanw hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1065 1.16.2.2 nathanw hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1066 1.16.2.2 nathanw hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1067 1.16.2.2 nathanw hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1068 1.16.2.2 nathanw } 1069 1.16.2.2 nathanw 1070 1.16.2.2 nathanw #ifdef HD64461PCMCIA_DEBUG 1071 1.16.2.2 nathanw void 1072 1.16.2.2 nathanw hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1073 1.16.2.2 nathanw { 1074 1.16.2.2 nathanw u_int8_t r8; 1075 1.16.2.2 nathanw 1076 1.16.2.2 nathanw dbg_banner_function(); 1077 1.16.2.2 nathanw /* 1078 1.16.2.2 nathanw * PCC0 1079 1.16.2.2 nathanw */ 1080 1.16.2.2 nathanw printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1081 1.16.2.2 nathanw printf("PCC0 Interface Status Register\n"); 1082 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1083 1.16.2.2 nathanw 1084 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1085 1.16.2.2 nathanw _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1086 1.16.2.2 nathanw _(P0BVD2);_(P0BVD1); 1087 1.16.2.2 nathanw #undef _ 1088 1.16.2.2 nathanw printf("\n"); 1089 1.16.2.2 nathanw 1090 1.16.2.2 nathanw printf("PCC0 General Control Register\n"); 1091 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1092 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1093 1.16.2.2 nathanw _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1094 1.16.2.2 nathanw _(P0PA25);_(P0PA24);_(P0REG); 1095 1.16.2.2 nathanw #undef _ 1096 1.16.2.2 nathanw printf("\n"); 1097 1.16.2.2 nathanw 1098 1.16.2.2 nathanw printf("PCC0 Card Status Change Register\n"); 1099 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1100 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1101 1.16.2.2 nathanw _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1102 1.16.2.2 nathanw #undef _ 1103 1.16.2.2 nathanw printf("\n"); 1104 1.16.2.2 nathanw 1105 1.16.2.2 nathanw printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1106 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1107 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1108 1.16.2.2 nathanw _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1109 1.16.2.2 nathanw #undef _ 1110 1.16.2.2 nathanw printf("\ninterrupt type: "); 1111 1.16.2.2 nathanw switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1112 1.16.2.2 nathanw case HD64461_PCC0CSCIER_P0IREQE_NONE: 1113 1.16.2.2 nathanw printf("none\n"); 1114 1.16.2.2 nathanw break; 1115 1.16.2.2 nathanw case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1116 1.16.2.2 nathanw printf("level\n"); 1117 1.16.2.2 nathanw break; 1118 1.16.2.2 nathanw case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1119 1.16.2.2 nathanw printf("falling edge\n"); 1120 1.16.2.2 nathanw break; 1121 1.16.2.2 nathanw case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1122 1.16.2.2 nathanw printf("rising edge\n"); 1123 1.16.2.2 nathanw break; 1124 1.16.2.2 nathanw } 1125 1.16.2.2 nathanw 1126 1.16.2.2 nathanw printf("PCC0 Software Control Register\n"); 1127 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1128 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1129 1.16.2.2 nathanw _(P0VCC1);_(P0SWP); 1130 1.16.2.2 nathanw #undef _ 1131 1.16.2.2 nathanw printf("\n"); 1132 1.16.2.2 nathanw 1133 1.16.2.2 nathanw /* 1134 1.16.2.2 nathanw * PCC1 1135 1.16.2.2 nathanw */ 1136 1.16.2.2 nathanw printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1137 1.16.2.2 nathanw printf("PCC1 Interface Status Register\n"); 1138 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1139 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1140 1.16.2.2 nathanw _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1141 1.16.2.2 nathanw _(P1BVD2);_(P1BVD1); 1142 1.16.2.2 nathanw #undef _ 1143 1.16.2.2 nathanw printf("\n"); 1144 1.16.2.2 nathanw 1145 1.16.2.2 nathanw printf("PCC1 General Contorol Register\n"); 1146 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1147 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1148 1.16.2.2 nathanw _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1149 1.16.2.2 nathanw #undef _ 1150 1.16.2.2 nathanw printf("\n"); 1151 1.16.2.2 nathanw 1152 1.16.2.2 nathanw printf("PCC1 Card Status Change Register\n"); 1153 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1154 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1155 1.16.2.2 nathanw _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1156 1.16.2.2 nathanw #undef _ 1157 1.16.2.2 nathanw printf("\n"); 1158 1.16.2.2 nathanw 1159 1.16.2.2 nathanw printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1160 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1161 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1162 1.16.2.2 nathanw _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1163 1.16.2.2 nathanw #undef _ 1164 1.16.2.2 nathanw printf("\n"); 1165 1.16.2.2 nathanw 1166 1.16.2.2 nathanw printf("PCC1 Software Control Register\n"); 1167 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1168 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1169 1.16.2.2 nathanw _(P1VCC1);_(P1SWP); 1170 1.16.2.2 nathanw #undef _ 1171 1.16.2.2 nathanw printf("\n"); 1172 1.16.2.2 nathanw 1173 1.16.2.2 nathanw /* 1174 1.16.2.2 nathanw * General Control 1175 1.16.2.2 nathanw */ 1176 1.16.2.2 nathanw printf("[General Control]\n"); 1177 1.16.2.2 nathanw printf("PCC0 Output pins Control Register\n"); 1178 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1179 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1180 1.16.2.2 nathanw _(P0DEPLUP);_(P0AEPLUP); 1181 1.16.2.2 nathanw #undef _ 1182 1.16.2.2 nathanw printf("\n"); 1183 1.16.2.2 nathanw 1184 1.16.2.2 nathanw printf("PCC1 Output pins Control Register\n"); 1185 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1186 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1187 1.16.2.2 nathanw _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1188 1.16.2.2 nathanw #undef _ 1189 1.16.2.2 nathanw printf("\n"); 1190 1.16.2.2 nathanw 1191 1.16.2.2 nathanw printf("PC Card General Control Register\n"); 1192 1.16.2.2 nathanw r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1193 1.16.2.2 nathanw #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1194 1.16.2.2 nathanw _(PSSDIR);_(PSSRDWR); 1195 1.16.2.2 nathanw #undef _ 1196 1.16.2.2 nathanw printf("\n"); 1197 1.16.2.2 nathanw 1198 1.16.2.2 nathanw dbg_banner_line(); 1199 1.16.2.2 nathanw } 1200 1.16.2.2 nathanw #endif /* HD64461PCMCIA_DEBUG */ 1201
Indexes created Mon Oct 20 20:10:13 GMT 2025