hd64461pcmcia.c revision 1.2.2.2
1 1.2.2.2 bouyer /* $NetBSD: hd64461pcmcia.c,v 1.2.2.2 2001/03/12 13:28:52 bouyer Exp $ */ 2 1.2.2.2 bouyer 3 1.2.2.2 bouyer /*- 4 1.2.2.2 bouyer * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.2.2.2 bouyer * All rights reserved. 6 1.2.2.2 bouyer * 7 1.2.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 bouyer * by UCHIYAMA Yasushi. 9 1.2.2.2 bouyer * 10 1.2.2.2 bouyer * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 bouyer * modification, are permitted provided that the following conditions 12 1.2.2.2 bouyer * are met: 13 1.2.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 bouyer * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 bouyer * documentation and/or other materials provided with the distribution. 18 1.2.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 19 1.2.2.2 bouyer * must display the following acknowledgement: 20 1.2.2.2 bouyer * This product includes software developed by the NetBSD 21 1.2.2.2 bouyer * Foundation, Inc. and its contributors. 22 1.2.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2.2.2 bouyer * contributors may be used to endorse or promote products derived 24 1.2.2.2 bouyer * from this software without specific prior written permission. 25 1.2.2.2 bouyer * 26 1.2.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 37 1.2.2.2 bouyer */ 38 1.2.2.2 bouyer #define HD64461PCMCIA_DEBUG 39 1.2.2.2 bouyer 40 1.2.2.2 bouyer #include <sys/param.h> 41 1.2.2.2 bouyer #include <sys/systm.h> 42 1.2.2.2 bouyer #include <sys/device.h> 43 1.2.2.2 bouyer #include <sys/malloc.h> 44 1.2.2.2 bouyer #include <sys/kthread.h> 45 1.2.2.2 bouyer #include <sys/boot_flag.h> 46 1.2.2.2 bouyer 47 1.2.2.2 bouyer #include <machine/bus.h> 48 1.2.2.2 bouyer #include <machine/intr.h> 49 1.2.2.2 bouyer 50 1.2.2.2 bouyer #ifdef DEBUG 51 1.2.2.2 bouyer #include <hpcsh/hpcsh/debug.h> 52 1.2.2.2 bouyer #endif 53 1.2.2.2 bouyer 54 1.2.2.2 bouyer #include <dev/pcmcia/pcmciareg.h> 55 1.2.2.2 bouyer #include <dev/pcmcia/pcmciavar.h> 56 1.2.2.2 bouyer #include <dev/pcmcia/pcmciachip.h> 57 1.2.2.2 bouyer 58 1.2.2.2 bouyer #include <sh3/bscreg.h> 59 1.2.2.2 bouyer 60 1.2.2.2 bouyer #include <hpcsh/dev/hd64461/hd64461reg.h> 61 1.2.2.2 bouyer #include <hpcsh/dev/hd64461/hd64461var.h> 62 1.2.2.2 bouyer #include <hpcsh/dev/hd64461/hd64461intcvar.h> 63 1.2.2.2 bouyer #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 1.2.2.2 bouyer #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 1.2.2.2 bouyer 66 1.2.2.2 bouyer #include "locators.h" 67 1.2.2.2 bouyer 68 1.2.2.2 bouyer #ifdef HD64461PCMCIA_DEBUG 69 1.2.2.2 bouyer int hd64461pcmcia_debug = 1; 70 1.2.2.2 bouyer #define DPRINTF(fmt, args...) \ 71 1.2.2.2 bouyer if (hd64461pcmcia_debug) \ 72 1.2.2.2 bouyer printf("%s: " fmt, __FUNCTION__ , ##args) 73 1.2.2.2 bouyer #define DPRINTFN(n, arg) \ 74 1.2.2.2 bouyer if (hd64461pcmcia_debug > (n)) \ 75 1.2.2.2 bouyer printf("%s: " fmt, __FUNCTION__ , ##args) 76 1.2.2.2 bouyer #else 77 1.2.2.2 bouyer #define DPRINTF(arg...) ((void)0) 78 1.2.2.2 bouyer #define DPRINTFN(n, arg...) ((void)0) 79 1.2.2.2 bouyer #endif 80 1.2.2.2 bouyer 81 1.2.2.2 bouyer enum controller_channel { 82 1.2.2.2 bouyer CHANNEL_0 = 0, 83 1.2.2.2 bouyer CHANNEL_1 = 1, 84 1.2.2.2 bouyer CHANNEL_MAX = 2 85 1.2.2.2 bouyer }; 86 1.2.2.2 bouyer 87 1.2.2.2 bouyer enum memory_window_mode { 88 1.2.2.2 bouyer MEMWIN_16M_MODE, 89 1.2.2.2 bouyer MEMWIN_32M_MODE 90 1.2.2.2 bouyer }; 91 1.2.2.2 bouyer 92 1.2.2.2 bouyer enum memory_window_16 { 93 1.2.2.2 bouyer MEMWIN_16M_COMMON_0, 94 1.2.2.2 bouyer MEMWIN_16M_COMMON_1, 95 1.2.2.2 bouyer MEMWIN_16M_COMMON_2, 96 1.2.2.2 bouyer MEMWIN_16M_COMMON_3, 97 1.2.2.2 bouyer }; 98 1.2.2.2 bouyer #define MEMWIN_16M_MAX 4 99 1.2.2.2 bouyer 100 1.2.2.2 bouyer enum memory_window_32 { 101 1.2.2.2 bouyer MEMWIN_32M_ATTR, 102 1.2.2.2 bouyer MEMWIN_32M_COMMON_0, 103 1.2.2.2 bouyer MEMWIN_32M_COMMON_1, 104 1.2.2.2 bouyer }; 105 1.2.2.2 bouyer #define MEMWIN_32M_MAX 3 106 1.2.2.2 bouyer 107 1.2.2.2 bouyer enum hd64461pcmcia_event_type { 108 1.2.2.2 bouyer EVENT_NONE, 109 1.2.2.2 bouyer EVENT_INSERT, 110 1.2.2.2 bouyer EVENT_REMOVE, 111 1.2.2.2 bouyer }; 112 1.2.2.2 bouyer #define EVENT_QUEUE_MAX 5 113 1.2.2.2 bouyer 114 1.2.2.2 bouyer struct hd64461pcmcia_softc; /* forward declaration */ 115 1.2.2.2 bouyer 116 1.2.2.2 bouyer struct hd64461pcmcia_window_cookie { 117 1.2.2.2 bouyer bus_space_tag_t wc_tag; 118 1.2.2.2 bouyer bus_space_handle_t wc_handle; 119 1.2.2.2 bouyer int wc_size; 120 1.2.2.2 bouyer int wc_window; 121 1.2.2.2 bouyer }; 122 1.2.2.2 bouyer 123 1.2.2.2 bouyer struct hd64461pcmcia_channel { 124 1.2.2.2 bouyer struct hd64461pcmcia_softc *ch_parent; 125 1.2.2.2 bouyer struct device *ch_pcmcia; 126 1.2.2.2 bouyer enum controller_channel ch_channel; 127 1.2.2.2 bouyer 128 1.2.2.2 bouyer /* memory space */ 129 1.2.2.2 bouyer enum memory_window_mode ch_memory_window_mode; 130 1.2.2.2 bouyer bus_space_tag_t ch_memt; 131 1.2.2.2 bouyer bus_space_handle_t ch_memh; 132 1.2.2.2 bouyer bus_addr_t ch_membase_addr; 133 1.2.2.2 bouyer bus_size_t ch_memsize; 134 1.2.2.2 bouyer bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 135 1.2.2.2 bouyer 136 1.2.2.2 bouyer /* I/O space */ 137 1.2.2.2 bouyer bus_space_tag_t ch_iot; 138 1.2.2.2 bouyer bus_addr_t ch_iobase; 139 1.2.2.2 bouyer bus_size_t ch_iosize; 140 1.2.2.2 bouyer 141 1.2.2.2 bouyer /* card interrupt */ 142 1.2.2.2 bouyer int (*ch_ih_card_func)(void *); 143 1.2.2.2 bouyer void *ch_ih_card_arg; 144 1.2.2.2 bouyer int ch_attached; 145 1.2.2.2 bouyer }; 146 1.2.2.2 bouyer 147 1.2.2.2 bouyer struct hd64461pcmcia_event { 148 1.2.2.2 bouyer int __queued; 149 1.2.2.2 bouyer enum hd64461pcmcia_event_type pe_type; 150 1.2.2.2 bouyer struct hd64461pcmcia_channel *pe_ch; 151 1.2.2.2 bouyer SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 152 1.2.2.2 bouyer }; 153 1.2.2.2 bouyer 154 1.2.2.2 bouyer struct hd64461pcmcia_softc { 155 1.2.2.2 bouyer struct device sc_dev; 156 1.2.2.2 bouyer enum hd64461_module_id sc_module_id; 157 1.2.2.2 bouyer int sc_shutdown; 158 1.2.2.2 bouyer 159 1.2.2.2 bouyer /* CSC event */ 160 1.2.2.2 bouyer struct proc *sc_event_thread; 161 1.2.2.2 bouyer struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 162 1.2.2.2 bouyer SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 163 1.2.2.2 bouyer 164 1.2.2.2 bouyer struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 165 1.2.2.2 bouyer }; 166 1.2.2.2 bouyer 167 1.2.2.2 bouyer static int _chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 1.2.2.2 bouyer struct pcmcia_mem_handle *); 169 1.2.2.2 bouyer static void _chip_mem_free(pcmcia_chipset_handle_t, 170 1.2.2.2 bouyer struct pcmcia_mem_handle *); 171 1.2.2.2 bouyer static int _chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 1.2.2.2 bouyer bus_size_t, struct pcmcia_mem_handle *, 173 1.2.2.2 bouyer bus_addr_t *, int *); 174 1.2.2.2 bouyer static void _chip_mem_unmap(pcmcia_chipset_handle_t, int); 175 1.2.2.2 bouyer static int _chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 176 1.2.2.2 bouyer bus_size_t, bus_size_t, struct pcmcia_io_handle *); 177 1.2.2.2 bouyer static void _chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 178 1.2.2.2 bouyer static int _chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 1.2.2.2 bouyer bus_size_t, struct pcmcia_io_handle *, int *); 180 1.2.2.2 bouyer static void _chip_io_unmap(pcmcia_chipset_handle_t, int); 181 1.2.2.2 bouyer static void _chip_socket_enable(pcmcia_chipset_handle_t); 182 1.2.2.2 bouyer static void _chip_socket_disable(pcmcia_chipset_handle_t); 183 1.2.2.2 bouyer static void *_chip_intr_establish(pcmcia_chipset_handle_t, 184 1.2.2.2 bouyer struct pcmcia_function *, int, 185 1.2.2.2 bouyer int (*)(void *), void *); 186 1.2.2.2 bouyer static void _chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 187 1.2.2.2 bouyer 188 1.2.2.2 bouyer static struct pcmcia_chip_functions hd64461pcmcia_functions = { 189 1.2.2.2 bouyer _chip_mem_alloc, 190 1.2.2.2 bouyer _chip_mem_free, 191 1.2.2.2 bouyer _chip_mem_map, 192 1.2.2.2 bouyer _chip_mem_unmap, 193 1.2.2.2 bouyer _chip_io_alloc, 194 1.2.2.2 bouyer _chip_io_free, 195 1.2.2.2 bouyer _chip_io_map, 196 1.2.2.2 bouyer _chip_io_unmap, 197 1.2.2.2 bouyer _chip_intr_establish, 198 1.2.2.2 bouyer _chip_intr_disestablish, 199 1.2.2.2 bouyer _chip_socket_enable, 200 1.2.2.2 bouyer _chip_socket_disable, 201 1.2.2.2 bouyer }; 202 1.2.2.2 bouyer 203 1.2.2.2 bouyer static int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 204 1.2.2.2 bouyer static void hd64461pcmcia_attach(struct device *, struct device *, void *); 205 1.2.2.2 bouyer static int hd64461pcmcia_print(void *, const char *); 206 1.2.2.2 bouyer static int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 207 1.2.2.2 bouyer 208 1.2.2.2 bouyer struct cfattach hd64461pcmcia_ca = { 209 1.2.2.2 bouyer sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 210 1.2.2.2 bouyer hd64461pcmcia_attach 211 1.2.2.2 bouyer }; 212 1.2.2.2 bouyer 213 1.2.2.2 bouyer static void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 214 1.2.2.2 bouyer enum controller_channel); 215 1.2.2.2 bouyer /* hot plug */ 216 1.2.2.2 bouyer static void hd64461pcmcia_create_event_thread(void *); 217 1.2.2.2 bouyer static void hd64461pcmcia_event_thread(void *); 218 1.2.2.2 bouyer static void queue_event(struct hd64461pcmcia_channel *, 219 1.2.2.2 bouyer enum hd64461pcmcia_event_type); 220 1.2.2.2 bouyer /* interrupt handler */ 221 1.2.2.2 bouyer static int hd64461pcmcia_channel0_intr(void *); 222 1.2.2.2 bouyer static int hd64461pcmcia_channel1_intr(void *); 223 1.2.2.2 bouyer /* card status */ 224 1.2.2.2 bouyer static enum hd64461pcmcia_event_type detect_card(enum controller_channel); 225 1.2.2.2 bouyer static void power_off(enum controller_channel); 226 1.2.2.2 bouyer static void power_on(enum controller_channel); 227 1.2.2.2 bouyer /* memory window access ops */ 228 1.2.2.2 bouyer static void memory_window_mode(enum controller_channel, 229 1.2.2.2 bouyer enum memory_window_mode); 230 1.2.2.2 bouyer static void memory_window_16(enum controller_channel, enum memory_window_16); 231 1.2.2.2 bouyer /* bus width */ 232 1.2.2.2 bouyer static void set_bus_width(enum controller_channel, int); 233 1.2.2.2 bouyer #ifdef DEBUG 234 1.2.2.2 bouyer static void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 235 1.2.2.2 bouyer #endif 236 1.2.2.2 bouyer 237 1.2.2.2 bouyer #define DELAY_MS(x) delay((x) * 1000) 238 1.2.2.2 bouyer 239 1.2.2.2 bouyer static int 240 1.2.2.2 bouyer hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 241 1.2.2.2 bouyer { 242 1.2.2.2 bouyer struct hd64461_attach_args *ha = aux; 243 1.2.2.2 bouyer 244 1.2.2.2 bouyer return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 245 1.2.2.2 bouyer } 246 1.2.2.2 bouyer 247 1.2.2.2 bouyer static void 248 1.2.2.2 bouyer hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 249 1.2.2.2 bouyer { 250 1.2.2.2 bouyer struct hd64461_attach_args *ha = aux; 251 1.2.2.2 bouyer struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 252 1.2.2.2 bouyer 253 1.2.2.2 bouyer sc->sc_module_id = ha->ha_module_id; 254 1.2.2.2 bouyer 255 1.2.2.2 bouyer printf("\n"); 256 1.2.2.2 bouyer 257 1.2.2.2 bouyer #ifdef DEBUG 258 1.2.2.2 bouyer if (bootverbose) 259 1.2.2.2 bouyer hd64461pcmcia_info(sc); 260 1.2.2.2 bouyer #endif 261 1.2.2.2 bouyer /* Channel 0/1 common CSC event queue */ 262 1.2.2.2 bouyer SIMPLEQ_INIT (&sc->sc_event_head); 263 1.2.2.2 bouyer kthread_create(hd64461pcmcia_create_event_thread, sc); 264 1.2.2.2 bouyer 265 1.2.2.2 bouyer hd64461pcmcia_attach_channel(sc, CHANNEL_0); 266 1.2.2.2 bouyer hd64461pcmcia_attach_channel(sc, CHANNEL_1); 267 1.2.2.2 bouyer } 268 1.2.2.2 bouyer 269 1.2.2.2 bouyer static void 270 1.2.2.2 bouyer hd64461pcmcia_create_event_thread(void *arg) 271 1.2.2.2 bouyer { 272 1.2.2.2 bouyer struct hd64461pcmcia_softc *sc = arg; 273 1.2.2.2 bouyer int error; 274 1.2.2.2 bouyer 275 1.2.2.2 bouyer error = kthread_create1(hd64461pcmcia_event_thread, sc, 276 1.2.2.2 bouyer &sc->sc_event_thread, "%s", 277 1.2.2.2 bouyer sc->sc_dev.dv_xname); 278 1.2.2.2 bouyer KASSERT(error == 0); 279 1.2.2.2 bouyer } 280 1.2.2.2 bouyer 281 1.2.2.2 bouyer static void 282 1.2.2.2 bouyer hd64461pcmcia_event_thread(void *arg) 283 1.2.2.2 bouyer { 284 1.2.2.2 bouyer struct hd64461pcmcia_softc *sc = arg; 285 1.2.2.2 bouyer struct hd64461pcmcia_event *pe; 286 1.2.2.2 bouyer int s; 287 1.2.2.2 bouyer 288 1.2.2.2 bouyer while (!sc->sc_shutdown) { 289 1.2.2.2 bouyer tsleep(sc, PWAIT, "CSC wait", 0); 290 1.2.2.2 bouyer s = splhigh(); 291 1.2.2.2 bouyer while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 292 1.2.2.2 bouyer splx(s); 293 1.2.2.2 bouyer switch (pe->pe_type) { 294 1.2.2.2 bouyer default: 295 1.2.2.2 bouyer printf("%s: unknown event.\n", __FUNCTION__); 296 1.2.2.2 bouyer break; 297 1.2.2.2 bouyer case EVENT_INSERT: 298 1.2.2.2 bouyer DPRINTF("insert event.\n"); 299 1.2.2.2 bouyer pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 300 1.2.2.2 bouyer break; 301 1.2.2.2 bouyer case EVENT_REMOVE: 302 1.2.2.2 bouyer DPRINTF("remove event.\n"); 303 1.2.2.2 bouyer pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 304 1.2.2.2 bouyer DETACH_FORCE); 305 1.2.2.2 bouyer break; 306 1.2.2.2 bouyer } 307 1.2.2.2 bouyer s = splhigh(); 308 1.2.2.2 bouyer SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 309 1.2.2.2 bouyer pe->__queued = 0; 310 1.2.2.2 bouyer } 311 1.2.2.2 bouyer splx(s); 312 1.2.2.2 bouyer } 313 1.2.2.2 bouyer /* NOTREACHED */ 314 1.2.2.2 bouyer } 315 1.2.2.2 bouyer 316 1.2.2.2 bouyer static int 317 1.2.2.2 bouyer hd64461pcmcia_print(void *arg, const char *pnp) 318 1.2.2.2 bouyer { 319 1.2.2.2 bouyer if (pnp) 320 1.2.2.2 bouyer printf("pcmcia at %s", pnp); 321 1.2.2.2 bouyer 322 1.2.2.2 bouyer return (UNCONF); 323 1.2.2.2 bouyer } 324 1.2.2.2 bouyer 325 1.2.2.2 bouyer static int 326 1.2.2.2 bouyer hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 327 1.2.2.2 bouyer { 328 1.2.2.2 bouyer struct pcmciabus_attach_args *paa = aux; 329 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = 330 1.2.2.2 bouyer (struct hd64461pcmcia_channel *)paa->pch; 331 1.2.2.2 bouyer 332 1.2.2.2 bouyer if (ch->ch_channel == CHANNEL_0) { 333 1.2.2.2 bouyer if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 334 1.2.2.2 bouyer PCMCIABUSCF_CONTROLLER_DEFAULT && 335 1.2.2.2 bouyer cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 336 1.2.2.2 bouyer return 0; 337 1.2.2.2 bouyer } else { 338 1.2.2.2 bouyer if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 339 1.2.2.2 bouyer PCMCIABUSCF_CONTROLLER_DEFAULT && 340 1.2.2.2 bouyer cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 341 1.2.2.2 bouyer return 0; 342 1.2.2.2 bouyer } 343 1.2.2.2 bouyer paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 344 1.2.2.2 bouyer 345 1.2.2.2 bouyer return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 346 1.2.2.2 bouyer } 347 1.2.2.2 bouyer 348 1.2.2.2 bouyer static void 349 1.2.2.2 bouyer hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 350 1.2.2.2 bouyer enum controller_channel channel) 351 1.2.2.2 bouyer { 352 1.2.2.2 bouyer struct device *parent = (struct device *)sc; 353 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 354 1.2.2.2 bouyer struct pcmciabus_attach_args paa; 355 1.2.2.2 bouyer bus_addr_t membase; 356 1.2.2.2 bouyer int i; 357 1.2.2.2 bouyer 358 1.2.2.2 bouyer ch->ch_parent = sc; 359 1.2.2.2 bouyer ch->ch_channel = channel; 360 1.2.2.2 bouyer 361 1.2.2.2 bouyer /* 362 1.2.2.2 bouyer * Continuous 16-MB Area Mode 363 1.2.2.2 bouyer */ 364 1.2.2.2 bouyer /* Attibute/Common memory extent */ 365 1.2.2.2 bouyer membase = (channel == CHANNEL_0) 366 1.2.2.2 bouyer ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 367 1.2.2.2 bouyer ch->ch_memt = bus_space_create("PCMCIA attribute memory", 368 1.2.2.2 bouyer membase, 0x01000000); /* 16MB */ 369 1.2.2.2 bouyer bus_space_alloc(ch->ch_memt, 0, 0x01000000, 0x01000000, 370 1.2.2.2 bouyer 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 371 1.2.2.2 bouyer &ch->ch_memh); 372 1.2.2.2 bouyer 373 1.2.2.2 bouyer /* Common memory space extent */ 374 1.2.2.2 bouyer ch->ch_memsize = 0x01000000; 375 1.2.2.2 bouyer for (i = 0; i < MEMWIN_16M_MAX; i++) { 376 1.2.2.2 bouyer ch->ch_cmemt[i] = bus_space_create("PCMCIA common memory", 377 1.2.2.2 bouyer membase + 0x01000000, 378 1.2.2.2 bouyer ch->ch_memsize); 379 1.2.2.2 bouyer } 380 1.2.2.2 bouyer 381 1.2.2.2 bouyer /* I/O port extent and interrupt staff */ 382 1.2.2.2 bouyer _chip_socket_disable(ch); /* enable CSC interrupt only */ 383 1.2.2.2 bouyer 384 1.2.2.2 bouyer if (channel == CHANNEL_0) { 385 1.2.2.2 bouyer ch->ch_iobase = 0; 386 1.2.2.2 bouyer ch->ch_iosize = HD64461_PCC0_IOSIZE; 387 1.2.2.2 bouyer ch->ch_iot = bus_space_create("PCMCIA I/O port", 388 1.2.2.2 bouyer HD64461_PCC0_IOBASE, 389 1.2.2.2 bouyer ch->ch_iosize); 390 1.2.2.2 bouyer 391 1.2.2.2 bouyer 392 1.2.2.2 bouyer hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 393 1.2.2.2 bouyer hd64461pcmcia_channel0_intr, ch); 394 1.2.2.2 bouyer } else { 395 1.2.2.2 bouyer set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 396 1.2.2.2 bouyer hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 397 1.2.2.2 bouyer hd64461pcmcia_channel1_intr, ch); 398 1.2.2.2 bouyer } 399 1.2.2.2 bouyer 400 1.2.2.2 bouyer paa.paa_busname = "pcmcia"; 401 1.2.2.2 bouyer paa.pch = (pcmcia_chipset_handle_t)ch; 402 1.2.2.2 bouyer paa.iobase = ch->ch_iobase; 403 1.2.2.2 bouyer paa.iosize = ch->ch_iosize; 404 1.2.2.2 bouyer 405 1.2.2.2 bouyer ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 406 1.2.2.2 bouyer hd64461pcmcia_submatch); 407 1.2.2.2 bouyer 408 1.2.2.2 bouyer if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 409 1.2.2.2 bouyer ch->ch_attached = 1; 410 1.2.2.2 bouyer pcmcia_card_attach(ch->ch_pcmcia); 411 1.2.2.2 bouyer } 412 1.2.2.2 bouyer } 413 1.2.2.2 bouyer 414 1.2.2.2 bouyer static int 415 1.2.2.2 bouyer hd64461pcmcia_channel0_intr(void *arg) 416 1.2.2.2 bouyer { 417 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 418 1.2.2.2 bouyer u_int8_t r; 419 1.2.2.2 bouyer int ret = 0; 420 1.2.2.2 bouyer 421 1.2.2.2 bouyer r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 422 1.2.2.2 bouyer /* clear interrtupt (edge source only) */ 423 1.2.2.2 bouyer hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 424 1.2.2.2 bouyer 425 1.2.2.2 bouyer if (r & HD64461_PCC0CSCR_P0IREQ) { 426 1.2.2.2 bouyer if (ch->ch_ih_card_func) 427 1.2.2.2 bouyer ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 428 1.2.2.2 bouyer else 429 1.2.2.2 bouyer DPRINTF("spurious IREQ interrupt.\n"); 430 1.2.2.2 bouyer } 431 1.2.2.2 bouyer 432 1.2.2.2 bouyer if (r & HD64461_PCC0CSCR_P0CDC) 433 1.2.2.2 bouyer queue_event(ch, detect_card(ch->ch_channel)); 434 1.2.2.2 bouyer 435 1.2.2.2 bouyer return ret; 436 1.2.2.2 bouyer } 437 1.2.2.2 bouyer 438 1.2.2.2 bouyer static int 439 1.2.2.2 bouyer hd64461pcmcia_channel1_intr(void *arg) 440 1.2.2.2 bouyer { 441 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 442 1.2.2.2 bouyer u_int8_t r; 443 1.2.2.2 bouyer int ret = 0; 444 1.2.2.2 bouyer 445 1.2.2.2 bouyer r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 446 1.2.2.2 bouyer /* clear interrtupt */ 447 1.2.2.2 bouyer hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 448 1.2.2.2 bouyer 449 1.2.2.2 bouyer if (r & HD64461_PCC1CSCR_P1RC) { 450 1.2.2.2 bouyer if (ch->ch_ih_card_func) 451 1.2.2.2 bouyer ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 452 1.2.2.2 bouyer else 453 1.2.2.2 bouyer DPRINTF("spurious READY interrupt.\n"); 454 1.2.2.2 bouyer } 455 1.2.2.2 bouyer 456 1.2.2.2 bouyer if (r & HD64461_PCC1CSCR_P1CDC) 457 1.2.2.2 bouyer queue_event(ch, detect_card(ch->ch_channel)); 458 1.2.2.2 bouyer 459 1.2.2.2 bouyer return ret; 460 1.2.2.2 bouyer } 461 1.2.2.2 bouyer 462 1.2.2.2 bouyer static void 463 1.2.2.2 bouyer queue_event(struct hd64461pcmcia_channel *ch, 464 1.2.2.2 bouyer enum hd64461pcmcia_event_type type) 465 1.2.2.2 bouyer { 466 1.2.2.2 bouyer struct hd64461pcmcia_event *pe, *pool; 467 1.2.2.2 bouyer struct hd64461pcmcia_softc *sc = ch->ch_parent; 468 1.2.2.2 bouyer int i; 469 1.2.2.2 bouyer int s = splhigh(); 470 1.2.2.2 bouyer 471 1.2.2.2 bouyer if (type == EVENT_NONE) 472 1.2.2.2 bouyer goto out; 473 1.2.2.2 bouyer 474 1.2.2.2 bouyer pe = 0; 475 1.2.2.2 bouyer pool = sc->sc_event_pool; 476 1.2.2.2 bouyer for (i = 0; i < EVENT_QUEUE_MAX; i++) { 477 1.2.2.2 bouyer if (!pool[i].__queued) { 478 1.2.2.2 bouyer pe = &pool[i]; 479 1.2.2.2 bouyer break; 480 1.2.2.2 bouyer } 481 1.2.2.2 bouyer } 482 1.2.2.2 bouyer 483 1.2.2.2 bouyer if (pe == 0) { 484 1.2.2.2 bouyer printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 485 1.2.2.2 bouyer EVENT_QUEUE_MAX); 486 1.2.2.2 bouyer goto out; 487 1.2.2.2 bouyer } 488 1.2.2.2 bouyer 489 1.2.2.2 bouyer if ((ch->ch_attached && (type == EVENT_INSERT)) || 490 1.2.2.2 bouyer (!ch->ch_attached && (type == EVENT_REMOVE))) { 491 1.2.2.2 bouyer DPRINTF("spurious CSC interrupt.\n"); 492 1.2.2.2 bouyer goto out; 493 1.2.2.2 bouyer } 494 1.2.2.2 bouyer 495 1.2.2.2 bouyer ch->ch_attached = (type == EVENT_INSERT); 496 1.2.2.2 bouyer pe->__queued = 1; 497 1.2.2.2 bouyer pe->pe_type = type; 498 1.2.2.2 bouyer pe->pe_ch = ch; 499 1.2.2.2 bouyer SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 500 1.2.2.2 bouyer wakeup(sc); 501 1.2.2.2 bouyer out: 502 1.2.2.2 bouyer splx(s); 503 1.2.2.2 bouyer } 504 1.2.2.2 bouyer 505 1.2.2.2 bouyer /* 506 1.2.2.2 bouyer * interface for pcmcia driver. 507 1.2.2.2 bouyer */ 508 1.2.2.2 bouyer static void * 509 1.2.2.2 bouyer _chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, 510 1.2.2.2 bouyer int ipl, int (*ih_func)(void *), void *ih_arg) 511 1.2.2.2 bouyer { 512 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 513 1.2.2.2 bouyer int channel = ch->ch_channel; 514 1.2.2.2 bouyer bus_addr_t cscier = HD64461_PCCCSCIER(channel); 515 1.2.2.2 bouyer int s = splhigh(); 516 1.2.2.2 bouyer u_int8_t r; 517 1.2.2.2 bouyer 518 1.2.2.2 bouyer ch->ch_ih_card_func = ih_func; 519 1.2.2.2 bouyer ch->ch_ih_card_arg = ih_arg; 520 1.2.2.2 bouyer 521 1.2.2.2 bouyer /* enable card interrupt */ 522 1.2.2.2 bouyer r = hd64461_reg_read_1(cscier); 523 1.2.2.2 bouyer if (channel == CHANNEL_0) { 524 1.2.2.2 bouyer /* set level mode */ 525 1.2.2.2 bouyer r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 526 1.2.2.2 bouyer r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 527 1.2.2.2 bouyer } else { 528 1.2.2.2 bouyer /* READY-pin LOW to HIGH changes generates interrupt */ 529 1.2.2.2 bouyer r |= HD64461_PCC1CSCIER_P1RE; 530 1.2.2.2 bouyer } 531 1.2.2.2 bouyer hd64461_reg_write_1(cscier, r); 532 1.2.2.2 bouyer 533 1.2.2.2 bouyer splx(s); 534 1.2.2.2 bouyer 535 1.2.2.2 bouyer return (void *)ih_func; 536 1.2.2.2 bouyer } 537 1.2.2.2 bouyer 538 1.2.2.2 bouyer static void 539 1.2.2.2 bouyer _chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 540 1.2.2.2 bouyer { 541 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 542 1.2.2.2 bouyer int channel = ch->ch_channel; 543 1.2.2.2 bouyer bus_addr_t cscier = HD64461_PCCCSCIER(channel); 544 1.2.2.2 bouyer int s = splhigh(); 545 1.2.2.2 bouyer u_int8_t r; 546 1.2.2.2 bouyer 547 1.2.2.2 bouyer /* disable card interrupt */ 548 1.2.2.2 bouyer r = hd64461_reg_read_1(cscier); 549 1.2.2.2 bouyer if (channel == CHANNEL_0) { 550 1.2.2.2 bouyer r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 551 1.2.2.2 bouyer r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 552 1.2.2.2 bouyer } else { 553 1.2.2.2 bouyer r &= ~HD64461_PCC1CSCIER_P1RE; 554 1.2.2.2 bouyer } 555 1.2.2.2 bouyer hd64461_reg_write_1(cscier, r); 556 1.2.2.2 bouyer 557 1.2.2.2 bouyer ch->ch_ih_card_func = 0; 558 1.2.2.2 bouyer 559 1.2.2.2 bouyer splx(s); 560 1.2.2.2 bouyer } 561 1.2.2.2 bouyer 562 1.2.2.2 bouyer static int 563 1.2.2.2 bouyer _chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 564 1.2.2.2 bouyer struct pcmcia_mem_handle *pcmhp) 565 1.2.2.2 bouyer { 566 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 567 1.2.2.2 bouyer 568 1.2.2.2 bouyer pcmhp->memt = ch->ch_memt; 569 1.2.2.2 bouyer pcmhp->addr = ch->ch_membase_addr; 570 1.2.2.2 bouyer pcmhp->memh = ch->ch_memh; 571 1.2.2.2 bouyer pcmhp->size = size; 572 1.2.2.2 bouyer pcmhp->realsize = size; 573 1.2.2.2 bouyer 574 1.2.2.2 bouyer DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 575 1.2.2.2 bouyer 576 1.2.2.2 bouyer return (0); 577 1.2.2.2 bouyer } 578 1.2.2.2 bouyer 579 1.2.2.2 bouyer static void 580 1.2.2.2 bouyer _chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 581 1.2.2.2 bouyer { 582 1.2.2.2 bouyer /* nothing to do */ 583 1.2.2.2 bouyer } 584 1.2.2.2 bouyer 585 1.2.2.2 bouyer static int 586 1.2.2.2 bouyer _chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, 587 1.2.2.2 bouyer bus_size_t size, struct pcmcia_mem_handle *pcmhp, 588 1.2.2.2 bouyer bus_addr_t *offsetp, int *windowp) 589 1.2.2.2 bouyer { 590 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 591 1.2.2.2 bouyer struct hd64461pcmcia_window_cookie *cookie; 592 1.2.2.2 bouyer bus_addr_t ofs; 593 1.2.2.2 bouyer 594 1.2.2.2 bouyer cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 595 1.2.2.2 bouyer M_DEVBUF, M_NOWAIT); 596 1.2.2.2 bouyer KASSERT(cookie); 597 1.2.2.2 bouyer memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 598 1.2.2.2 bouyer 599 1.2.2.2 bouyer /* Address */ 600 1.2.2.2 bouyer if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 601 1.2.2.2 bouyer cookie->wc_tag = ch->ch_memt; 602 1.2.2.2 bouyer if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 603 1.2.2.2 bouyer size, &cookie->wc_handle) != 0) 604 1.2.2.2 bouyer goto bad; 605 1.2.2.2 bouyer 606 1.2.2.2 bouyer *offsetp = card_addr; 607 1.2.2.2 bouyer cookie->wc_window = -1; 608 1.2.2.2 bouyer } else { 609 1.2.2.2 bouyer int window = card_addr / ch->ch_memsize; 610 1.2.2.2 bouyer KASSERT(window < MEMWIN_16M_MAX); 611 1.2.2.2 bouyer 612 1.2.2.2 bouyer cookie->wc_tag = ch->ch_cmemt[window]; 613 1.2.2.2 bouyer ofs = card_addr - window * ch->ch_memsize; 614 1.2.2.2 bouyer if (bus_space_map(cookie->wc_tag, ofs, size, 0, 615 1.2.2.2 bouyer &cookie->wc_handle) != 0) 616 1.2.2.2 bouyer goto bad; 617 1.2.2.2 bouyer 618 1.2.2.2 bouyer // XXX bogus. bus_space_tag should be vtbl... 619 1.2.2.2 bouyer memory_window_16(ch->ch_channel, window); 620 1.2.2.2 bouyer *offsetp = ofs + 0x01000000; /* skip attribute area */ 621 1.2.2.2 bouyer cookie->wc_window = window; 622 1.2.2.2 bouyer } 623 1.2.2.2 bouyer cookie->wc_size = size; 624 1.2.2.2 bouyer *windowp = (int)cookie; 625 1.2.2.2 bouyer 626 1.2.2.2 bouyer DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 627 1.2.2.2 bouyer "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 628 1.2.2.2 bouyer size); 629 1.2.2.2 bouyer 630 1.2.2.2 bouyer return (0); 631 1.2.2.2 bouyer bad: 632 1.2.2.2 bouyer DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 633 1.2.2.2 bouyer free(cookie, M_DEVBUF); 634 1.2.2.2 bouyer 635 1.2.2.2 bouyer return (1); 636 1.2.2.2 bouyer } 637 1.2.2.2 bouyer 638 1.2.2.2 bouyer static void 639 1.2.2.2 bouyer _chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 640 1.2.2.2 bouyer { 641 1.2.2.2 bouyer struct hd64461pcmcia_window_cookie *cookie = (void *)window; 642 1.2.2.2 bouyer 643 1.2.2.2 bouyer if (cookie->wc_window != -1) 644 1.2.2.2 bouyer bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 645 1.2.2.2 bouyer cookie->wc_size); 646 1.2.2.2 bouyer DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 647 1.2.2.2 bouyer free(cookie, M_DEVBUF); 648 1.2.2.2 bouyer } 649 1.2.2.2 bouyer 650 1.2.2.2 bouyer static int 651 1.2.2.2 bouyer _chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, 652 1.2.2.2 bouyer bus_size_t align, struct pcmcia_io_handle *pcihp) 653 1.2.2.2 bouyer { 654 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 655 1.2.2.2 bouyer 656 1.2.2.2 bouyer if (ch->ch_channel == CHANNEL_1) 657 1.2.2.2 bouyer return (1); 658 1.2.2.2 bouyer 659 1.2.2.2 bouyer if (start) { 660 1.2.2.2 bouyer if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 661 1.2.2.2 bouyer DPRINTF("couldn't map %#lx+%#lx\n", start, size); 662 1.2.2.2 bouyer return (1); 663 1.2.2.2 bouyer } 664 1.2.2.2 bouyer DPRINTF("map %#lx+%#lx\n", start, size); 665 1.2.2.2 bouyer } else { 666 1.2.2.2 bouyer if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 667 1.2.2.2 bouyer ch->ch_iobase + ch->ch_iosize, 668 1.2.2.2 bouyer size, align, 0, 0, &pcihp->addr, 669 1.2.2.2 bouyer &pcihp->ioh)) { 670 1.2.2.2 bouyer DPRINTF("couldn't allocate %#lx\n", size); 671 1.2.2.2 bouyer return (1); 672 1.2.2.2 bouyer } 673 1.2.2.2 bouyer pcihp->flags = PCMCIA_IO_ALLOCATED; 674 1.2.2.2 bouyer DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 675 1.2.2.2 bouyer } 676 1.2.2.2 bouyer 677 1.2.2.2 bouyer pcihp->iot = ch->ch_iot; 678 1.2.2.2 bouyer pcihp->size = size; 679 1.2.2.2 bouyer 680 1.2.2.2 bouyer return (0); 681 1.2.2.2 bouyer } 682 1.2.2.2 bouyer 683 1.2.2.2 bouyer static int 684 1.2.2.2 bouyer _chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 685 1.2.2.2 bouyer bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 686 1.2.2.2 bouyer { 687 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 688 1.2.2.2 bouyer #ifdef HD64461PCMCIA_DEBUG 689 1.2.2.2 bouyer static char *width_names[] = { "auto", "io8", "io16" }; 690 1.2.2.2 bouyer #endif 691 1.2.2.2 bouyer if (ch->ch_channel == CHANNEL_1) 692 1.2.2.2 bouyer return (1); 693 1.2.2.2 bouyer 694 1.2.2.2 bouyer set_bus_width(CHANNEL_0, width); 695 1.2.2.2 bouyer 696 1.2.2.2 bouyer DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 697 1.2.2.2 bouyer width_names[width]); 698 1.2.2.2 bouyer 699 1.2.2.2 bouyer return (0); 700 1.2.2.2 bouyer } 701 1.2.2.2 bouyer 702 1.2.2.2 bouyer static void 703 1.2.2.2 bouyer _chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 704 1.2.2.2 bouyer { 705 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 706 1.2.2.2 bouyer 707 1.2.2.2 bouyer if (ch->ch_channel == CHANNEL_1) 708 1.2.2.2 bouyer return; 709 1.2.2.2 bouyer 710 1.2.2.2 bouyer if (pcihp->flags & PCMCIA_IO_ALLOCATED) 711 1.2.2.2 bouyer bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 712 1.2.2.2 bouyer else 713 1.2.2.2 bouyer bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 714 1.2.2.2 bouyer 715 1.2.2.2 bouyer DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 716 1.2.2.2 bouyer } 717 1.2.2.2 bouyer 718 1.2.2.2 bouyer static void 719 1.2.2.2 bouyer _chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 720 1.2.2.2 bouyer { 721 1.2.2.2 bouyer /* nothing to do */ 722 1.2.2.2 bouyer } 723 1.2.2.2 bouyer 724 1.2.2.2 bouyer static void 725 1.2.2.2 bouyer _chip_socket_enable(pcmcia_chipset_handle_t pch) 726 1.2.2.2 bouyer { 727 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 728 1.2.2.2 bouyer int channel = ch->ch_channel; 729 1.2.2.2 bouyer bus_addr_t isr, gcr; 730 1.2.2.2 bouyer u_int8_t r; 731 1.2.2.2 bouyer int cardtype; 732 1.2.2.2 bouyer int i; 733 1.2.2.2 bouyer 734 1.2.2.2 bouyer DPRINTF("enable channel %d\n", channel); 735 1.2.2.2 bouyer isr = HD64461_PCCISR(channel); 736 1.2.2.2 bouyer gcr = HD64461_PCCGCR(channel); 737 1.2.2.2 bouyer 738 1.2.2.2 bouyer power_off(channel); 739 1.2.2.2 bouyer power_on(channel); 740 1.2.2.2 bouyer 741 1.2.2.2 bouyer /* assert reset */ 742 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 743 1.2.2.2 bouyer r |= HD64461_PCCGCR_PCCR; 744 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 745 1.2.2.2 bouyer 746 1.2.2.2 bouyer /* 747 1.2.2.2 bouyer * hold RESET at least 10us. 748 1.2.2.2 bouyer */ 749 1.2.2.2 bouyer DELAY_MS(20); 750 1.2.2.2 bouyer 751 1.2.2.2 bouyer /* clear the reset flag */ 752 1.2.2.2 bouyer r &= ~HD64461_PCCGCR_PCCR; 753 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 754 1.2.2.2 bouyer DELAY_MS(2000); 755 1.2.2.2 bouyer 756 1.2.2.2 bouyer /* wait for the chip to finish initializing */ 757 1.2.2.2 bouyer for (i = 0; i < 10000; i++) { 758 1.2.2.2 bouyer if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 759 1.2.2.2 bouyer goto reset_ok; 760 1.2.2.2 bouyer DELAY_MS(500); 761 1.2.2.2 bouyer 762 1.2.2.2 bouyer if ((i > 5000) && (i % 100 == 99)) 763 1.2.2.2 bouyer printf("."); 764 1.2.2.2 bouyer } 765 1.2.2.2 bouyer printf("reset failed.\n"); 766 1.2.2.2 bouyer power_off(channel); 767 1.2.2.2 bouyer return; 768 1.2.2.2 bouyer reset_ok: 769 1.2.2.2 bouyer 770 1.2.2.2 bouyer /* set Continuous 16-MB Area Mode */ 771 1.2.2.2 bouyer ch->ch_memory_window_mode = MEMWIN_16M_MODE; 772 1.2.2.2 bouyer memory_window_mode(channel, ch->ch_memory_window_mode); 773 1.2.2.2 bouyer 774 1.2.2.2 bouyer /* 775 1.2.2.2 bouyer * set Common memory area. 776 1.2.2.2 bouyer */ 777 1.2.2.2 bouyer memory_window_16(channel, MEMWIN_16M_COMMON_0); 778 1.2.2.2 bouyer 779 1.2.2.2 bouyer /* set the card type */ 780 1.2.2.2 bouyer if (channel == CHANNEL_0) { 781 1.2.2.2 bouyer cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 782 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 783 1.2.2.2 bouyer if (cardtype == PCMCIA_IFTYPE_IO) 784 1.2.2.2 bouyer r |= HD64461_PCC0GCR_P0PCCT; 785 1.2.2.2 bouyer else 786 1.2.2.2 bouyer r &= ~HD64461_PCC0GCR_P0PCCT; 787 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 788 1.2.2.2 bouyer } 789 1.2.2.2 bouyer 790 1.2.2.2 bouyer 791 1.2.2.2 bouyer DPRINTF("OK.\n"); 792 1.2.2.2 bouyer } 793 1.2.2.2 bouyer 794 1.2.2.2 bouyer static void 795 1.2.2.2 bouyer _chip_socket_disable(pcmcia_chipset_handle_t pch) 796 1.2.2.2 bouyer { 797 1.2.2.2 bouyer struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 798 1.2.2.2 bouyer int channel = ch->ch_channel; 799 1.2.2.2 bouyer 800 1.2.2.2 bouyer /* dont' disable CSC interrupt */ 801 1.2.2.2 bouyer hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 802 1.2.2.2 bouyer hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 803 1.2.2.2 bouyer 804 1.2.2.2 bouyer /* power down the socket */ 805 1.2.2.2 bouyer power_off(channel); 806 1.2.2.2 bouyer } 807 1.2.2.2 bouyer 808 1.2.2.2 bouyer /* 809 1.2.2.2 bouyer * Card detect 810 1.2.2.2 bouyer */ 811 1.2.2.2 bouyer static void 812 1.2.2.2 bouyer power_off(enum controller_channel channel) 813 1.2.2.2 bouyer { 814 1.2.2.2 bouyer u_int8_t r; 815 1.2.2.2 bouyer u_int16_t r16; 816 1.2.2.2 bouyer bus_addr_t scr, gcr; 817 1.2.2.2 bouyer 818 1.2.2.2 bouyer gcr = HD64461_PCCGCR(channel); 819 1.2.2.2 bouyer scr = HD64461_PCCSCR(channel); 820 1.2.2.2 bouyer 821 1.2.2.2 bouyer /* DRV (external buffer) high level */ 822 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 823 1.2.2.2 bouyer r &= ~HD64461_PCCGCR_DRVE; 824 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 825 1.2.2.2 bouyer 826 1.2.2.2 bouyer /* stop power */ 827 1.2.2.2 bouyer r = hd64461_reg_read_1(scr); 828 1.2.2.2 bouyer r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 829 1.2.2.2 bouyer hd64461_reg_write_1(scr, r); 830 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 831 1.2.2.2 bouyer r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 832 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 833 1.2.2.2 bouyer /* 834 1.2.2.2 bouyer * wait 300ms until power fails (Tpf). Then, wait 100ms since 835 1.2.2.2 bouyer * we are changing Vcc (Toff). 836 1.2.2.2 bouyer */ 837 1.2.2.2 bouyer DELAY_MS(300 + 100); 838 1.2.2.2 bouyer 839 1.2.2.2 bouyer /* stop clock */ 840 1.2.2.2 bouyer r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 841 1.2.2.2 bouyer r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 842 1.2.2.2 bouyer HD64461_SYSSTBCR_SPC1ST); 843 1.2.2.2 bouyer hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 844 1.2.2.2 bouyer 845 1.2.2.2 bouyer if (channel == CHANNEL_0) { 846 1.2.2.2 bouyer /* GPIO Port A XXX Jonanada690 specific? */ 847 1.2.2.2 bouyer r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 848 1.2.2.2 bouyer r16 |= 0xf; 849 1.2.2.2 bouyer hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 850 1.2.2.2 bouyer } 851 1.2.2.2 bouyer } 852 1.2.2.2 bouyer 853 1.2.2.2 bouyer static void 854 1.2.2.2 bouyer power_on(enum controller_channel channel) 855 1.2.2.2 bouyer { 856 1.2.2.2 bouyer u_int8_t r; 857 1.2.2.2 bouyer u_int16_t r16; 858 1.2.2.2 bouyer bus_addr_t scr, gcr, isr; 859 1.2.2.2 bouyer 860 1.2.2.2 bouyer isr = HD64461_PCCISR(channel); 861 1.2.2.2 bouyer gcr = HD64461_PCCGCR(channel); 862 1.2.2.2 bouyer scr = HD64461_PCCSCR(channel); 863 1.2.2.2 bouyer 864 1.2.2.2 bouyer if (channel == CHANNEL_0) { 865 1.2.2.2 bouyer /* GPIO Port A XXX Jonanada690 specific? */ 866 1.2.2.2 bouyer r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 867 1.2.2.2 bouyer r16 &= ~0xf; 868 1.2.2.2 bouyer r16 |= 0x5; 869 1.2.2.2 bouyer hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 870 1.2.2.2 bouyer } 871 1.2.2.2 bouyer 872 1.2.2.2 bouyer /* supply clock */ 873 1.2.2.2 bouyer r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 874 1.2.2.2 bouyer r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 875 1.2.2.2 bouyer HD64461_SYSSTBCR_SPC1ST); 876 1.2.2.2 bouyer hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 877 1.2.2.2 bouyer DELAY_MS(200); 878 1.2.2.2 bouyer 879 1.2.2.2 bouyer /* detect voltage and supply VCC */ 880 1.2.2.2 bouyer r = hd64461_reg_read_1(isr); 881 1.2.2.2 bouyer switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 882 1.2.2.2 bouyer case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): 883 1.2.2.2 bouyer DPRINTF("5V card\n"); 884 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 885 1.2.2.2 bouyer r &= ~HD64461_PCCGCR_VCC0; 886 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 887 1.2.2.2 bouyer r = hd64461_reg_read_1(scr); 888 1.2.2.2 bouyer r &= ~HD64461_PCCSCR_VCC1; 889 1.2.2.2 bouyer hd64461_reg_write_1(scr, r); 890 1.2.2.2 bouyer break; 891 1.2.2.2 bouyer case HD64461_PCCISR_VS2: 892 1.2.2.2 bouyer DPRINTF("3.3V card\n"); 893 1.2.2.2 bouyer if (channel == CHANNEL_1) { 894 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 895 1.2.2.2 bouyer r &= ~HD64461_PCCGCR_VCC0; 896 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 897 1.2.2.2 bouyer } 898 1.2.2.2 bouyer r = hd64461_reg_read_1(scr); 899 1.2.2.2 bouyer r &= ~HD64461_PCCSCR_VCC1; 900 1.2.2.2 bouyer hd64461_reg_write_1(scr, r); 901 1.2.2.2 bouyer break; 902 1.2.2.2 bouyer default: 903 1.2.2.2 bouyer printf("\nunknown Voltage. don't attach.\n"); 904 1.2.2.2 bouyer return; 905 1.2.2.2 bouyer } 906 1.2.2.2 bouyer /* 907 1.2.2.2 bouyer * wait 100ms until power raise (Tpr) and 20ms to become 908 1.2.2.2 bouyer * stable (Tsu(Vcc)). 909 1.2.2.2 bouyer * 910 1.2.2.2 bouyer * some machines require some more time to be settled 911 1.2.2.2 bouyer * (300ms is added here). 912 1.2.2.2 bouyer */ 913 1.2.2.2 bouyer DELAY_MS(100 + 20 + 300); 914 1.2.2.2 bouyer 915 1.2.2.2 bouyer /* DRV (external buffer) low level */ 916 1.2.2.2 bouyer r = hd64461_reg_read_1(gcr); 917 1.2.2.2 bouyer r |= HD64461_PCCGCR_DRVE; 918 1.2.2.2 bouyer hd64461_reg_write_1(gcr, r); 919 1.2.2.2 bouyer 920 1.2.2.2 bouyer /* clear interrupt */ 921 1.2.2.2 bouyer hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 922 1.2.2.2 bouyer HD64461_PCC1CSCR_REG8, 0); 923 1.2.2.2 bouyer } 924 1.2.2.2 bouyer 925 1.2.2.2 bouyer static enum hd64461pcmcia_event_type 926 1.2.2.2 bouyer detect_card(enum controller_channel channel) 927 1.2.2.2 bouyer { 928 1.2.2.2 bouyer u_int8_t r; 929 1.2.2.2 bouyer 930 1.2.2.2 bouyer r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 931 1.2.2.2 bouyer (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 932 1.2.2.2 bouyer 933 1.2.2.2 bouyer if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 934 1.2.2.2 bouyer DPRINTF("remove\n"); 935 1.2.2.2 bouyer return EVENT_REMOVE; 936 1.2.2.2 bouyer } 937 1.2.2.2 bouyer if (r == 0) { 938 1.2.2.2 bouyer DPRINTF("insert\n"); 939 1.2.2.2 bouyer return EVENT_INSERT; 940 1.2.2.2 bouyer } 941 1.2.2.2 bouyer DPRINTF("transition\n"); 942 1.2.2.2 bouyer 943 1.2.2.2 bouyer return EVENT_NONE; 944 1.2.2.2 bouyer } 945 1.2.2.2 bouyer 946 1.2.2.2 bouyer /* 947 1.2.2.2 bouyer * Memory window access ops. 948 1.2.2.2 bouyer */ 949 1.2.2.2 bouyer static void 950 1.2.2.2 bouyer memory_window_mode(enum controller_channel channel, 951 1.2.2.2 bouyer enum memory_window_mode mode) 952 1.2.2.2 bouyer { 953 1.2.2.2 bouyer bus_addr_t a = HD64461_PCCGCR(channel); 954 1.2.2.2 bouyer u_int8_t r = hd64461_reg_read_1(a); 955 1.2.2.2 bouyer 956 1.2.2.2 bouyer r &= ~HD64461_PCCGCR_MMOD; 957 1.2.2.2 bouyer r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 958 1.2.2.2 bouyer HD64461_PCCGCR_MMOD_32M; 959 1.2.2.2 bouyer hd64461_reg_write_1(a, r); 960 1.2.2.2 bouyer } 961 1.2.2.2 bouyer 962 1.2.2.2 bouyer static void 963 1.2.2.2 bouyer memory_window_16(enum controller_channel channel, enum memory_window_16 window) 964 1.2.2.2 bouyer { 965 1.2.2.2 bouyer bus_addr_t a = HD64461_PCCGCR(channel); 966 1.2.2.2 bouyer u_int8_t r; 967 1.2.2.2 bouyer 968 1.2.2.2 bouyer r = hd64461_reg_read_1(a); 969 1.2.2.2 bouyer r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 970 1.2.2.2 bouyer 971 1.2.2.2 bouyer switch (window) { 972 1.2.2.2 bouyer case MEMWIN_16M_COMMON_0: 973 1.2.2.2 bouyer break; 974 1.2.2.2 bouyer case MEMWIN_16M_COMMON_1: 975 1.2.2.2 bouyer r |= HD64461_PCCGCR_PA24; 976 1.2.2.2 bouyer break; 977 1.2.2.2 bouyer case MEMWIN_16M_COMMON_2: 978 1.2.2.2 bouyer r |= HD64461_PCCGCR_PA25; 979 1.2.2.2 bouyer break; 980 1.2.2.2 bouyer case MEMWIN_16M_COMMON_3: 981 1.2.2.2 bouyer r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 982 1.2.2.2 bouyer break; 983 1.2.2.2 bouyer } 984 1.2.2.2 bouyer 985 1.2.2.2 bouyer hd64461_reg_write_1(a, r); 986 1.2.2.2 bouyer } 987 1.2.2.2 bouyer 988 1.2.2.2 bouyer #if unused 989 1.2.2.2 bouyer static void 990 1.2.2.2 bouyer memory_window_32(enum controller_channel channel, enum memory_window_32 window) 991 1.2.2.2 bouyer { 992 1.2.2.2 bouyer bus_addr_t a = HD64461_PCCGCR(channel); 993 1.2.2.2 bouyer u_int8_t r; 994 1.2.2.2 bouyer 995 1.2.2.2 bouyer r = hd64461_reg_read_1(a); 996 1.2.2.2 bouyer r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 997 1.2.2.2 bouyer 998 1.2.2.2 bouyer switch (window) { 999 1.2.2.2 bouyer case MEMWIN_32M_ATTR: 1000 1.2.2.2 bouyer break; 1001 1.2.2.2 bouyer case MEMWIN_32M_COMMON_0: 1002 1.2.2.2 bouyer r |= HD64461_PCCGCR_PREG; 1003 1.2.2.2 bouyer break; 1004 1.2.2.2 bouyer case MEMWIN_32M_COMMON_1: 1005 1.2.2.2 bouyer r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1006 1.2.2.2 bouyer break; 1007 1.2.2.2 bouyer } 1008 1.2.2.2 bouyer 1009 1.2.2.2 bouyer hd64461_reg_write_1(a, r); 1010 1.2.2.2 bouyer } 1011 1.2.2.2 bouyer #endif 1012 1.2.2.2 bouyer 1013 1.2.2.2 bouyer static void 1014 1.2.2.2 bouyer set_bus_width(enum controller_channel channel, int width) 1015 1.2.2.2 bouyer { 1016 1.2.2.2 bouyer u_int16_t r16; 1017 1.2.2.2 bouyer 1018 1.2.2.2 bouyer r16 = SHREG_BCR2; 1019 1.2.2.2 bouyer if (channel == CHANNEL_0) { 1020 1.2.2.2 bouyer r16 &= ~((1 << 13)|(1 << 12)); 1021 1.2.2.2 bouyer r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1022 1.2.2.2 bouyer } else { 1023 1.2.2.2 bouyer r16 &= ~((1 << 11)|(1 << 10)); 1024 1.2.2.2 bouyer r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1025 1.2.2.2 bouyer } 1026 1.2.2.2 bouyer SHREG_BCR2 = r16; 1027 1.2.2.2 bouyer } 1028 1.2.2.2 bouyer 1029 1.2.2.2 bouyer #ifdef DEBUG 1030 1.2.2.2 bouyer static void 1031 1.2.2.2 bouyer hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1032 1.2.2.2 bouyer { 1033 1.2.2.2 bouyer const char name[] = __FUNCTION__; 1034 1.2.2.2 bouyer u_int8_t r8; 1035 1.2.2.2 bouyer 1036 1.2.2.2 bouyer dbg_banner_start(name, sizeof name); 1037 1.2.2.2 bouyer /* 1038 1.2.2.2 bouyer * PCC0 1039 1.2.2.2 bouyer */ 1040 1.2.2.2 bouyer printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1041 1.2.2.2 bouyer printf("PCC0 Interface Status Register\n"); 1042 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1043 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 1044 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0READY); 1045 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0MWP); 1046 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0VS2); 1047 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0VS1); 1048 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0CD2); 1049 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0CD1); 1050 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0BVD2); 1051 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0BVD1); 1052 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1053 1.2.2.2 bouyer printf("\n"); 1054 1.2.2.2 bouyer 1055 1.2.2.2 bouyer printf("PCC0 General Control Register\n"); 1056 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1057 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 1058 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0DRVE); 1059 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0PCCR); 1060 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0PCCT); 1061 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0VCC0); 1062 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0MMOD); 1063 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0PA25); 1064 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0PA24); 1065 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0REG); 1066 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1067 1.2.2.2 bouyer printf("\n"); 1068 1.2.2.2 bouyer 1069 1.2.2.2 bouyer printf("PCC0 Card Status Change Register\n"); 1070 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1071 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 1072 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0SCDI); 1073 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0IREQ); 1074 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0SC); 1075 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0CDC); 1076 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0RC); 1077 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0BW); 1078 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0BD); 1079 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1080 1.2.2.2 bouyer printf("\n"); 1081 1.2.2.2 bouyer 1082 1.2.2.2 bouyer printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1083 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1084 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 1085 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0CRE); 1086 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0SCE); 1087 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0CDE); 1088 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0RE); 1089 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0BWE); 1090 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0BDE); 1091 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1092 1.2.2.2 bouyer printf("\ninterrupt type: "); 1093 1.2.2.2 bouyer switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1094 1.2.2.2 bouyer case HD64461_PCC0CSCIER_P0IREQE_NONE: 1095 1.2.2.2 bouyer printf("none\n"); 1096 1.2.2.2 bouyer break; 1097 1.2.2.2 bouyer case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1098 1.2.2.2 bouyer printf("level\n"); 1099 1.2.2.2 bouyer break; 1100 1.2.2.2 bouyer case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1101 1.2.2.2 bouyer printf("falling edge\n"); 1102 1.2.2.2 bouyer break; 1103 1.2.2.2 bouyer case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1104 1.2.2.2 bouyer printf("rising edge\n"); 1105 1.2.2.2 bouyer break; 1106 1.2.2.2 bouyer } 1107 1.2.2.2 bouyer 1108 1.2.2.2 bouyer printf("PCC0 Software Control Register\n"); 1109 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1110 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 1111 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0VCC1); 1112 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0SWP); 1113 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1114 1.2.2.2 bouyer printf("\n"); 1115 1.2.2.2 bouyer 1116 1.2.2.2 bouyer /* 1117 1.2.2.2 bouyer * PCC1 1118 1.2.2.2 bouyer */ 1119 1.2.2.2 bouyer printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1120 1.2.2.2 bouyer printf("PCC1 Interface Status Register\n"); 1121 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1122 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 1123 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1READY); 1124 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1MWP); 1125 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1VS2); 1126 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1VS1); 1127 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1CD2); 1128 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1CD1); 1129 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1BVD2); 1130 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1BVD1); 1131 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1132 1.2.2.2 bouyer printf("\n"); 1133 1.2.2.2 bouyer 1134 1.2.2.2 bouyer printf("PCC1 General Contorol Register\n"); 1135 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1136 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 1137 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1DRVE); 1138 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1PCCR); 1139 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1VCC0); 1140 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1MMOD); 1141 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1PA25); 1142 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1PA24); 1143 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1REG); 1144 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1145 1.2.2.2 bouyer printf("\n"); 1146 1.2.2.2 bouyer 1147 1.2.2.2 bouyer printf("PCC1 Card Status Change Register\n"); 1148 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1149 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 1150 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1SCDI); 1151 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1CDC); 1152 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1RC); 1153 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1BW); 1154 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1BD); 1155 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1156 1.2.2.2 bouyer printf("\n"); 1157 1.2.2.2 bouyer 1158 1.2.2.2 bouyer printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1159 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1160 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 1161 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1CRE); 1162 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1CDE); 1163 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1RE); 1164 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1BWE); 1165 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1BDE); 1166 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1167 1.2.2.2 bouyer printf("\n"); 1168 1.2.2.2 bouyer 1169 1.2.2.2 bouyer printf("PCC1 Software Control Register\n"); 1170 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1171 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 1172 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1VCC1); 1173 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1SWP); 1174 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1175 1.2.2.2 bouyer printf("\n"); 1176 1.2.2.2 bouyer 1177 1.2.2.2 bouyer /* 1178 1.2.2.2 bouyer * General Control 1179 1.2.2.2 bouyer */ 1180 1.2.2.2 bouyer printf("[General Control]\n"); 1181 1.2.2.2 bouyer printf("PCC0 Output pins Control Register\n"); 1182 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1183 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 1184 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0DEPLUP); 1185 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P0AEPLUP); 1186 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1187 1.2.2.2 bouyer printf("\n"); 1188 1.2.2.2 bouyer 1189 1.2.2.2 bouyer printf("PCC1 Output pins Control Register\n"); 1190 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1191 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 1192 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1RST8MA); 1193 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1RST4MA); 1194 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1RAS8MA); 1195 1.2.2.2 bouyer DBG_BIT_PRINT(r8, P1RAS4MA); 1196 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1197 1.2.2.2 bouyer printf("\n"); 1198 1.2.2.2 bouyer 1199 1.2.2.2 bouyer printf("PC Card General Control Register\n"); 1200 1.2.2.2 bouyer r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1201 1.2.2.2 bouyer #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 1202 1.2.2.2 bouyer DBG_BIT_PRINT(r8, PSSDIR); 1203 1.2.2.2 bouyer DBG_BIT_PRINT(r8, PSSRDWR); 1204 1.2.2.2 bouyer #undef DBG_BIT_PRINT 1205 1.2.2.2 bouyer printf("\n"); 1206 1.2.2.2 bouyer 1207 1.2.2.2 bouyer dbg_banner_end(); 1208 1.2.2.2 bouyer } 1209 1.2.2.2 bouyer #endif /* DEBUG */ 1210 1.2.2.2 bouyer 1211
Indexes created Thu Oct 23 22:10:10 GMT 2025