hd64461pcmcia.c revision 1.1
1 /* $NetBSD: hd64461pcmcia.c,v 1.1 2001/02/21 15:39:09 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #define HD64461PCMCIA_DEBUG 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 #include <sys/boot_flag.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #ifdef DEBUG 51 #include <hpcsh/hpcsh/debug.h> 52 #endif 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcvar.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #ifdef HD64461PCMCIA_DEBUG 67 int hd64461pcmcia_debug = 1; 68 #define DPRINTF(fmt, args...) \ 69 if (hd64461pcmcia_debug) \ 70 printf("%s: " fmt, __FUNCTION__ , ##args) 71 #define DPRINTFN(n, arg) \ 72 if (hd64461pcmcia_debug > (n)) \ 73 printf("%s: " fmt, __FUNCTION__ , ##args) 74 #else 75 #define DPRINTF(arg...) ((void)0) 76 #define DPRINTFN(n, arg...) ((void)0) 77 #endif 78 79 enum controller_channel { 80 CHANNEL_0 = 0, 81 CHANNEL_1 = 1, 82 CHANNEL_MAX = 2 83 }; 84 85 enum memory_window_mode { 86 MEMWIN_16M_MODE, 87 MEMWIN_32M_MODE 88 }; 89 90 enum memory_window_16 { 91 MEMWIN_16M_COMMON_0, 92 MEMWIN_16M_COMMON_1, 93 MEMWIN_16M_COMMON_2, 94 MEMWIN_16M_COMMON_3, 95 }; 96 #define MEMWIN_16M_MAX 4 97 98 enum memory_window_32 { 99 MEMWIN_32M_ATTR, 100 MEMWIN_32M_COMMON_0, 101 MEMWIN_32M_COMMON_1, 102 }; 103 #define MEMWIN_32M_MAX 3 104 105 enum hd64461pcmcia_event_type { 106 EVENT_NONE, 107 EVENT_INSERT, 108 EVENT_REMOVE, 109 }; 110 #define EVENT_QUEUE_MAX 5 111 112 struct hd64461pcmcia_softc; /* forward declaration */ 113 114 struct hd64461pcmcia_window_cookie { 115 bus_space_tag_t wc_tag; 116 bus_space_handle_t wc_handle; 117 int wc_size; 118 int wc_window; 119 }; 120 121 struct hd64461pcmcia_channel { 122 struct hd64461pcmcia_softc *ch_parent; 123 struct device *ch_pcmcia; 124 enum controller_channel ch_channel; 125 126 /* memory space */ 127 enum memory_window_mode ch_memory_window_mode; 128 bus_space_tag_t ch_memt; 129 bus_space_handle_t ch_memh; 130 bus_addr_t ch_membase_addr; 131 bus_size_t ch_memsize; 132 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 133 134 /* I/O space */ 135 bus_space_tag_t ch_iot; 136 bus_addr_t ch_iobase; 137 bus_size_t ch_iosize; 138 139 /* card interrupt */ 140 int (*ch_ih_card_func)(void *); 141 void *ch_ih_card_arg; 142 int ch_attached; 143 }; 144 145 struct hd64461pcmcia_event { 146 int __queued; 147 enum hd64461pcmcia_event_type pe_type; 148 struct hd64461pcmcia_channel *pe_ch; 149 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 150 }; 151 152 struct hd64461pcmcia_softc { 153 struct device sc_dev; 154 enum hd64461_module_id sc_module_id; 155 int sc_shutdown; 156 157 /* CSC event */ 158 struct proc *sc_event_thread; 159 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 160 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 161 162 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 163 }; 164 165 static int _chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 166 struct pcmcia_mem_handle *); 167 static void _chip_mem_free(pcmcia_chipset_handle_t, 168 struct pcmcia_mem_handle *); 169 static int _chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_mem_handle *, 171 bus_addr_t *, int *); 172 static void _chip_mem_unmap(pcmcia_chipset_handle_t, int); 173 static int _chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 174 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 175 static void _chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 176 static int _chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 177 bus_size_t, struct pcmcia_io_handle *, int *); 178 static void _chip_io_unmap(pcmcia_chipset_handle_t, int); 179 static void _chip_socket_enable(pcmcia_chipset_handle_t); 180 static void _chip_socket_disable(pcmcia_chipset_handle_t); 181 static void *_chip_intr_establish(pcmcia_chipset_handle_t, 182 struct pcmcia_function *, int, 183 int (*)(void *), void *); 184 static void _chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 185 186 static struct pcmcia_chip_functions hd64461pcmcia_functions = { 187 _chip_mem_alloc, 188 _chip_mem_free, 189 _chip_mem_map, 190 _chip_mem_unmap, 191 _chip_io_alloc, 192 _chip_io_free, 193 _chip_io_map, 194 _chip_io_unmap, 195 _chip_intr_establish, 196 _chip_intr_disestablish, 197 _chip_socket_enable, 198 _chip_socket_disable, 199 }; 200 201 static int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 202 static void hd64461pcmcia_attach(struct device *, struct device *, void *); 203 static int hd64461pcmcia_print(void *, const char *); 204 static int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 205 206 struct cfattach hd64461pcmcia_ca = { 207 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 208 hd64461pcmcia_attach 209 }; 210 211 static void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 212 enum controller_channel); 213 /* hot plug */ 214 static void hd64461pcmcia_create_event_thread(void *); 215 static void hd64461pcmcia_event_thread(void *); 216 static void queue_event(struct hd64461pcmcia_channel *, 217 enum hd64461pcmcia_event_type); 218 /* interrupt handler */ 219 static int hd64461pcmcia_channel0_intr(void *); 220 static int hd64461pcmcia_channel1_intr(void *); 221 /* card status */ 222 static enum hd64461pcmcia_event_type detect_card(enum controller_channel); 223 static void power_off(enum controller_channel); 224 static void power_on(enum controller_channel); 225 /* memory window access ops */ 226 static void memory_window_mode(enum controller_channel, 227 enum memory_window_mode); 228 static void memory_window_16(enum controller_channel, enum memory_window_16); 229 static void memory_window_32(enum controller_channel, enum memory_window_32) 230 __attribute__((__unused__)); 231 #ifdef DEBUG 232 static void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 233 #endif 234 #define __delay(x) delay((x) * 100) //XXX 235 236 static int 237 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 238 { 239 struct hd64461_attach_args *ha = aux; 240 241 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 242 } 243 244 static void 245 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 246 { 247 struct hd64461_attach_args *ha = aux; 248 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 249 250 sc->sc_module_id = ha->ha_module_id; 251 252 printf("\n"); 253 254 #ifdef DEBUG 255 if (bootverbose) 256 hd64461pcmcia_info(sc); 257 #endif 258 /* Channel 0/1 common CSC event queue */ 259 SIMPLEQ_INIT (&sc->sc_event_head); 260 kthread_create(hd64461pcmcia_create_event_thread, sc); 261 262 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 263 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 264 } 265 266 static void 267 hd64461pcmcia_create_event_thread(void *arg) 268 { 269 struct hd64461pcmcia_softc *sc = arg; 270 int error; 271 272 error = kthread_create1(hd64461pcmcia_event_thread, sc, 273 &sc->sc_event_thread, "%s", 274 sc->sc_dev.dv_xname); 275 KASSERT(error == 0); 276 } 277 278 static void 279 hd64461pcmcia_event_thread(void *arg) 280 { 281 struct hd64461pcmcia_softc *sc = arg; 282 struct hd64461pcmcia_event *pe; 283 int s; 284 285 while (!sc->sc_shutdown) { 286 tsleep(sc, PWAIT, "CSC wait", 0); 287 s = splhigh(); 288 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 289 splx(s); 290 switch (pe->pe_type) { 291 default: 292 printf("%s: unknown event.\n", __FUNCTION__); 293 break; 294 case EVENT_INSERT: 295 DPRINTF("insert event.\n"); 296 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 297 break; 298 case EVENT_REMOVE: 299 DPRINTF("remove event.\n"); 300 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 301 DETACH_FORCE); 302 break; 303 } 304 s = splhigh(); 305 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 306 pe->__queued = 0; 307 } 308 splx(s); 309 } 310 /* NOTREACHED */ 311 } 312 313 static int 314 hd64461pcmcia_print(void *arg, const char *pnp) 315 { 316 if (pnp) 317 printf("pcmcia at %s", pnp); 318 319 return (UNCONF); 320 } 321 322 static int 323 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 324 { 325 struct pcmciabus_attach_args *paa = aux; 326 327 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 328 329 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 330 } 331 332 static void 333 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 334 enum controller_channel channel) 335 { 336 struct device *parent = (struct device *)sc; 337 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 338 struct pcmciabus_attach_args paa; 339 bus_addr_t membase; 340 int i; 341 342 ch->ch_parent = sc; 343 ch->ch_channel = channel; 344 345 /* 346 * Continuous 16-MB Area Mode 347 */ 348 /* Attibute/Common memory extent */ 349 membase = (channel == CHANNEL_0) 350 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 351 ch->ch_memt = bus_space_create("PCMCIA attribute memory", 352 membase, 0x01000000); /* 16MB */ 353 bus_space_alloc(ch->ch_memt, 0, 0x01000000, 0x01000000, 354 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 355 &ch->ch_memh); 356 357 /* Common memory space extent */ 358 ch->ch_memsize = 0x01000000; 359 for (i = 0; i < MEMWIN_16M_MAX; i++) { 360 ch->ch_cmemt[i] = bus_space_create("PCMCIA common memory", 361 membase + 0x01000000, 362 ch->ch_memsize); 363 } 364 365 /* I/O port extent and interrupt staff */ 366 _chip_socket_disable(ch); /* enable CSC interrupt only */ 367 368 if (channel == CHANNEL_0) { 369 /* real I/O space */ 370 ch->ch_iobase = 0; 371 ch->ch_iosize = HD64461_PCC0_IOSIZE; 372 ch->ch_iot = bus_space_create("PCMCIA I/O port", 373 HD64461_PCC0_IOBASE, 374 ch->ch_iosize); 375 376 377 hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 378 hd64461pcmcia_channel0_intr, ch); 379 } else { 380 /* Compact Flash memory mapped mode (Common memory space) */ 381 ch->ch_iobase = 0; 382 ch->ch_iosize = 0x10; /* 16byte (dont' use 0x400-0x7ff) */ 383 ch->ch_iot = bus_space_create("PCMCIA memory mapped I/O port", 384 HD64461_PCC1_MEMBASE + 385 0x01000000, ch->ch_iosize); 386 387 hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 388 hd64461pcmcia_channel1_intr, ch); 389 } 390 391 paa.paa_busname = "pcmcia"; 392 paa.pch = (pcmcia_chipset_handle_t)ch; 393 paa.iobase = ch->ch_iobase; 394 paa.iosize = ch->ch_iosize; 395 396 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 397 hd64461pcmcia_submatch); 398 399 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 400 ch->ch_attached = 1; 401 pcmcia_card_attach(ch->ch_pcmcia); 402 } 403 } 404 405 static int 406 hd64461pcmcia_channel0_intr(void *arg) 407 { 408 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 409 u_int8_t r; 410 int ret = 0; 411 412 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 413 /* clear interrtupt (edge source only) */ 414 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 415 416 if (r & HD64461_PCC0CSCR_P0IREQ) { 417 if (ch->ch_ih_card_func) 418 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 419 else 420 DPRINTF("spurious IREQ interrupt.\n"); 421 } 422 423 if (r & HD64461_PCC0CSCR_P0CDC) 424 queue_event(ch, detect_card(ch->ch_channel)); 425 426 return ret; 427 } 428 429 static int 430 hd64461pcmcia_channel1_intr(void *arg) 431 { 432 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 433 u_int8_t r; 434 int ret = 0; 435 436 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 437 /* clear interrtupt */ 438 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 439 440 if (r & HD64461_PCC1CSCR_P1RC) { 441 if (ch->ch_ih_card_func) 442 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 443 else 444 DPRINTF("spurious READY interrupt.\n"); 445 } 446 447 if (r & HD64461_PCC1CSCR_P1CDC) 448 queue_event(ch, detect_card(ch->ch_channel)); 449 450 return ret; 451 } 452 453 static void 454 queue_event(struct hd64461pcmcia_channel *ch, 455 enum hd64461pcmcia_event_type type) 456 { 457 struct hd64461pcmcia_event *pe, *pool; 458 struct hd64461pcmcia_softc *sc = ch->ch_parent; 459 int i; 460 int s = splhigh(); 461 462 if (type == EVENT_NONE) 463 goto out; 464 465 pe = 0; 466 pool = sc->sc_event_pool; 467 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 468 if (!pool[i].__queued) { 469 pe = &pool[i]; 470 break; 471 } 472 } 473 474 if (pe == 0) { 475 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 476 EVENT_QUEUE_MAX); 477 goto out; 478 } 479 480 if ((ch->ch_attached && (type == EVENT_INSERT)) || 481 (!ch->ch_attached && (type == EVENT_REMOVE))) { 482 DPRINTF("spurious CSC interrupt.\n"); 483 goto out; 484 } 485 486 ch->ch_attached = (type == EVENT_INSERT); 487 pe->__queued = 1; 488 pe->pe_type = type; 489 pe->pe_ch = ch; 490 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 491 wakeup(sc); 492 out: 493 splx(s); 494 } 495 496 /* 497 * interface for pcmcia driver. 498 */ 499 static void * 500 _chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, 501 int ipl, int (*ih_func)(void *), void *ih_arg) 502 { 503 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 504 int channel = ch->ch_channel; 505 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 506 int s = splhigh(); 507 u_int8_t r; 508 509 ch->ch_ih_card_func = ih_func; 510 ch->ch_ih_card_arg = ih_arg; 511 512 /* enable card interrupt */ 513 r = hd64461_reg_read_1(cscier); 514 if (channel == CHANNEL_0) { 515 /* set level mode */ 516 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 517 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 518 } else { 519 /* READY-pin LOW to HIGH changes generates interrupt */ 520 r |= HD64461_PCC1CSCIER_P1RE; 521 } 522 hd64461_reg_write_1(cscier, r); 523 524 splx(s); 525 526 return (void *)ih_func; 527 } 528 529 static void 530 _chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 531 { 532 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 533 int channel = ch->ch_channel; 534 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 535 int s = splhigh(); 536 u_int8_t r; 537 538 /* disable card interrupt */ 539 r = hd64461_reg_read_1(cscier); 540 if (channel == CHANNEL_0) { 541 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 542 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 543 } else { 544 r &= ~HD64461_PCC1CSCIER_P1RE; 545 } 546 hd64461_reg_write_1(cscier, r); 547 548 ch->ch_ih_card_func = 0; 549 550 splx(s); 551 } 552 553 static int 554 _chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 555 struct pcmcia_mem_handle *pcmhp) 556 { 557 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 558 559 pcmhp->memt = ch->ch_memt; 560 pcmhp->addr = ch->ch_membase_addr; 561 pcmhp->memh = ch->ch_memh; 562 pcmhp->size = size; 563 pcmhp->realsize = size; 564 565 return (0); 566 } 567 568 static void 569 _chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 570 { 571 /* nothing to do */ 572 } 573 574 static int 575 _chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, 576 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 577 bus_addr_t *offsetp, int *windowp) 578 { 579 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 580 struct hd64461pcmcia_window_cookie *cookie; 581 582 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 583 M_DEVBUF, M_NOWAIT); 584 KASSERT(cookie); 585 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 586 587 if (kind == PCMCIA_MEM_ATTR) { 588 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 589 size, &cookie->wc_handle) != 0) 590 goto bad; 591 592 *offsetp = card_addr; 593 cookie->wc_window = -1; 594 } else { 595 int window = card_addr / ch->ch_memsize; 596 KASSERT(window < MEMWIN_16M_MAX); 597 598 *offsetp = card_addr - window * ch->ch_memsize; 599 600 if (bus_space_map(ch->ch_cmemt[window], *offsetp, size, 0, 601 &cookie->wc_handle) != 0) 602 goto bad; 603 604 // XXX bogus. bus_space_tag should be vtbl... 605 memory_window_16(ch->ch_channel, window); 606 cookie->wc_window = window; 607 } 608 cookie->wc_size = size; 609 *windowp = (int)cookie; 610 611 DPRINTF("%#lx-> %#lx+%#lx\n", card_addr, *offsetp, size); 612 613 return (0); 614 bad: 615 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 616 free(cookie, M_DEVBUF); 617 618 return (1); 619 } 620 621 static void 622 _chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 623 { 624 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 625 626 if (cookie->wc_window != -1) 627 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 628 cookie->wc_size); 629 free(cookie, M_DEVBUF); 630 } 631 632 static int 633 _chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, 634 bus_size_t align, struct pcmcia_io_handle *pcihp) 635 { 636 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 637 638 if (start) { 639 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 640 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 641 return (1); 642 } 643 DPRINTF("map %#lx+%#lx\n", start, size); 644 } else { 645 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 646 ch->ch_iobase + ch->ch_iosize, 647 size, align, 0, 0, &pcihp->addr, 648 &pcihp->ioh)) { 649 DPRINTF("couldn't allocate %#lx\n", size); 650 return (1); 651 } 652 pcihp->flags = PCMCIA_IO_ALLOCATED; 653 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 654 } 655 656 pcihp->iot = ch->ch_iot; 657 pcihp->size = size; 658 659 return (0); 660 } 661 662 static int 663 _chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 664 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 665 { 666 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 667 #ifdef HD64461PCMCIA_DEBUG 668 static char *width_names[] = { "auto", "io8", "io16" }; 669 #endif 670 u_int16_t r16; 671 672 /* Set bus width */ 673 r16 = SHREG_BCR2; 674 if (ch->ch_channel == CHANNEL_0) { 675 r16 &= ~((1 << 13)|(1 << 12)); 676 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 677 } else { 678 r16 &= ~((1 << 11)|(1 << 10)); 679 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 680 } 681 SHREG_BCR2 = r16; 682 683 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 684 width_names[width]); 685 686 return (0); 687 } 688 689 static void 690 _chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 691 { 692 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 693 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 694 else 695 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 696 697 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 698 } 699 700 static void 701 _chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 702 { 703 /* nothing to do */ 704 } 705 706 static void 707 _chip_socket_enable(pcmcia_chipset_handle_t pch) 708 { 709 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 710 int channel = ch->ch_channel; 711 bus_addr_t isr, gcr; 712 u_int8_t r; 713 int cardtype; 714 int i; 715 716 DPRINTF("enable channel %d\n", channel); 717 isr = HD64461_PCCISR(channel); 718 gcr = HD64461_PCCGCR(channel); 719 720 power_off(channel); 721 power_on(channel); 722 723 /* assert reset */ 724 r = hd64461_reg_read_1(gcr); 725 r |= HD64461_PCCGCR_PCCR; 726 hd64461_reg_write_1(gcr, r); 727 728 /* 729 * hold RESET at least 10us. 730 */ 731 __delay(20); 732 733 /* clear the reset flag */ 734 r &= ~HD64461_PCCGCR_PCCR; 735 hd64461_reg_write_1(gcr, r); 736 __delay(20000); 737 738 /* wait for the chip to finish initializing */ 739 for (i = 0; i < 10000; i++) { 740 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 741 goto reset_ok; 742 __delay(500); 743 744 if ((i > 5000) && (i % 100 == 99)) 745 printf("."); 746 } 747 printf("reset failed.\n"); 748 power_off(channel); 749 return; 750 reset_ok: 751 752 /* set Continuous 16-MB Area Mode */ 753 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 754 memory_window_mode(channel, ch->ch_memory_window_mode); 755 756 /* 757 * set Common memory area. 758 */ 759 memory_window_16(channel, MEMWIN_16M_COMMON_0); 760 761 /* set the card type */ 762 if (channel == CHANNEL_0) { 763 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 764 r = hd64461_reg_read_1(gcr); 765 if (cardtype == PCMCIA_IFTYPE_IO) 766 r |= HD64461_PCC0GCR_P0PCCT; 767 else 768 r &= ~HD64461_PCC0GCR_P0PCCT; 769 hd64461_reg_write_1(gcr, r); 770 } 771 772 773 DPRINTF("OK.\n"); 774 } 775 776 static void 777 _chip_socket_disable(pcmcia_chipset_handle_t pch) 778 { 779 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 780 int channel = ch->ch_channel; 781 782 /* dont' disable CSC interrupt */ 783 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 784 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 785 786 /* power down the socket */ 787 power_off(channel); 788 } 789 790 /* 791 * Card detect 792 */ 793 static void 794 power_off(enum controller_channel channel) 795 { 796 u_int8_t r; 797 u_int16_t r16; 798 bus_addr_t scr, gcr; 799 800 gcr = HD64461_PCCGCR(channel); 801 scr = HD64461_PCCSCR(channel); 802 803 /* DRV (external buffer) high level */ 804 r = hd64461_reg_read_1(gcr); 805 r &= ~HD64461_PCCGCR_DRVE; 806 hd64461_reg_write_1(gcr, r); 807 808 /* stop power */ 809 r = hd64461_reg_read_1(scr); 810 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 811 hd64461_reg_write_1(scr, r); 812 r = hd64461_reg_read_1(gcr); 813 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 814 hd64461_reg_write_1(gcr, r); 815 /* 816 * wait 300ms until power fails (Tpf). Then, wait 100ms since 817 * we are changing Vcc (Toff). 818 */ 819 __delay(300 + 100); 820 821 /* stop clock */ 822 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 823 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 824 HD64461_SYSSTBCR_SPC1ST); 825 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 826 827 if (channel == CHANNEL_0) { 828 /* GPIO Port A XXX Jonanada690 specific? */ 829 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 830 r16 |= 0xf; 831 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 832 } 833 } 834 835 static void 836 power_on(enum controller_channel channel) 837 { 838 u_int8_t r; 839 u_int16_t r16; 840 bus_addr_t scr, gcr, isr; 841 842 isr = HD64461_PCCISR(channel); 843 gcr = HD64461_PCCGCR(channel); 844 scr = HD64461_PCCSCR(channel); 845 846 if (channel == CHANNEL_0) { 847 /* GPIO Port A XXX Jonanada690 specific? */ 848 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 849 r16 &= ~0xf; 850 r16 |= 0x5; 851 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 852 } 853 854 /* supply clock */ 855 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 856 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 857 HD64461_SYSSTBCR_SPC1ST); 858 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 859 __delay(2000); 860 861 /* detect voltage and supply VCC */ 862 r = hd64461_reg_read_1(isr); 863 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 864 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): 865 DPRINTF("5V card\n"); 866 r = hd64461_reg_read_1(gcr); 867 r &= ~HD64461_PCCGCR_VCC0; 868 hd64461_reg_write_1(gcr, r); 869 r = hd64461_reg_read_1(scr); 870 r &= ~HD64461_PCCSCR_VCC1; 871 hd64461_reg_write_1(scr, r); 872 break; 873 case HD64461_PCCISR_VS2: 874 DPRINTF("3.3V card\n"); 875 if (channel == CHANNEL_1) { 876 r = hd64461_reg_read_1(gcr); 877 r &= ~HD64461_PCCGCR_VCC0; 878 hd64461_reg_write_1(gcr, r); 879 } 880 r = hd64461_reg_read_1(scr); 881 r &= ~HD64461_PCCSCR_VCC1; 882 hd64461_reg_write_1(scr, r); 883 break; 884 default: 885 printf("\nunknown Voltage. don't attach.\n"); 886 return; 887 } 888 /* 889 * wait 100ms until power raise (Tpr) and 20ms to become 890 * stable (Tsu(Vcc)). 891 * 892 * some machines require some more time to be settled 893 * (300ms is added here). 894 */ 895 __delay(100 + 20 + 300); 896 897 /* DRV (external buffer) low level */ 898 r = hd64461_reg_read_1(gcr); 899 r |= HD64461_PCCGCR_DRVE; 900 hd64461_reg_write_1(gcr, r); 901 902 /* clear interrupt */ 903 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 904 HD64461_PCC1CSCR_REG8, 0); 905 } 906 907 static enum hd64461pcmcia_event_type 908 detect_card(enum controller_channel channel) 909 { 910 u_int8_t r; 911 912 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 913 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 914 915 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 916 DPRINTF("remove\n"); 917 return EVENT_REMOVE; 918 } 919 if (r == 0) { 920 DPRINTF("insert\n"); 921 return EVENT_INSERT; 922 } 923 DPRINTF("transition\n"); 924 925 return EVENT_NONE; 926 } 927 928 /* 929 * Memory window access ops. 930 */ 931 static void 932 memory_window_mode(enum controller_channel channel, 933 enum memory_window_mode mode) 934 { 935 bus_addr_t a = HD64461_PCCGCR(channel); 936 u_int8_t r = hd64461_reg_read_1(a); 937 938 r &= ~HD64461_PCCGCR_MMOD; 939 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 940 HD64461_PCCGCR_MMOD_32M; 941 hd64461_reg_write_1(a, r); 942 } 943 944 static void 945 memory_window_16(enum controller_channel channel, enum memory_window_16 window) 946 { 947 bus_addr_t a = HD64461_PCCGCR(channel); 948 u_int8_t r; 949 950 r = hd64461_reg_read_1(a); 951 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 952 953 switch (window) { 954 case MEMWIN_16M_COMMON_0: 955 break; 956 case MEMWIN_16M_COMMON_1: 957 r |= HD64461_PCCGCR_PA24; 958 break; 959 case MEMWIN_16M_COMMON_2: 960 r |= HD64461_PCCGCR_PA25; 961 break; 962 case MEMWIN_16M_COMMON_3: 963 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 964 break; 965 } 966 967 hd64461_reg_write_1(a, r); 968 } 969 970 static void 971 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 972 { 973 bus_addr_t a = HD64461_PCCGCR(channel); 974 u_int8_t r; 975 976 r = hd64461_reg_read_1(a); 977 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 978 979 switch (window) { 980 case MEMWIN_32M_ATTR: 981 break; 982 case MEMWIN_32M_COMMON_0: 983 r |= HD64461_PCCGCR_PREG; 984 break; 985 case MEMWIN_32M_COMMON_1: 986 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 987 break; 988 } 989 990 hd64461_reg_write_1(a, r); 991 } 992 993 #ifdef DEBUG 994 static void 995 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 996 { 997 const char name[] = __FUNCTION__; 998 u_int8_t r8; 999 1000 dbg_banner_start(name, sizeof name); 1001 /* 1002 * PCC0 1003 */ 1004 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1005 printf("PCC0 Interface Status Register\n"); 1006 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1007 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 1008 DBG_BIT_PRINT(r8, P0READY); 1009 DBG_BIT_PRINT(r8, P0MWP); 1010 DBG_BIT_PRINT(r8, P0VS2); 1011 DBG_BIT_PRINT(r8, P0VS1); 1012 DBG_BIT_PRINT(r8, P0CD2); 1013 DBG_BIT_PRINT(r8, P0CD1); 1014 DBG_BIT_PRINT(r8, P0BVD2); 1015 DBG_BIT_PRINT(r8, P0BVD1); 1016 #undef DBG_BIT_PRINT 1017 printf("\n"); 1018 1019 printf("PCC0 General Control Register\n"); 1020 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1021 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 1022 DBG_BIT_PRINT(r8, P0DRVE); 1023 DBG_BIT_PRINT(r8, P0PCCR); 1024 DBG_BIT_PRINT(r8, P0PCCT); 1025 DBG_BIT_PRINT(r8, P0VCC0); 1026 DBG_BIT_PRINT(r8, P0MMOD); 1027 DBG_BIT_PRINT(r8, P0PA25); 1028 DBG_BIT_PRINT(r8, P0PA24); 1029 DBG_BIT_PRINT(r8, P0REG); 1030 #undef DBG_BIT_PRINT 1031 printf("\n"); 1032 1033 printf("PCC0 Card Status Change Register\n"); 1034 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1035 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 1036 DBG_BIT_PRINT(r8, P0SCDI); 1037 DBG_BIT_PRINT(r8, P0IREQ); 1038 DBG_BIT_PRINT(r8, P0SC); 1039 DBG_BIT_PRINT(r8, P0CDC); 1040 DBG_BIT_PRINT(r8, P0RC); 1041 DBG_BIT_PRINT(r8, P0BW); 1042 DBG_BIT_PRINT(r8, P0BD); 1043 #undef DBG_BIT_PRINT 1044 printf("\n"); 1045 1046 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1047 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1048 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 1049 DBG_BIT_PRINT(r8, P0CRE); 1050 DBG_BIT_PRINT(r8, P0SCE); 1051 DBG_BIT_PRINT(r8, P0CDE); 1052 DBG_BIT_PRINT(r8, P0RE); 1053 DBG_BIT_PRINT(r8, P0BWE); 1054 DBG_BIT_PRINT(r8, P0BDE); 1055 #undef DBG_BIT_PRINT 1056 printf("\ninterrupt type: "); 1057 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1058 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1059 printf("none\n"); 1060 break; 1061 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1062 printf("level\n"); 1063 break; 1064 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1065 printf("falling edge\n"); 1066 break; 1067 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1068 printf("rising edge\n"); 1069 break; 1070 } 1071 1072 printf("PCC0 Software Control Register\n"); 1073 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1074 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 1075 DBG_BIT_PRINT(r8, P0VCC1); 1076 DBG_BIT_PRINT(r8, P0SWP); 1077 #undef DBG_BIT_PRINT 1078 printf("\n"); 1079 1080 /* 1081 * PCC1 1082 */ 1083 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1084 printf("PCC1 Interface Status Register\n"); 1085 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1086 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 1087 DBG_BIT_PRINT(r8, P1READY); 1088 DBG_BIT_PRINT(r8, P1MWP); 1089 DBG_BIT_PRINT(r8, P1VS2); 1090 DBG_BIT_PRINT(r8, P1VS1); 1091 DBG_BIT_PRINT(r8, P1CD2); 1092 DBG_BIT_PRINT(r8, P1CD1); 1093 DBG_BIT_PRINT(r8, P1BVD2); 1094 DBG_BIT_PRINT(r8, P1BVD1); 1095 #undef DBG_BIT_PRINT 1096 printf("\n"); 1097 1098 printf("PCC1 General Contorol Register\n"); 1099 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1100 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 1101 DBG_BIT_PRINT(r8, P1DRVE); 1102 DBG_BIT_PRINT(r8, P1PCCR); 1103 DBG_BIT_PRINT(r8, P1VCC0); 1104 DBG_BIT_PRINT(r8, P1MMOD); 1105 DBG_BIT_PRINT(r8, P1PA25); 1106 DBG_BIT_PRINT(r8, P1PA24); 1107 DBG_BIT_PRINT(r8, P1REG); 1108 #undef DBG_BIT_PRINT 1109 printf("\n"); 1110 1111 printf("PCC1 Card Status Change Register\n"); 1112 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1113 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 1114 DBG_BIT_PRINT(r8, P1SCDI); 1115 DBG_BIT_PRINT(r8, P1CDC); 1116 DBG_BIT_PRINT(r8, P1RC); 1117 DBG_BIT_PRINT(r8, P1BW); 1118 DBG_BIT_PRINT(r8, P1BD); 1119 #undef DBG_BIT_PRINT 1120 printf("\n"); 1121 1122 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1123 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1124 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 1125 DBG_BIT_PRINT(r8, P1CRE); 1126 DBG_BIT_PRINT(r8, P1CDE); 1127 DBG_BIT_PRINT(r8, P1RE); 1128 DBG_BIT_PRINT(r8, P1BWE); 1129 DBG_BIT_PRINT(r8, P1BDE); 1130 #undef DBG_BIT_PRINT 1131 printf("\n"); 1132 1133 printf("PCC1 Software Control Register\n"); 1134 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1135 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 1136 DBG_BIT_PRINT(r8, P1VCC1); 1137 DBG_BIT_PRINT(r8, P1SWP); 1138 #undef DBG_BIT_PRINT 1139 printf("\n"); 1140 1141 /* 1142 * General Control 1143 */ 1144 printf("[General Control]\n"); 1145 printf("PCC0 Output pins Control Register\n"); 1146 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1147 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 1148 DBG_BIT_PRINT(r8, P0DEPLUP); 1149 DBG_BIT_PRINT(r8, P0AEPLUP); 1150 #undef DBG_BIT_PRINT 1151 printf("\n"); 1152 1153 printf("PCC1 Output pins Control Register\n"); 1154 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1155 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 1156 DBG_BIT_PRINT(r8, P1RST8MA); 1157 DBG_BIT_PRINT(r8, P1RST4MA); 1158 DBG_BIT_PRINT(r8, P1RAS8MA); 1159 DBG_BIT_PRINT(r8, P1RAS4MA); 1160 #undef DBG_BIT_PRINT 1161 printf("\n"); 1162 1163 printf("PC Card General Control Register\n"); 1164 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1165 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 1166 DBG_BIT_PRINT(r8, PSSDIR); 1167 DBG_BIT_PRINT(r8, PSSRDWR); 1168 #undef DBG_BIT_PRINT 1169 printf("\n"); 1170 1171 dbg_banner_end(); 1172 } 1173 #endif /* DEBUG */ 1174 1175
Indexes created Thu Oct 02 01:09:59 GMT 2025