hd64461pcmcia.c revision 1.12
1 /* $NetBSD: hd64461pcmcia.c,v 1.12 2002/02/17 21:01:17 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "debug_hpcsh.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/kthread.h> 46 #include <sys/boot_flag.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/cpufunc.h> 56 57 #include <hpcsh/dev/hd64461/hd64461reg.h> 58 #include <hpcsh/dev/hd64461/hd64461var.h> 59 #include <hpcsh/dev/hd64461/hd64461intcvar.h> 60 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 61 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 62 63 #include "locators.h" 64 65 #ifdef HD64461PCMCIA_DEBUG 66 #define DPRINTF_ENABLE 67 #define DPRINTF_DEBUG hd64461pcmcia_debug 68 #endif 69 #include <machine/debug.h> 70 71 enum controller_channel { 72 CHANNEL_0 = 0, 73 CHANNEL_1 = 1, 74 CHANNEL_MAX = 2 75 }; 76 77 enum memory_window_mode { 78 MEMWIN_16M_MODE, 79 MEMWIN_32M_MODE 80 }; 81 82 enum memory_window_16 { 83 MEMWIN_16M_COMMON_0, 84 MEMWIN_16M_COMMON_1, 85 MEMWIN_16M_COMMON_2, 86 MEMWIN_16M_COMMON_3, 87 }; 88 #define MEMWIN_16M_MAX 4 89 90 enum memory_window_32 { 91 MEMWIN_32M_ATTR, 92 MEMWIN_32M_COMMON_0, 93 MEMWIN_32M_COMMON_1, 94 }; 95 #define MEMWIN_32M_MAX 3 96 97 enum hd64461pcmcia_event_type { 98 EVENT_NONE, 99 EVENT_INSERT, 100 EVENT_REMOVE, 101 }; 102 #define EVENT_QUEUE_MAX 5 103 104 struct hd64461pcmcia_softc; /* forward declaration */ 105 106 struct hd64461pcmcia_window_cookie { 107 bus_space_tag_t wc_tag; 108 bus_space_handle_t wc_handle; 109 int wc_size; 110 int wc_window; 111 }; 112 113 struct hd64461pcmcia_channel { 114 struct hd64461pcmcia_softc *ch_parent; 115 struct device *ch_pcmcia; 116 enum controller_channel ch_channel; 117 118 /* memory space */ 119 enum memory_window_mode ch_memory_window_mode; 120 bus_space_tag_t ch_memt; 121 bus_space_handle_t ch_memh; 122 bus_addr_t ch_membase_addr; 123 bus_size_t ch_memsize; 124 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 125 126 /* I/O space */ 127 bus_space_tag_t ch_iot; 128 bus_addr_t ch_iobase; 129 bus_size_t ch_iosize; 130 131 /* card interrupt */ 132 int (*ch_ih_card_func)(void *); 133 void *ch_ih_card_arg; 134 int ch_attached; 135 }; 136 137 struct hd64461pcmcia_event { 138 int __queued; 139 enum hd64461pcmcia_event_type pe_type; 140 struct hd64461pcmcia_channel *pe_ch; 141 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 142 }; 143 144 struct hd64461pcmcia_softc { 145 struct device sc_dev; 146 enum hd64461_module_id sc_module_id; 147 int sc_shutdown; 148 149 /* CSC event */ 150 struct proc *sc_event_thread; 151 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 152 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 153 154 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 155 }; 156 157 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 158 struct pcmcia_mem_handle *); 159 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 160 struct pcmcia_mem_handle *); 161 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 162 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 163 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 164 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 165 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 166 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 167 struct pcmcia_io_handle *); 168 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_io_handle *, int *); 170 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 171 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 172 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 173 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 174 struct pcmcia_function *, int, int (*)(void *), void *); 175 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 176 void *); 177 178 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 179 hd64461pcmcia_chip_mem_alloc, 180 hd64461pcmcia_chip_mem_free, 181 hd64461pcmcia_chip_mem_map, 182 hd64461pcmcia_chip_mem_unmap, 183 hd64461pcmcia_chip_io_alloc, 184 hd64461pcmcia_chip_io_free, 185 hd64461pcmcia_chip_io_map, 186 hd64461pcmcia_chip_io_unmap, 187 hd64461pcmcia_chip_intr_establish, 188 hd64461pcmcia_chip_intr_disestablish, 189 hd64461pcmcia_chip_socket_enable, 190 hd64461pcmcia_chip_socket_disable, 191 }; 192 193 STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 194 STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 195 STATIC int hd64461pcmcia_print(void *, const char *); 196 STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 197 198 struct cfattach hd64461pcmcia_ca = { 199 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 200 hd64461pcmcia_attach 201 }; 202 203 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 204 enum controller_channel); 205 /* hot plug */ 206 STATIC void hd64461pcmcia_create_event_thread(void *); 207 STATIC void hd64461pcmcia_event_thread(void *); 208 STATIC void queue_event(struct hd64461pcmcia_channel *, 209 enum hd64461pcmcia_event_type); 210 /* interrupt handler */ 211 STATIC int hd64461pcmcia_channel0_intr(void *); 212 STATIC int hd64461pcmcia_channel1_intr(void *); 213 /* card status */ 214 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 215 STATIC void hd64461pcmcia_power_off(enum controller_channel) 216 __attribute__((__unused__)); 217 STATIC void hd64461pcmcia_power_on(enum controller_channel) 218 __attribute__((__unused__)); 219 /* memory window access ops */ 220 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 221 enum memory_window_mode)__attribute__((__unused__)); 222 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 223 enum memory_window_16); 224 /* bus width */ 225 STATIC void hd64461_set_bus_width(enum controller_channel, int); 226 #ifdef HD64461PCMCIA_DEBUG 227 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 228 #endif 229 /* fix SH3 Area[56] bug */ 230 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 231 #define _BUS_SPACE_ACCESS_HOOK() \ 232 do { \ 233 u_int8_t dummy __attribute__((__unused__)) = \ 234 *(volatile u_int8_t *)0xba000000; \ 235 } while (/*CONSTCOND*/0) 236 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 237 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 238 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 239 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 240 #undef _BUS_SPACE_ACCESS_HOOK 241 242 #define DELAY_MS(x) delay((x) * 1000) 243 244 int 245 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 246 { 247 struct hd64461_attach_args *ha = aux; 248 249 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 250 } 251 252 void 253 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 254 { 255 struct hd64461_attach_args *ha = aux; 256 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 257 258 sc->sc_module_id = ha->ha_module_id; 259 260 printf("\n"); 261 262 #ifdef HD64461PCMCIA_DEBUG 263 hd64461pcmcia_info(sc); 264 #endif 265 /* Channel 0/1 common CSC event queue */ 266 SIMPLEQ_INIT (&sc->sc_event_head); 267 kthread_create(hd64461pcmcia_create_event_thread, sc); 268 269 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 270 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 271 } 272 273 void 274 hd64461pcmcia_create_event_thread(void *arg) 275 { 276 struct hd64461pcmcia_softc *sc = arg; 277 int error; 278 279 error = kthread_create1(hd64461pcmcia_event_thread, sc, 280 &sc->sc_event_thread, "%s", 281 sc->sc_dev.dv_xname); 282 KASSERT(error == 0); 283 } 284 285 void 286 hd64461pcmcia_event_thread(void *arg) 287 { 288 struct hd64461pcmcia_softc *sc = arg; 289 struct hd64461pcmcia_event *pe; 290 int s; 291 292 while (!sc->sc_shutdown) { 293 tsleep(sc, PWAIT, "CSC wait", 0); 294 s = splhigh(); 295 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 296 splx(s); 297 switch (pe->pe_type) { 298 default: 299 printf("%s: unknown event.\n", __FUNCTION__); 300 break; 301 case EVENT_INSERT: 302 DPRINTF("insert event.\n"); 303 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 304 break; 305 case EVENT_REMOVE: 306 DPRINTF("remove event.\n"); 307 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 308 DETACH_FORCE); 309 break; 310 } 311 s = splhigh(); 312 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 313 pe->__queued = 0; 314 } 315 splx(s); 316 } 317 /* NOTREACHED */ 318 } 319 320 int 321 hd64461pcmcia_print(void *arg, const char *pnp) 322 { 323 324 if (pnp) 325 printf("pcmcia at %s", pnp); 326 327 return (UNCONF); 328 } 329 330 int 331 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 332 { 333 struct pcmciabus_attach_args *paa = aux; 334 struct hd64461pcmcia_channel *ch = 335 (struct hd64461pcmcia_channel *)paa->pch; 336 337 if (ch->ch_channel == CHANNEL_0) { 338 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 339 PCMCIABUSCF_CONTROLLER_DEFAULT && 340 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 341 return 0; 342 } else { 343 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 344 PCMCIABUSCF_CONTROLLER_DEFAULT && 345 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 346 return 0; 347 } 348 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 349 350 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 351 } 352 353 void 354 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 355 enum controller_channel channel) 356 { 357 struct device *parent = (struct device *)sc; 358 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 359 struct pcmciabus_attach_args paa; 360 bus_addr_t membase; 361 int i; 362 363 ch->ch_parent = sc; 364 ch->ch_channel = channel; 365 366 /* 367 * Continuous 16-MB Area Mode 368 */ 369 /* Attibute/Common memory extent */ 370 membase = (channel == CHANNEL_0) 371 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 372 373 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 374 membase, 0x01000000); /* 16MB */ 375 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 376 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 377 &ch->ch_memh); 378 fixup_sh3_pcmcia_area(ch->ch_memt); 379 380 /* Common memory space extent */ 381 ch->ch_memsize = 0x01000000; 382 for (i = 0; i < MEMWIN_16M_MAX; i++) { 383 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 384 membase + 0x01000000, 385 ch->ch_memsize); 386 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 387 } 388 389 /* I/O port extent and interrupt staff */ 390 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 391 392 if (channel == CHANNEL_0) { 393 ch->ch_iobase = 0; 394 ch->ch_iosize = HD64461_PCC0_IOSIZE; 395 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 396 HD64461_PCC0_IOBASE, 397 ch->ch_iosize); 398 fixup_sh3_pcmcia_area(ch->ch_iot); 399 400 hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 401 hd64461pcmcia_channel0_intr, ch); 402 } else { 403 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 404 hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 405 hd64461pcmcia_channel1_intr, ch); 406 } 407 408 paa.paa_busname = "pcmcia"; 409 paa.pch = (pcmcia_chipset_handle_t)ch; 410 paa.iobase = ch->ch_iobase; 411 paa.iosize = ch->ch_iosize; 412 413 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 414 hd64461pcmcia_submatch); 415 416 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 417 ch->ch_attached = 1; 418 pcmcia_card_attach(ch->ch_pcmcia); 419 } 420 } 421 422 int 423 hd64461pcmcia_channel0_intr(void *arg) 424 { 425 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 426 u_int8_t r; 427 int ret = 0; 428 429 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 430 /* clear interrtupt (edge source only) */ 431 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 432 433 if (r & HD64461_PCC0CSCR_P0IREQ) { 434 if (ch->ch_ih_card_func) { 435 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 436 } else 437 DPRINTF("spurious IREQ interrupt.\n"); 438 } 439 440 if (r & HD64461_PCC0CSCR_P0CDC) 441 queue_event(ch, detect_card(ch->ch_channel)); 442 443 return ret; 444 } 445 446 int 447 hd64461pcmcia_channel1_intr(void *arg) 448 { 449 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 450 u_int8_t r; 451 int ret = 0; 452 453 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 454 /* clear interrtupt */ 455 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 456 457 if (r & HD64461_PCC1CSCR_P1RC) { 458 if (ch->ch_ih_card_func) 459 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 460 else 461 DPRINTF("spurious READY interrupt.\n"); 462 } 463 464 if (r & HD64461_PCC1CSCR_P1CDC) 465 queue_event(ch, detect_card(ch->ch_channel)); 466 467 return ret; 468 } 469 470 void 471 queue_event(struct hd64461pcmcia_channel *ch, 472 enum hd64461pcmcia_event_type type) 473 { 474 struct hd64461pcmcia_event *pe, *pool; 475 struct hd64461pcmcia_softc *sc = ch->ch_parent; 476 int i; 477 int s = splhigh(); 478 479 if (type == EVENT_NONE) 480 goto out; 481 482 pe = 0; 483 pool = sc->sc_event_pool; 484 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 485 if (!pool[i].__queued) { 486 pe = &pool[i]; 487 break; 488 } 489 } 490 491 if (pe == 0) { 492 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 493 EVENT_QUEUE_MAX); 494 goto out; 495 } 496 497 if ((ch->ch_attached && (type == EVENT_INSERT)) || 498 (!ch->ch_attached && (type == EVENT_REMOVE))) { 499 DPRINTF("spurious CSC interrupt.\n"); 500 goto out; 501 } 502 503 ch->ch_attached = (type == EVENT_INSERT); 504 pe->__queued = 1; 505 pe->pe_type = type; 506 pe->pe_ch = ch; 507 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 508 wakeup(sc); 509 out: 510 splx(s); 511 } 512 513 /* 514 * interface for pcmcia driver. 515 */ 516 void * 517 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 518 struct pcmcia_function *pf, 519 int ipl, int (*ih_func)(void *), void *ih_arg) 520 { 521 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 522 int channel = ch->ch_channel; 523 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 524 int s = splhigh(); 525 u_int8_t r; 526 527 ch->ch_ih_card_func = ih_func; 528 ch->ch_ih_card_arg = ih_arg; 529 530 /* enable card interrupt */ 531 r = hd64461_reg_read_1(cscier); 532 if (channel == CHANNEL_0) { 533 /* set level mode */ 534 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 535 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 536 } else { 537 /* READY-pin LOW to HIGH changes generates interrupt */ 538 r |= HD64461_PCC1CSCIER_P1RE; 539 } 540 hd64461_reg_write_1(cscier, r); 541 542 splx(s); 543 544 return (void *)ih_func; 545 } 546 547 void 548 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 549 { 550 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 551 int channel = ch->ch_channel; 552 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 553 int s = splhigh(); 554 u_int8_t r; 555 556 /* disable card interrupt */ 557 r = hd64461_reg_read_1(cscier); 558 if (channel == CHANNEL_0) { 559 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 560 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 561 } else { 562 r &= ~HD64461_PCC1CSCIER_P1RE; 563 } 564 hd64461_reg_write_1(cscier, r); 565 566 ch->ch_ih_card_func = 0; 567 568 splx(s); 569 } 570 571 int 572 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 573 struct pcmcia_mem_handle *pcmhp) 574 { 575 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 576 577 pcmhp->memt = ch->ch_memt; 578 pcmhp->addr = ch->ch_membase_addr; 579 pcmhp->memh = ch->ch_memh; 580 pcmhp->size = size; 581 pcmhp->realsize = size; 582 583 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 584 585 return (0); 586 } 587 588 void 589 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 590 struct pcmcia_mem_handle *pcmhp) 591 { 592 /* nothing to do */ 593 } 594 595 int 596 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 597 bus_addr_t card_addr, 598 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 599 bus_size_t *offsetp, int *windowp) 600 { 601 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 602 struct hd64461pcmcia_window_cookie *cookie; 603 bus_addr_t ofs; 604 605 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 606 M_DEVBUF, M_NOWAIT); 607 KASSERT(cookie); 608 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 609 610 /* Address */ 611 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 612 cookie->wc_tag = ch->ch_memt; 613 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 614 size, &cookie->wc_handle) != 0) 615 goto bad; 616 617 *offsetp = card_addr; 618 cookie->wc_window = -1; 619 } else { 620 int window = card_addr / ch->ch_memsize; 621 KASSERT(window < MEMWIN_16M_MAX); 622 623 cookie->wc_tag = ch->ch_cmemt[window]; 624 ofs = card_addr - window * ch->ch_memsize; 625 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 626 &cookie->wc_handle) != 0) 627 goto bad; 628 629 /* XXX bogus. check window per common memory access. */ 630 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 631 *offsetp = ofs + 0x01000000; /* skip attribute area */ 632 cookie->wc_window = window; 633 } 634 cookie->wc_size = size; 635 *windowp = (int)cookie; 636 637 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 638 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 639 size); 640 641 return (0); 642 bad: 643 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 644 free(cookie, M_DEVBUF); 645 646 return (1); 647 } 648 649 void 650 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 651 { 652 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 653 654 if (cookie->wc_window != -1) 655 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 656 cookie->wc_size); 657 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 658 free(cookie, M_DEVBUF); 659 } 660 661 int 662 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 663 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 664 { 665 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 666 667 if (ch->ch_channel == CHANNEL_1) 668 return (1); 669 670 if (start) { 671 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 672 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 673 return (1); 674 } 675 DPRINTF("map %#lx+%#lx\n", start, size); 676 } else { 677 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 678 ch->ch_iobase + ch->ch_iosize - 1, 679 size, align, 0, 0, &pcihp->addr, 680 &pcihp->ioh)) { 681 DPRINTF("couldn't allocate %#lx\n", size); 682 return (1); 683 } 684 pcihp->flags = PCMCIA_IO_ALLOCATED; 685 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 686 } 687 688 pcihp->iot = ch->ch_iot; 689 pcihp->size = size; 690 691 return (0); 692 } 693 694 int 695 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 696 bus_addr_t offset, 697 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 698 { 699 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 700 #ifdef HD64461PCMCIA_DEBUG 701 static char *width_names[] = { "auto", "io8", "io16" }; 702 #endif 703 if (ch->ch_channel == CHANNEL_1) 704 return (1); 705 706 hd64461_set_bus_width(CHANNEL_0, width); 707 708 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 709 width_names[width]); 710 711 return (0); 712 } 713 714 void 715 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 716 struct pcmcia_io_handle *pcihp) 717 { 718 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 719 720 if (ch->ch_channel == CHANNEL_1) 721 return; 722 723 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 724 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 725 else 726 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 727 728 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 729 } 730 731 void 732 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 733 { 734 /* nothing to do */ 735 } 736 737 void 738 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 739 { 740 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 741 int channel = ch->ch_channel; 742 bus_addr_t isr, gcr; 743 u_int8_t r; 744 int cardtype; 745 746 DPRINTF("enable channel %d\n", channel); 747 isr = HD64461_PCCISR(channel); 748 gcr = HD64461_PCCGCR(channel); 749 750 hd64461pcmcia_power_off(channel); 751 hd64461pcmcia_power_on(channel); 752 #if notyet 753 { 754 int i; 755 /* assert reset */ 756 r = hd64461_reg_read_1(gcr); 757 r |= HD64461_PCCGCR_PCCR; 758 hd64461_reg_write_1(gcr, r); 759 760 /* 761 * hold RESET at least 10us. 762 */ 763 DELAY_MS(20); 764 765 /* clear the reset flag */ 766 r &= ~HD64461_PCCGCR_PCCR; 767 hd64461_reg_write_1(gcr, r); 768 DELAY_MS(2000); 769 770 /* wait for the chip to finish initializing */ 771 for (i = 0; i < 10000; i++) { 772 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 773 goto reset_ok; 774 DELAY_MS(500); 775 776 if ((i > 5000) && (i % 100 == 99)) 777 printf("."); 778 } 779 printf("reset failed.\n"); 780 hd64461pcmcia_power_off(channel); 781 return; 782 reset_ok: 783 } 784 #endif /* notyet */ 785 /* set Continuous 16-MB Area Mode */ 786 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 787 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 788 789 /* 790 * set Common memory area. 791 */ 792 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 793 794 /* set the card type */ 795 r = hd64461_reg_read_1(gcr); 796 if (channel == CHANNEL_0) { 797 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 798 if (cardtype == PCMCIA_IFTYPE_IO) 799 r |= HD64461_PCC0GCR_P0PCCT; 800 else 801 r &= ~HD64461_PCC0GCR_P0PCCT; 802 } else { 803 /* reserved bit must be 0 */ 804 r &= ~HD64461_PCC1GCR_RESERVED; 805 } 806 hd64461_reg_write_1(gcr, r); 807 808 DPRINTF("OK.\n"); 809 } 810 811 void 812 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 813 { 814 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 815 int channel = ch->ch_channel; 816 817 /* dont' disable CSC interrupt */ 818 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 819 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 820 821 /* power down the socket */ 822 hd64461pcmcia_power_off(channel); 823 } 824 825 /* 826 * Card detect 827 */ 828 void 829 hd64461pcmcia_power_off(enum controller_channel channel) 830 { 831 #if notyet 832 u_int8_t r; 833 u_int16_t r16; 834 bus_addr_t scr, gcr; 835 836 gcr = HD64461_PCCGCR(channel); 837 scr = HD64461_PCCSCR(channel); 838 839 /* DRV (external buffer) high level */ 840 r = hd64461_reg_read_1(gcr); 841 r &= ~HD64461_PCCGCR_DRVE; 842 hd64461_reg_write_1(gcr, r); 843 844 /* stop power */ 845 r = hd64461_reg_read_1(scr); 846 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 847 hd64461_reg_write_1(scr, r); 848 r = hd64461_reg_read_1(gcr); 849 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 850 hd64461_reg_write_1(gcr, r); 851 /* 852 * wait 300ms until power fails (Tpf). Then, wait 100ms since 853 * we are changing Vcc (Toff). 854 */ 855 DELAY_MS(300 + 100); 856 857 /* stop clock */ 858 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 859 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 860 HD64461_SYSSTBCR_SPC1ST); 861 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 862 863 if (channel == CHANNEL_0) { 864 /* GPIO Port A XXX Jornada690 specific? */ 865 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 866 r16 |= 0xf; 867 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 868 } 869 870 #endif /* notyet */ 871 } 872 873 void 874 hd64461pcmcia_power_on(enum controller_channel channel) 875 { 876 u_int8_t r; 877 u_int16_t r16; 878 bus_addr_t scr, gcr, isr; 879 880 isr = HD64461_PCCISR(channel); 881 gcr = HD64461_PCCGCR(channel); 882 scr = HD64461_PCCSCR(channel); 883 884 /* 885 * XXX to access attribute memory, this is required. 886 */ 887 if (channel == CHANNEL_0) { 888 /* GPIO Port A XXX Jonanada690 specific? */ 889 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 890 r16 &= ~0xf; 891 r16 |= 0x5; 892 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 893 } 894 895 if (channel == CHANNEL_1) { 896 /* GPIO Port C, Port D XXX HP620LX specific? */ 897 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 898 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 899 } 900 901 /* supply clock */ 902 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 903 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 904 HD64461_SYSSTBCR_SPC1ST); 905 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 906 DELAY_MS(200); 907 908 /* detect voltage and supply VCC */ 909 r = hd64461_reg_read_1(isr); 910 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 911 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 912 DPRINTF("5V card\n"); 913 r = hd64461_reg_read_1(gcr); 914 r &= ~HD64461_PCCGCR_VCC0; 915 hd64461_reg_write_1(gcr, r); 916 r = hd64461_reg_read_1(scr); 917 r &= ~HD64461_PCCSCR_VCC1; 918 hd64461_reg_write_1(scr, r); 919 break; 920 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 921 /* FALLTHROUGH */ 922 case 0: /* x.x / 3.3 / 5 V */ 923 DPRINTF("3.3V card\n"); 924 if (channel == CHANNEL_1) { 925 r = hd64461_reg_read_1(gcr); 926 r &= ~HD64461_PCCGCR_VCC0; 927 hd64461_reg_write_1(gcr, r); 928 } else { 929 r = hd64461_reg_read_1(gcr); 930 r |= HD64461_PCCGCR_VCC0; 931 hd64461_reg_write_1(gcr, r); 932 } 933 r = hd64461_reg_read_1(scr); 934 r &= ~HD64461_PCCSCR_VCC1; 935 hd64461_reg_write_1(scr, r); 936 break; 937 case HD64461_PCCISR_VS1: /* x.x V */ 938 /* FALLTHROUGH */ 939 printf("x.x V not supported.\n"); 940 return; 941 default: 942 printf("\nunknown Voltage. don't attach.\n"); 943 return; 944 } 945 /* 946 * wait 100ms until power raise (Tpr) and 20ms to become 947 * stable (Tsu(Vcc)). 948 * 949 * some machines require some more time to be settled 950 * (300ms is added here). 951 */ 952 DELAY_MS(100 + 20 + 300); 953 954 /* DRV (external buffer) low level */ 955 r = hd64461_reg_read_1(gcr); 956 r |= HD64461_PCCGCR_DRVE; 957 hd64461_reg_write_1(gcr, r); 958 959 /* clear interrupt */ 960 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 961 HD64461_PCC1CSCR_REG8, 0); 962 } 963 964 enum hd64461pcmcia_event_type 965 detect_card(enum controller_channel channel) 966 { 967 u_int8_t r; 968 969 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 970 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 971 972 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 973 DPRINTF("remove\n"); 974 return EVENT_REMOVE; 975 } 976 if (r == 0) { 977 DPRINTF("insert\n"); 978 return EVENT_INSERT; 979 } 980 DPRINTF("transition\n"); 981 982 return EVENT_NONE; 983 } 984 985 /* 986 * Memory window access ops. 987 */ 988 void 989 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 990 enum memory_window_mode mode) 991 { 992 bus_addr_t a = HD64461_PCCGCR(channel); 993 u_int8_t r = hd64461_reg_read_1(a); 994 995 r &= ~HD64461_PCCGCR_MMOD; 996 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 997 HD64461_PCCGCR_MMOD_32M; 998 hd64461_reg_write_1(a, r); 999 } 1000 1001 void 1002 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1003 enum memory_window_16 window) 1004 { 1005 bus_addr_t a = HD64461_PCCGCR(channel); 1006 u_int8_t r; 1007 1008 r = hd64461_reg_read_1(a); 1009 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1010 1011 switch (window) { 1012 case MEMWIN_16M_COMMON_0: 1013 break; 1014 case MEMWIN_16M_COMMON_1: 1015 r |= HD64461_PCCGCR_PA24; 1016 break; 1017 case MEMWIN_16M_COMMON_2: 1018 r |= HD64461_PCCGCR_PA25; 1019 break; 1020 case MEMWIN_16M_COMMON_3: 1021 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1022 break; 1023 } 1024 1025 hd64461_reg_write_1(a, r); 1026 } 1027 1028 #if unused 1029 void 1030 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1031 { 1032 bus_addr_t a = HD64461_PCCGCR(channel); 1033 u_int8_t r; 1034 1035 r = hd64461_reg_read_1(a); 1036 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1037 1038 switch (window) { 1039 case MEMWIN_32M_ATTR: 1040 break; 1041 case MEMWIN_32M_COMMON_0: 1042 r |= HD64461_PCCGCR_PREG; 1043 break; 1044 case MEMWIN_32M_COMMON_1: 1045 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1046 break; 1047 } 1048 1049 hd64461_reg_write_1(a, r); 1050 } 1051 #endif 1052 1053 void 1054 hd64461_set_bus_width(enum controller_channel channel, int width) 1055 { 1056 #define SH3_BCR2 0xffffff62 1057 u_int16_t r16; 1058 1059 r16 = _reg_read_2(SH3_BCR2); 1060 if (channel == CHANNEL_0) { 1061 r16 &= ~((1 << 13)|(1 << 12)); 1062 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1063 } else { 1064 r16 &= ~((1 << 11)|(1 << 10)); 1065 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1066 } 1067 _reg_write_2(SH3_BCR2, r16); 1068 } 1069 1070 void 1071 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1072 { 1073 struct hpcsh_bus_space *hbs = (void *)t; 1074 1075 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1076 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1077 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1078 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1079 } 1080 1081 #ifdef HD64461PCMCIA_DEBUG 1082 void 1083 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1084 { 1085 u_int8_t r8; 1086 1087 dbg_banner_function(); 1088 /* 1089 * PCC0 1090 */ 1091 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1092 printf("PCC0 Interface Status Register\n"); 1093 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1094 1095 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1096 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1097 _(P0BVD2);_(P0BVD1); 1098 #undef _ 1099 printf("\n"); 1100 1101 printf("PCC0 General Control Register\n"); 1102 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1103 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1104 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1105 _(P0PA25);_(P0PA24);_(P0REG); 1106 #undef _ 1107 printf("\n"); 1108 1109 printf("PCC0 Card Status Change Register\n"); 1110 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1111 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1112 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1113 #undef _ 1114 printf("\n"); 1115 1116 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1117 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1118 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1119 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1120 #undef _ 1121 printf("\ninterrupt type: "); 1122 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1123 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1124 printf("none\n"); 1125 break; 1126 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1127 printf("level\n"); 1128 break; 1129 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1130 printf("falling edge\n"); 1131 break; 1132 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1133 printf("rising edge\n"); 1134 break; 1135 } 1136 1137 printf("PCC0 Software Control Register\n"); 1138 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1139 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1140 _(P0VCC1);_(P0SWP); 1141 #undef _ 1142 printf("\n"); 1143 1144 /* 1145 * PCC1 1146 */ 1147 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1148 printf("PCC1 Interface Status Register\n"); 1149 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1150 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1151 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1152 _(P1BVD2);_(P1BVD1); 1153 #undef _ 1154 printf("\n"); 1155 1156 printf("PCC1 General Contorol Register\n"); 1157 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1158 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1159 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1160 #undef _ 1161 printf("\n"); 1162 1163 printf("PCC1 Card Status Change Register\n"); 1164 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1165 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1166 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1167 #undef _ 1168 printf("\n"); 1169 1170 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1171 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1172 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1173 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1174 #undef _ 1175 printf("\n"); 1176 1177 printf("PCC1 Software Control Register\n"); 1178 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1179 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1180 _(P1VCC1);_(P1SWP); 1181 #undef _ 1182 printf("\n"); 1183 1184 /* 1185 * General Control 1186 */ 1187 printf("[General Control]\n"); 1188 printf("PCC0 Output pins Control Register\n"); 1189 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1190 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1191 _(P0DEPLUP);_(P0AEPLUP); 1192 #undef _ 1193 printf("\n"); 1194 1195 printf("PCC1 Output pins Control Register\n"); 1196 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1197 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1198 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1199 #undef _ 1200 printf("\n"); 1201 1202 printf("PC Card General Control Register\n"); 1203 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1204 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1205 _(PSSDIR);_(PSSRDWR); 1206 #undef _ 1207 printf("\n"); 1208 1209 dbg_banner_line(); 1210 } 1211 #endif /* DEBUG */ 1212
Indexes created Thu Oct 02 01:09:59 GMT 2025