hd64461pcmcia.c revision 1.13
1 /* $NetBSD: hd64461pcmcia.c,v 1.13 2002/02/28 01:57:00 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "debug_hpcsh.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/kthread.h> 46 #include <sys/boot_flag.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/cpufunc.h> 56 #include <sh3/bscreg.h> 57 58 #include <hpcsh/dev/hd64461/hd64461reg.h> 59 #include <hpcsh/dev/hd64461/hd64461var.h> 60 #include <hpcsh/dev/hd64461/hd64461intcvar.h> 61 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 62 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 63 64 #include "locators.h" 65 66 #ifdef HD64461PCMCIA_DEBUG 67 #define DPRINTF_ENABLE 68 #define DPRINTF_DEBUG hd64461pcmcia_debug 69 #endif 70 #include <machine/debug.h> 71 72 enum controller_channel { 73 CHANNEL_0 = 0, 74 CHANNEL_1 = 1, 75 CHANNEL_MAX = 2 76 }; 77 78 enum memory_window_mode { 79 MEMWIN_16M_MODE, 80 MEMWIN_32M_MODE 81 }; 82 83 enum memory_window_16 { 84 MEMWIN_16M_COMMON_0, 85 MEMWIN_16M_COMMON_1, 86 MEMWIN_16M_COMMON_2, 87 MEMWIN_16M_COMMON_3, 88 }; 89 #define MEMWIN_16M_MAX 4 90 91 enum memory_window_32 { 92 MEMWIN_32M_ATTR, 93 MEMWIN_32M_COMMON_0, 94 MEMWIN_32M_COMMON_1, 95 }; 96 #define MEMWIN_32M_MAX 3 97 98 enum hd64461pcmcia_event_type { 99 EVENT_NONE, 100 EVENT_INSERT, 101 EVENT_REMOVE, 102 }; 103 #define EVENT_QUEUE_MAX 5 104 105 struct hd64461pcmcia_softc; /* forward declaration */ 106 107 struct hd64461pcmcia_window_cookie { 108 bus_space_tag_t wc_tag; 109 bus_space_handle_t wc_handle; 110 int wc_size; 111 int wc_window; 112 }; 113 114 struct hd64461pcmcia_channel { 115 struct hd64461pcmcia_softc *ch_parent; 116 struct device *ch_pcmcia; 117 enum controller_channel ch_channel; 118 119 /* memory space */ 120 enum memory_window_mode ch_memory_window_mode; 121 bus_space_tag_t ch_memt; 122 bus_space_handle_t ch_memh; 123 bus_addr_t ch_membase_addr; 124 bus_size_t ch_memsize; 125 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 126 127 /* I/O space */ 128 bus_space_tag_t ch_iot; 129 bus_addr_t ch_iobase; 130 bus_size_t ch_iosize; 131 132 /* card interrupt */ 133 int (*ch_ih_card_func)(void *); 134 void *ch_ih_card_arg; 135 int ch_attached; 136 }; 137 138 struct hd64461pcmcia_event { 139 int __queued; 140 enum hd64461pcmcia_event_type pe_type; 141 struct hd64461pcmcia_channel *pe_ch; 142 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 143 }; 144 145 struct hd64461pcmcia_softc { 146 struct device sc_dev; 147 enum hd64461_module_id sc_module_id; 148 int sc_shutdown; 149 150 /* CSC event */ 151 struct proc *sc_event_thread; 152 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 153 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 154 155 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 156 }; 157 158 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 159 struct pcmcia_mem_handle *); 160 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 161 struct pcmcia_mem_handle *); 162 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 163 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 164 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 165 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 166 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 167 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 168 struct pcmcia_io_handle *); 169 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_io_handle *, int *); 171 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 172 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 }; 193 194 STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 195 STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 196 STATIC int hd64461pcmcia_print(void *, const char *); 197 STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 198 199 struct cfattach hd64461pcmcia_ca = { 200 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 201 hd64461pcmcia_attach 202 }; 203 204 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 205 enum controller_channel); 206 /* hot plug */ 207 STATIC void hd64461pcmcia_create_event_thread(void *); 208 STATIC void hd64461pcmcia_event_thread(void *); 209 STATIC void queue_event(struct hd64461pcmcia_channel *, 210 enum hd64461pcmcia_event_type); 211 /* interrupt handler */ 212 STATIC int hd64461pcmcia_channel0_intr(void *); 213 STATIC int hd64461pcmcia_channel1_intr(void *); 214 /* card status */ 215 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 216 STATIC void hd64461pcmcia_power_off(enum controller_channel) 217 __attribute__((__unused__)); 218 STATIC void hd64461pcmcia_power_on(enum controller_channel) 219 __attribute__((__unused__)); 220 /* memory window access ops */ 221 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 222 enum memory_window_mode)__attribute__((__unused__)); 223 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 224 enum memory_window_16); 225 /* bus width */ 226 STATIC void hd64461_set_bus_width(enum controller_channel, int); 227 #ifdef HD64461PCMCIA_DEBUG 228 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 229 #endif 230 /* fix SH3 Area[56] bug */ 231 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 232 #define _BUS_SPACE_ACCESS_HOOK() \ 233 do { \ 234 u_int8_t dummy __attribute__((__unused__)) = \ 235 *(volatile u_int8_t *)0xba000000; \ 236 } while (/*CONSTCOND*/0) 237 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 238 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 239 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 240 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 241 #undef _BUS_SPACE_ACCESS_HOOK 242 243 #define DELAY_MS(x) delay((x) * 1000) 244 245 int 246 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 247 { 248 struct hd64461_attach_args *ha = aux; 249 250 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 251 } 252 253 void 254 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 255 { 256 struct hd64461_attach_args *ha = aux; 257 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 258 259 sc->sc_module_id = ha->ha_module_id; 260 261 printf("\n"); 262 263 #ifdef HD64461PCMCIA_DEBUG 264 hd64461pcmcia_info(sc); 265 #endif 266 /* Channel 0/1 common CSC event queue */ 267 SIMPLEQ_INIT (&sc->sc_event_head); 268 kthread_create(hd64461pcmcia_create_event_thread, sc); 269 270 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 271 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 272 } 273 274 void 275 hd64461pcmcia_create_event_thread(void *arg) 276 { 277 struct hd64461pcmcia_softc *sc = arg; 278 int error; 279 280 error = kthread_create1(hd64461pcmcia_event_thread, sc, 281 &sc->sc_event_thread, "%s", 282 sc->sc_dev.dv_xname); 283 KASSERT(error == 0); 284 } 285 286 void 287 hd64461pcmcia_event_thread(void *arg) 288 { 289 struct hd64461pcmcia_softc *sc = arg; 290 struct hd64461pcmcia_event *pe; 291 int s; 292 293 while (!sc->sc_shutdown) { 294 tsleep(sc, PWAIT, "CSC wait", 0); 295 s = splhigh(); 296 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 297 splx(s); 298 switch (pe->pe_type) { 299 default: 300 printf("%s: unknown event.\n", __FUNCTION__); 301 break; 302 case EVENT_INSERT: 303 DPRINTF("insert event.\n"); 304 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 305 break; 306 case EVENT_REMOVE: 307 DPRINTF("remove event.\n"); 308 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 309 DETACH_FORCE); 310 break; 311 } 312 s = splhigh(); 313 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 314 pe->__queued = 0; 315 } 316 splx(s); 317 } 318 /* NOTREACHED */ 319 } 320 321 int 322 hd64461pcmcia_print(void *arg, const char *pnp) 323 { 324 325 if (pnp) 326 printf("pcmcia at %s", pnp); 327 328 return (UNCONF); 329 } 330 331 int 332 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 333 { 334 struct pcmciabus_attach_args *paa = aux; 335 struct hd64461pcmcia_channel *ch = 336 (struct hd64461pcmcia_channel *)paa->pch; 337 338 if (ch->ch_channel == CHANNEL_0) { 339 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 340 PCMCIABUSCF_CONTROLLER_DEFAULT && 341 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 342 return 0; 343 } else { 344 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 345 PCMCIABUSCF_CONTROLLER_DEFAULT && 346 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 347 return 0; 348 } 349 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 350 351 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 352 } 353 354 void 355 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 356 enum controller_channel channel) 357 { 358 struct device *parent = (struct device *)sc; 359 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 360 struct pcmciabus_attach_args paa; 361 bus_addr_t membase; 362 int i; 363 364 ch->ch_parent = sc; 365 ch->ch_channel = channel; 366 367 /* 368 * Continuous 16-MB Area Mode 369 */ 370 /* Attibute/Common memory extent */ 371 membase = (channel == CHANNEL_0) 372 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 373 374 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 375 membase, 0x01000000); /* 16MB */ 376 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 377 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 378 &ch->ch_memh); 379 fixup_sh3_pcmcia_area(ch->ch_memt); 380 381 /* Common memory space extent */ 382 ch->ch_memsize = 0x01000000; 383 for (i = 0; i < MEMWIN_16M_MAX; i++) { 384 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 385 membase + 0x01000000, 386 ch->ch_memsize); 387 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 388 } 389 390 /* I/O port extent and interrupt staff */ 391 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 392 393 if (channel == CHANNEL_0) { 394 ch->ch_iobase = 0; 395 ch->ch_iosize = HD64461_PCC0_IOSIZE; 396 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 397 HD64461_PCC0_IOBASE, 398 ch->ch_iosize); 399 fixup_sh3_pcmcia_area(ch->ch_iot); 400 401 hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 402 hd64461pcmcia_channel0_intr, ch); 403 } else { 404 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 405 hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 406 hd64461pcmcia_channel1_intr, ch); 407 } 408 409 paa.paa_busname = "pcmcia"; 410 paa.pch = (pcmcia_chipset_handle_t)ch; 411 paa.iobase = ch->ch_iobase; 412 paa.iosize = ch->ch_iosize; 413 414 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 415 hd64461pcmcia_submatch); 416 417 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 418 ch->ch_attached = 1; 419 pcmcia_card_attach(ch->ch_pcmcia); 420 } 421 } 422 423 int 424 hd64461pcmcia_channel0_intr(void *arg) 425 { 426 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 427 u_int8_t r; 428 int ret = 0; 429 430 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 431 /* clear interrtupt (edge source only) */ 432 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 433 434 if (r & HD64461_PCC0CSCR_P0IREQ) { 435 if (ch->ch_ih_card_func) { 436 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 437 } else 438 DPRINTF("spurious IREQ interrupt.\n"); 439 } 440 441 if (r & HD64461_PCC0CSCR_P0CDC) 442 queue_event(ch, detect_card(ch->ch_channel)); 443 444 return ret; 445 } 446 447 int 448 hd64461pcmcia_channel1_intr(void *arg) 449 { 450 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 451 u_int8_t r; 452 int ret = 0; 453 454 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 455 /* clear interrtupt */ 456 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 457 458 if (r & HD64461_PCC1CSCR_P1RC) { 459 if (ch->ch_ih_card_func) 460 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 461 else 462 DPRINTF("spurious READY interrupt.\n"); 463 } 464 465 if (r & HD64461_PCC1CSCR_P1CDC) 466 queue_event(ch, detect_card(ch->ch_channel)); 467 468 return ret; 469 } 470 471 void 472 queue_event(struct hd64461pcmcia_channel *ch, 473 enum hd64461pcmcia_event_type type) 474 { 475 struct hd64461pcmcia_event *pe, *pool; 476 struct hd64461pcmcia_softc *sc = ch->ch_parent; 477 int i; 478 int s = splhigh(); 479 480 if (type == EVENT_NONE) 481 goto out; 482 483 pe = 0; 484 pool = sc->sc_event_pool; 485 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 486 if (!pool[i].__queued) { 487 pe = &pool[i]; 488 break; 489 } 490 } 491 492 if (pe == 0) { 493 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 494 EVENT_QUEUE_MAX); 495 goto out; 496 } 497 498 if ((ch->ch_attached && (type == EVENT_INSERT)) || 499 (!ch->ch_attached && (type == EVENT_REMOVE))) { 500 DPRINTF("spurious CSC interrupt.\n"); 501 goto out; 502 } 503 504 ch->ch_attached = (type == EVENT_INSERT); 505 pe->__queued = 1; 506 pe->pe_type = type; 507 pe->pe_ch = ch; 508 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 509 wakeup(sc); 510 out: 511 splx(s); 512 } 513 514 /* 515 * interface for pcmcia driver. 516 */ 517 void * 518 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 519 struct pcmcia_function *pf, 520 int ipl, int (*ih_func)(void *), void *ih_arg) 521 { 522 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 523 int channel = ch->ch_channel; 524 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 525 int s = splhigh(); 526 u_int8_t r; 527 528 ch->ch_ih_card_func = ih_func; 529 ch->ch_ih_card_arg = ih_arg; 530 531 /* enable card interrupt */ 532 r = hd64461_reg_read_1(cscier); 533 if (channel == CHANNEL_0) { 534 /* set level mode */ 535 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 536 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 537 } else { 538 /* READY-pin LOW to HIGH changes generates interrupt */ 539 r |= HD64461_PCC1CSCIER_P1RE; 540 } 541 hd64461_reg_write_1(cscier, r); 542 543 splx(s); 544 545 return (void *)ih_func; 546 } 547 548 void 549 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 550 { 551 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 552 int channel = ch->ch_channel; 553 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 554 int s = splhigh(); 555 u_int8_t r; 556 557 /* disable card interrupt */ 558 r = hd64461_reg_read_1(cscier); 559 if (channel == CHANNEL_0) { 560 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 561 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 562 } else { 563 r &= ~HD64461_PCC1CSCIER_P1RE; 564 } 565 hd64461_reg_write_1(cscier, r); 566 567 ch->ch_ih_card_func = 0; 568 569 splx(s); 570 } 571 572 int 573 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 574 struct pcmcia_mem_handle *pcmhp) 575 { 576 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 577 578 pcmhp->memt = ch->ch_memt; 579 pcmhp->addr = ch->ch_membase_addr; 580 pcmhp->memh = ch->ch_memh; 581 pcmhp->size = size; 582 pcmhp->realsize = size; 583 584 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 585 586 return (0); 587 } 588 589 void 590 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 591 struct pcmcia_mem_handle *pcmhp) 592 { 593 /* nothing to do */ 594 } 595 596 int 597 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 598 bus_addr_t card_addr, 599 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 600 bus_size_t *offsetp, int *windowp) 601 { 602 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 603 struct hd64461pcmcia_window_cookie *cookie; 604 bus_addr_t ofs; 605 606 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 607 M_DEVBUF, M_NOWAIT); 608 KASSERT(cookie); 609 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 610 611 /* Address */ 612 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 613 cookie->wc_tag = ch->ch_memt; 614 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 615 size, &cookie->wc_handle) != 0) 616 goto bad; 617 618 *offsetp = card_addr; 619 cookie->wc_window = -1; 620 } else { 621 int window = card_addr / ch->ch_memsize; 622 KASSERT(window < MEMWIN_16M_MAX); 623 624 cookie->wc_tag = ch->ch_cmemt[window]; 625 ofs = card_addr - window * ch->ch_memsize; 626 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 627 &cookie->wc_handle) != 0) 628 goto bad; 629 630 /* XXX bogus. check window per common memory access. */ 631 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 632 *offsetp = ofs + 0x01000000; /* skip attribute area */ 633 cookie->wc_window = window; 634 } 635 cookie->wc_size = size; 636 *windowp = (int)cookie; 637 638 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 639 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 640 size); 641 642 return (0); 643 bad: 644 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 645 free(cookie, M_DEVBUF); 646 647 return (1); 648 } 649 650 void 651 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 652 { 653 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 654 655 if (cookie->wc_window != -1) 656 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 657 cookie->wc_size); 658 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 659 free(cookie, M_DEVBUF); 660 } 661 662 int 663 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 664 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 665 { 666 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 667 668 if (ch->ch_channel == CHANNEL_1) 669 return (1); 670 671 if (start) { 672 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 673 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 674 return (1); 675 } 676 DPRINTF("map %#lx+%#lx\n", start, size); 677 } else { 678 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 679 ch->ch_iobase + ch->ch_iosize - 1, 680 size, align, 0, 0, &pcihp->addr, 681 &pcihp->ioh)) { 682 DPRINTF("couldn't allocate %#lx\n", size); 683 return (1); 684 } 685 pcihp->flags = PCMCIA_IO_ALLOCATED; 686 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 687 } 688 689 pcihp->iot = ch->ch_iot; 690 pcihp->size = size; 691 692 return (0); 693 } 694 695 int 696 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 697 bus_addr_t offset, 698 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 699 { 700 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 701 #ifdef HD64461PCMCIA_DEBUG 702 static char *width_names[] = { "auto", "io8", "io16" }; 703 #endif 704 if (ch->ch_channel == CHANNEL_1) 705 return (1); 706 707 hd64461_set_bus_width(CHANNEL_0, width); 708 709 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 710 width_names[width]); 711 712 return (0); 713 } 714 715 void 716 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 717 struct pcmcia_io_handle *pcihp) 718 { 719 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 720 721 if (ch->ch_channel == CHANNEL_1) 722 return; 723 724 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 725 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 726 else 727 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 728 729 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 730 } 731 732 void 733 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 734 { 735 /* nothing to do */ 736 } 737 738 void 739 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 740 { 741 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 742 int channel = ch->ch_channel; 743 bus_addr_t isr, gcr; 744 u_int8_t r; 745 int cardtype; 746 747 DPRINTF("enable channel %d\n", channel); 748 isr = HD64461_PCCISR(channel); 749 gcr = HD64461_PCCGCR(channel); 750 751 hd64461pcmcia_power_off(channel); 752 hd64461pcmcia_power_on(channel); 753 #if notyet 754 { 755 int i; 756 /* assert reset */ 757 r = hd64461_reg_read_1(gcr); 758 r |= HD64461_PCCGCR_PCCR; 759 hd64461_reg_write_1(gcr, r); 760 761 /* 762 * hold RESET at least 10us. 763 */ 764 DELAY_MS(20); 765 766 /* clear the reset flag */ 767 r &= ~HD64461_PCCGCR_PCCR; 768 hd64461_reg_write_1(gcr, r); 769 DELAY_MS(2000); 770 771 /* wait for the chip to finish initializing */ 772 for (i = 0; i < 10000; i++) { 773 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 774 goto reset_ok; 775 DELAY_MS(500); 776 777 if ((i > 5000) && (i % 100 == 99)) 778 printf("."); 779 } 780 printf("reset failed.\n"); 781 hd64461pcmcia_power_off(channel); 782 return; 783 reset_ok: 784 } 785 #endif /* notyet */ 786 /* set Continuous 16-MB Area Mode */ 787 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 788 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 789 790 /* 791 * set Common memory area. 792 */ 793 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 794 795 /* set the card type */ 796 r = hd64461_reg_read_1(gcr); 797 if (channel == CHANNEL_0) { 798 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 799 if (cardtype == PCMCIA_IFTYPE_IO) 800 r |= HD64461_PCC0GCR_P0PCCT; 801 else 802 r &= ~HD64461_PCC0GCR_P0PCCT; 803 } else { 804 /* reserved bit must be 0 */ 805 r &= ~HD64461_PCC1GCR_RESERVED; 806 } 807 hd64461_reg_write_1(gcr, r); 808 809 DPRINTF("OK.\n"); 810 } 811 812 void 813 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 814 { 815 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 816 int channel = ch->ch_channel; 817 818 /* dont' disable CSC interrupt */ 819 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 820 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 821 822 /* power down the socket */ 823 hd64461pcmcia_power_off(channel); 824 } 825 826 /* 827 * Card detect 828 */ 829 void 830 hd64461pcmcia_power_off(enum controller_channel channel) 831 { 832 #if notyet 833 u_int8_t r; 834 u_int16_t r16; 835 bus_addr_t scr, gcr; 836 837 gcr = HD64461_PCCGCR(channel); 838 scr = HD64461_PCCSCR(channel); 839 840 /* DRV (external buffer) high level */ 841 r = hd64461_reg_read_1(gcr); 842 r &= ~HD64461_PCCGCR_DRVE; 843 hd64461_reg_write_1(gcr, r); 844 845 /* stop power */ 846 r = hd64461_reg_read_1(scr); 847 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 848 hd64461_reg_write_1(scr, r); 849 r = hd64461_reg_read_1(gcr); 850 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 851 hd64461_reg_write_1(gcr, r); 852 /* 853 * wait 300ms until power fails (Tpf). Then, wait 100ms since 854 * we are changing Vcc (Toff). 855 */ 856 DELAY_MS(300 + 100); 857 858 /* stop clock */ 859 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 860 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 861 HD64461_SYSSTBCR_SPC1ST); 862 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 863 864 if (channel == CHANNEL_0) { 865 /* GPIO Port A XXX Jornada690 specific? */ 866 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 867 r16 |= 0xf; 868 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 869 } 870 871 #endif /* notyet */ 872 } 873 874 void 875 hd64461pcmcia_power_on(enum controller_channel channel) 876 { 877 u_int8_t r; 878 u_int16_t r16; 879 bus_addr_t scr, gcr, isr; 880 881 isr = HD64461_PCCISR(channel); 882 gcr = HD64461_PCCGCR(channel); 883 scr = HD64461_PCCSCR(channel); 884 885 /* 886 * XXX to access attribute memory, this is required. 887 */ 888 if (channel == CHANNEL_0) { 889 /* GPIO Port A XXX Jonanada690 specific? */ 890 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 891 r16 &= ~0xf; 892 r16 |= 0x5; 893 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 894 } 895 896 if (channel == CHANNEL_1) { 897 /* GPIO Port C, Port D XXX HP620LX specific? */ 898 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 899 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 900 } 901 902 /* supply clock */ 903 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 904 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 905 HD64461_SYSSTBCR_SPC1ST); 906 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 907 DELAY_MS(200); 908 909 /* detect voltage and supply VCC */ 910 r = hd64461_reg_read_1(isr); 911 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 912 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 913 DPRINTF("5V card\n"); 914 r = hd64461_reg_read_1(gcr); 915 r &= ~HD64461_PCCGCR_VCC0; 916 hd64461_reg_write_1(gcr, r); 917 r = hd64461_reg_read_1(scr); 918 r &= ~HD64461_PCCSCR_VCC1; 919 hd64461_reg_write_1(scr, r); 920 break; 921 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 922 /* FALLTHROUGH */ 923 case 0: /* x.x / 3.3 / 5 V */ 924 DPRINTF("3.3V card\n"); 925 if (channel == CHANNEL_1) { 926 r = hd64461_reg_read_1(gcr); 927 r &= ~HD64461_PCCGCR_VCC0; 928 hd64461_reg_write_1(gcr, r); 929 } else { 930 r = hd64461_reg_read_1(gcr); 931 r |= HD64461_PCCGCR_VCC0; 932 hd64461_reg_write_1(gcr, r); 933 } 934 r = hd64461_reg_read_1(scr); 935 r &= ~HD64461_PCCSCR_VCC1; 936 hd64461_reg_write_1(scr, r); 937 break; 938 case HD64461_PCCISR_VS1: /* x.x V */ 939 /* FALLTHROUGH */ 940 printf("x.x V not supported.\n"); 941 return; 942 default: 943 printf("\nunknown Voltage. don't attach.\n"); 944 return; 945 } 946 /* 947 * wait 100ms until power raise (Tpr) and 20ms to become 948 * stable (Tsu(Vcc)). 949 * 950 * some machines require some more time to be settled 951 * (300ms is added here). 952 */ 953 DELAY_MS(100 + 20 + 300); 954 955 /* DRV (external buffer) low level */ 956 r = hd64461_reg_read_1(gcr); 957 r |= HD64461_PCCGCR_DRVE; 958 hd64461_reg_write_1(gcr, r); 959 960 /* clear interrupt */ 961 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 962 HD64461_PCC1CSCR_REG8, 0); 963 } 964 965 enum hd64461pcmcia_event_type 966 detect_card(enum controller_channel channel) 967 { 968 u_int8_t r; 969 970 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 971 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 972 973 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 974 DPRINTF("remove\n"); 975 return EVENT_REMOVE; 976 } 977 if (r == 0) { 978 DPRINTF("insert\n"); 979 return EVENT_INSERT; 980 } 981 DPRINTF("transition\n"); 982 983 return EVENT_NONE; 984 } 985 986 /* 987 * Memory window access ops. 988 */ 989 void 990 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 991 enum memory_window_mode mode) 992 { 993 bus_addr_t a = HD64461_PCCGCR(channel); 994 u_int8_t r = hd64461_reg_read_1(a); 995 996 r &= ~HD64461_PCCGCR_MMOD; 997 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 998 HD64461_PCCGCR_MMOD_32M; 999 hd64461_reg_write_1(a, r); 1000 } 1001 1002 void 1003 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1004 enum memory_window_16 window) 1005 { 1006 bus_addr_t a = HD64461_PCCGCR(channel); 1007 u_int8_t r; 1008 1009 r = hd64461_reg_read_1(a); 1010 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1011 1012 switch (window) { 1013 case MEMWIN_16M_COMMON_0: 1014 break; 1015 case MEMWIN_16M_COMMON_1: 1016 r |= HD64461_PCCGCR_PA24; 1017 break; 1018 case MEMWIN_16M_COMMON_2: 1019 r |= HD64461_PCCGCR_PA25; 1020 break; 1021 case MEMWIN_16M_COMMON_3: 1022 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1023 break; 1024 } 1025 1026 hd64461_reg_write_1(a, r); 1027 } 1028 1029 #if unused 1030 void 1031 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1032 { 1033 bus_addr_t a = HD64461_PCCGCR(channel); 1034 u_int8_t r; 1035 1036 r = hd64461_reg_read_1(a); 1037 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1038 1039 switch (window) { 1040 case MEMWIN_32M_ATTR: 1041 break; 1042 case MEMWIN_32M_COMMON_0: 1043 r |= HD64461_PCCGCR_PREG; 1044 break; 1045 case MEMWIN_32M_COMMON_1: 1046 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1047 break; 1048 } 1049 1050 hd64461_reg_write_1(a, r); 1051 } 1052 #endif 1053 1054 void 1055 hd64461_set_bus_width(enum controller_channel channel, int width) 1056 { 1057 u_int16_t r16; 1058 1059 r16 = _reg_read_2(SH3_BCR2); 1060 if (channel == CHANNEL_0) { 1061 r16 &= ~((1 << 13)|(1 << 12)); 1062 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1063 } else { 1064 r16 &= ~((1 << 11)|(1 << 10)); 1065 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1066 } 1067 _reg_write_2(SH3_BCR2, r16); 1068 } 1069 1070 void 1071 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1072 { 1073 struct hpcsh_bus_space *hbs = (void *)t; 1074 1075 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1076 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1077 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1078 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1079 } 1080 1081 #ifdef HD64461PCMCIA_DEBUG 1082 void 1083 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1084 { 1085 u_int8_t r8; 1086 1087 dbg_banner_function(); 1088 /* 1089 * PCC0 1090 */ 1091 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1092 printf("PCC0 Interface Status Register\n"); 1093 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1094 1095 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1096 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1097 _(P0BVD2);_(P0BVD1); 1098 #undef _ 1099 printf("\n"); 1100 1101 printf("PCC0 General Control Register\n"); 1102 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1103 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1104 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1105 _(P0PA25);_(P0PA24);_(P0REG); 1106 #undef _ 1107 printf("\n"); 1108 1109 printf("PCC0 Card Status Change Register\n"); 1110 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1111 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1112 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1113 #undef _ 1114 printf("\n"); 1115 1116 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1117 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1118 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1119 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1120 #undef _ 1121 printf("\ninterrupt type: "); 1122 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1123 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1124 printf("none\n"); 1125 break; 1126 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1127 printf("level\n"); 1128 break; 1129 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1130 printf("falling edge\n"); 1131 break; 1132 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1133 printf("rising edge\n"); 1134 break; 1135 } 1136 1137 printf("PCC0 Software Control Register\n"); 1138 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1139 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1140 _(P0VCC1);_(P0SWP); 1141 #undef _ 1142 printf("\n"); 1143 1144 /* 1145 * PCC1 1146 */ 1147 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1148 printf("PCC1 Interface Status Register\n"); 1149 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1150 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1151 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1152 _(P1BVD2);_(P1BVD1); 1153 #undef _ 1154 printf("\n"); 1155 1156 printf("PCC1 General Contorol Register\n"); 1157 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1158 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1159 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1160 #undef _ 1161 printf("\n"); 1162 1163 printf("PCC1 Card Status Change Register\n"); 1164 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1165 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1166 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1167 #undef _ 1168 printf("\n"); 1169 1170 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1171 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1172 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1173 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1174 #undef _ 1175 printf("\n"); 1176 1177 printf("PCC1 Software Control Register\n"); 1178 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1179 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1180 _(P1VCC1);_(P1SWP); 1181 #undef _ 1182 printf("\n"); 1183 1184 /* 1185 * General Control 1186 */ 1187 printf("[General Control]\n"); 1188 printf("PCC0 Output pins Control Register\n"); 1189 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1190 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1191 _(P0DEPLUP);_(P0AEPLUP); 1192 #undef _ 1193 printf("\n"); 1194 1195 printf("PCC1 Output pins Control Register\n"); 1196 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1197 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1198 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1199 #undef _ 1200 printf("\n"); 1201 1202 printf("PC Card General Control Register\n"); 1203 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1204 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1205 _(PSSDIR);_(PSSRDWR); 1206 #undef _ 1207 printf("\n"); 1208 1209 dbg_banner_line(); 1210 } 1211 #endif /* DEBUG */ 1212
Indexes created Thu Oct 02 01:09:59 GMT 2025