hd64461pcmcia.c revision 1.16
1 /* $NetBSD: hd64461pcmcia.c,v 1.16 2002/06/01 23:50:54 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "debug_hpcsh.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/kthread.h> 46 #include <sys/boot_flag.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/bscreg.h> 56 57 #include <hpcsh/dev/hd64461/hd64461reg.h> 58 #include <hpcsh/dev/hd64461/hd64461var.h> 59 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 60 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 61 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 62 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 63 64 #include "locators.h" 65 66 #ifdef HD64461PCMCIA_DEBUG 67 #define DPRINTF_ENABLE 68 #define DPRINTF_DEBUG hd64461pcmcia_debug 69 #endif 70 #include <machine/debug.h> 71 72 enum controller_channel { 73 CHANNEL_0 = 0, 74 CHANNEL_1 = 1, 75 CHANNEL_MAX = 2 76 }; 77 78 enum memory_window_mode { 79 MEMWIN_16M_MODE, 80 MEMWIN_32M_MODE 81 }; 82 83 enum memory_window_16 { 84 MEMWIN_16M_COMMON_0, 85 MEMWIN_16M_COMMON_1, 86 MEMWIN_16M_COMMON_2, 87 MEMWIN_16M_COMMON_3, 88 }; 89 #define MEMWIN_16M_MAX 4 90 91 enum memory_window_32 { 92 MEMWIN_32M_ATTR, 93 MEMWIN_32M_COMMON_0, 94 MEMWIN_32M_COMMON_1, 95 }; 96 #define MEMWIN_32M_MAX 3 97 98 enum hd64461pcmcia_event_type { 99 EVENT_NONE, 100 EVENT_INSERT, 101 EVENT_REMOVE, 102 }; 103 #define EVENT_QUEUE_MAX 5 104 105 struct hd64461pcmcia_softc; /* forward declaration */ 106 107 struct hd64461pcmcia_window_cookie { 108 bus_space_tag_t wc_tag; 109 bus_space_handle_t wc_handle; 110 int wc_size; 111 int wc_window; 112 }; 113 114 struct hd64461pcmcia_channel { 115 struct hd64461pcmcia_softc *ch_parent; 116 struct device *ch_pcmcia; 117 enum controller_channel ch_channel; 118 119 /* memory space */ 120 enum memory_window_mode ch_memory_window_mode; 121 bus_space_tag_t ch_memt; 122 bus_space_handle_t ch_memh; 123 bus_addr_t ch_membase_addr; 124 bus_size_t ch_memsize; 125 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 126 127 /* I/O space */ 128 bus_space_tag_t ch_iot; 129 bus_addr_t ch_iobase; 130 bus_size_t ch_iosize; 131 132 /* card interrupt */ 133 int (*ch_ih_card_func)(void *); 134 void *ch_ih_card_arg; 135 int ch_attached; 136 }; 137 138 struct hd64461pcmcia_event { 139 int __queued; 140 enum hd64461pcmcia_event_type pe_type; 141 struct hd64461pcmcia_channel *pe_ch; 142 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 143 }; 144 145 struct hd64461pcmcia_softc { 146 struct device sc_dev; 147 enum hd64461_module_id sc_module_id; 148 int sc_shutdown; 149 150 /* CSC event */ 151 struct proc *sc_event_thread; 152 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 153 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 154 155 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 156 }; 157 158 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 159 struct pcmcia_mem_handle *); 160 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 161 struct pcmcia_mem_handle *); 162 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 163 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 164 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 165 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 166 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 167 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 168 struct pcmcia_io_handle *); 169 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_io_handle *, int *); 171 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 172 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 }; 193 194 STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 195 STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 196 STATIC int hd64461pcmcia_print(void *, const char *); 197 STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 198 199 struct cfattach hd64461pcmcia_ca = { 200 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 201 hd64461pcmcia_attach 202 }; 203 204 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 205 enum controller_channel); 206 /* hot plug */ 207 STATIC void hd64461pcmcia_create_event_thread(void *); 208 STATIC void hd64461pcmcia_event_thread(void *); 209 STATIC void queue_event(struct hd64461pcmcia_channel *, 210 enum hd64461pcmcia_event_type); 211 /* interrupt handler */ 212 STATIC int hd64461pcmcia_channel0_intr(void *); 213 STATIC int hd64461pcmcia_channel1_intr(void *); 214 /* card status */ 215 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 216 STATIC void hd64461pcmcia_power_off(enum controller_channel) 217 __attribute__((__unused__)); 218 STATIC void hd64461pcmcia_power_on(enum controller_channel) 219 __attribute__((__unused__)); 220 /* memory window access ops */ 221 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 222 enum memory_window_mode)__attribute__((__unused__)); 223 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 224 enum memory_window_16); 225 /* bus width */ 226 STATIC void hd64461_set_bus_width(enum controller_channel, int); 227 #ifdef HD64461PCMCIA_DEBUG 228 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 229 #endif 230 /* fix SH3 Area[56] bug */ 231 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 232 #define _BUS_SPACE_ACCESS_HOOK() \ 233 do { \ 234 u_int8_t dummy __attribute__((__unused__)) = \ 235 *(volatile u_int8_t *)0xba000000; \ 236 } while (/*CONSTCOND*/0) 237 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 238 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 239 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 240 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 241 #undef _BUS_SPACE_ACCESS_HOOK 242 243 #define DELAY_MS(x) delay((x) * 1000) 244 245 int 246 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 247 { 248 struct hd64461_attach_args *ha = aux; 249 250 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 251 } 252 253 void 254 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 255 { 256 struct hd64461_attach_args *ha = aux; 257 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 258 259 sc->sc_module_id = ha->ha_module_id; 260 261 printf("\n"); 262 263 #ifdef HD64461PCMCIA_DEBUG 264 hd64461pcmcia_info(sc); 265 #endif 266 /* Channel 0/1 common CSC event queue */ 267 SIMPLEQ_INIT (&sc->sc_event_head); 268 kthread_create(hd64461pcmcia_create_event_thread, sc); 269 270 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 271 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 272 } 273 274 void 275 hd64461pcmcia_create_event_thread(void *arg) 276 { 277 struct hd64461pcmcia_softc *sc = arg; 278 int error; 279 280 error = kthread_create1(hd64461pcmcia_event_thread, sc, 281 &sc->sc_event_thread, "%s", 282 sc->sc_dev.dv_xname); 283 KASSERT(error == 0); 284 } 285 286 void 287 hd64461pcmcia_event_thread(void *arg) 288 { 289 struct hd64461pcmcia_softc *sc = arg; 290 struct hd64461pcmcia_event *pe; 291 int s; 292 293 while (!sc->sc_shutdown) { 294 tsleep(sc, PWAIT, "CSC wait", 0); 295 s = splhigh(); 296 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 297 splx(s); 298 switch (pe->pe_type) { 299 default: 300 printf("%s: unknown event.\n", __FUNCTION__); 301 break; 302 case EVENT_INSERT: 303 DPRINTF("insert event.\n"); 304 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 305 break; 306 case EVENT_REMOVE: 307 DPRINTF("remove event.\n"); 308 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 309 DETACH_FORCE); 310 break; 311 } 312 s = splhigh(); 313 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 314 pe->__queued = 0; 315 } 316 splx(s); 317 } 318 /* NOTREACHED */ 319 } 320 321 int 322 hd64461pcmcia_print(void *arg, const char *pnp) 323 { 324 325 if (pnp) 326 printf("pcmcia at %s", pnp); 327 328 return (UNCONF); 329 } 330 331 int 332 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 333 { 334 struct pcmciabus_attach_args *paa = aux; 335 struct hd64461pcmcia_channel *ch = 336 (struct hd64461pcmcia_channel *)paa->pch; 337 338 if (ch->ch_channel == CHANNEL_0) { 339 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 340 PCMCIABUSCF_CONTROLLER_DEFAULT && 341 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 342 return 0; 343 } else { 344 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 345 PCMCIABUSCF_CONTROLLER_DEFAULT && 346 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 347 return 0; 348 } 349 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 350 351 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 352 } 353 354 void 355 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 356 enum controller_channel channel) 357 { 358 struct device *parent = (struct device *)sc; 359 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 360 struct pcmciabus_attach_args paa; 361 bus_addr_t membase; 362 int i; 363 364 ch->ch_parent = sc; 365 ch->ch_channel = channel; 366 367 /* 368 * Continuous 16-MB Area Mode 369 */ 370 /* Attibute/Common memory extent */ 371 membase = (channel == CHANNEL_0) 372 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 373 374 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 375 membase, 0x01000000); /* 16MB */ 376 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 377 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 378 &ch->ch_memh); 379 fixup_sh3_pcmcia_area(ch->ch_memt); 380 381 /* Common memory space extent */ 382 ch->ch_memsize = 0x01000000; 383 for (i = 0; i < MEMWIN_16M_MAX; i++) { 384 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 385 membase + 0x01000000, 386 ch->ch_memsize); 387 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 388 } 389 390 /* I/O port extent and interrupt staff */ 391 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 392 393 if (channel == CHANNEL_0) { 394 ch->ch_iobase = 0; 395 ch->ch_iosize = HD64461_PCC0_IOSIZE; 396 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 397 HD64461_PCC0_IOBASE, 398 ch->ch_iosize); 399 fixup_sh3_pcmcia_area(ch->ch_iot); 400 401 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 402 hd64461pcmcia_channel0_intr, ch); 403 } else { 404 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 405 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 406 hd64461pcmcia_channel1_intr, ch); 407 } 408 409 paa.paa_busname = "pcmcia"; 410 paa.pch = (pcmcia_chipset_handle_t)ch; 411 paa.iobase = ch->ch_iobase; 412 paa.iosize = ch->ch_iosize; 413 414 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 415 hd64461pcmcia_submatch); 416 417 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 418 ch->ch_attached = 1; 419 pcmcia_card_attach(ch->ch_pcmcia); 420 } 421 } 422 423 int 424 hd64461pcmcia_channel0_intr(void *arg) 425 { 426 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 427 u_int8_t r; 428 int ret = 0; 429 430 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 431 /* clear interrtupt (edge source only) */ 432 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 433 434 if (r & HD64461_PCC0CSCR_P0IREQ) { 435 if (ch->ch_ih_card_func) { 436 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 437 } else 438 DPRINTF("spurious IREQ interrupt.\n"); 439 } 440 441 if (r & HD64461_PCC0CSCR_P0CDC) 442 queue_event(ch, detect_card(ch->ch_channel)); 443 444 return ret; 445 } 446 447 int 448 hd64461pcmcia_channel1_intr(void *arg) 449 { 450 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 451 u_int8_t r; 452 int ret = 0; 453 454 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 455 /* clear interrtupt */ 456 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 457 458 if (r & HD64461_PCC1CSCR_P1RC) { 459 if (ch->ch_ih_card_func) 460 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 461 else 462 DPRINTF("spurious READY interrupt.\n"); 463 } 464 465 if (r & HD64461_PCC1CSCR_P1CDC) 466 queue_event(ch, detect_card(ch->ch_channel)); 467 468 return ret; 469 } 470 471 void 472 queue_event(struct hd64461pcmcia_channel *ch, 473 enum hd64461pcmcia_event_type type) 474 { 475 struct hd64461pcmcia_event *pe, *pool; 476 struct hd64461pcmcia_softc *sc = ch->ch_parent; 477 int i; 478 int s = splhigh(); 479 480 if (type == EVENT_NONE) 481 goto out; 482 483 pe = 0; 484 pool = sc->sc_event_pool; 485 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 486 if (!pool[i].__queued) { 487 pe = &pool[i]; 488 break; 489 } 490 } 491 492 if (pe == 0) { 493 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 494 EVENT_QUEUE_MAX); 495 goto out; 496 } 497 498 if ((ch->ch_attached && (type == EVENT_INSERT)) || 499 (!ch->ch_attached && (type == EVENT_REMOVE))) { 500 DPRINTF("spurious CSC interrupt.\n"); 501 goto out; 502 } 503 504 ch->ch_attached = (type == EVENT_INSERT); 505 pe->__queued = 1; 506 pe->pe_type = type; 507 pe->pe_ch = ch; 508 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 509 wakeup(sc); 510 out: 511 splx(s); 512 } 513 514 /* 515 * interface for pcmcia driver. 516 */ 517 void * 518 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 519 struct pcmcia_function *pf, 520 int ipl, int (*ih_func)(void *), void *ih_arg) 521 { 522 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 523 int channel = ch->ch_channel; 524 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 525 int s = splhigh(); 526 u_int8_t r; 527 528 ch->ch_ih_card_func = ih_func; 529 ch->ch_ih_card_arg = ih_arg; 530 531 /* enable card interrupt */ 532 r = hd64461_reg_read_1(cscier); 533 if (channel == CHANNEL_0) { 534 /* set level mode */ 535 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 536 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 537 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 538 } else { 539 /* READY-pin LOW to HIGH changes generates interrupt */ 540 r |= HD64461_PCC1CSCIER_P1RE; 541 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 542 } 543 hd64461_reg_write_1(cscier, r); 544 545 splx(s); 546 547 return (void *)ih_func; 548 } 549 550 void 551 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 552 { 553 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 554 int channel = ch->ch_channel; 555 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 556 int s = splhigh(); 557 u_int8_t r; 558 559 /* disable card interrupt */ 560 r = hd64461_reg_read_1(cscier); 561 if (channel == CHANNEL_0) { 562 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 563 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 564 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 565 } else { 566 r &= ~HD64461_PCC1CSCIER_P1RE; 567 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 568 } 569 hd64461_reg_write_1(cscier, r); 570 571 ch->ch_ih_card_func = 0; 572 573 splx(s); 574 } 575 576 int 577 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 578 struct pcmcia_mem_handle *pcmhp) 579 { 580 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 581 582 pcmhp->memt = ch->ch_memt; 583 pcmhp->addr = ch->ch_membase_addr; 584 pcmhp->memh = ch->ch_memh; 585 pcmhp->size = size; 586 pcmhp->realsize = size; 587 588 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 589 590 return (0); 591 } 592 593 void 594 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 595 struct pcmcia_mem_handle *pcmhp) 596 { 597 /* nothing to do */ 598 } 599 600 int 601 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 602 bus_addr_t card_addr, 603 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 604 bus_size_t *offsetp, int *windowp) 605 { 606 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 607 struct hd64461pcmcia_window_cookie *cookie; 608 bus_addr_t ofs; 609 610 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 611 M_DEVBUF, M_NOWAIT); 612 KASSERT(cookie); 613 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 614 615 /* Address */ 616 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 617 cookie->wc_tag = ch->ch_memt; 618 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 619 size, &cookie->wc_handle) != 0) 620 goto bad; 621 622 *offsetp = card_addr; 623 cookie->wc_window = -1; 624 } else { 625 int window = card_addr / ch->ch_memsize; 626 KASSERT(window < MEMWIN_16M_MAX); 627 628 cookie->wc_tag = ch->ch_cmemt[window]; 629 ofs = card_addr - window * ch->ch_memsize; 630 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 631 &cookie->wc_handle) != 0) 632 goto bad; 633 634 /* XXX bogus. check window per common memory access. */ 635 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 636 *offsetp = ofs + 0x01000000; /* skip attribute area */ 637 cookie->wc_window = window; 638 } 639 cookie->wc_size = size; 640 *windowp = (int)cookie; 641 642 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 643 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 644 size); 645 646 return (0); 647 bad: 648 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 649 free(cookie, M_DEVBUF); 650 651 return (1); 652 } 653 654 void 655 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 656 { 657 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 658 659 if (cookie->wc_window != -1) 660 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 661 cookie->wc_size); 662 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 663 free(cookie, M_DEVBUF); 664 } 665 666 int 667 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 668 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 669 { 670 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 671 672 if (ch->ch_channel == CHANNEL_1) 673 return (1); 674 675 if (start) { 676 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 677 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 678 return (1); 679 } 680 DPRINTF("map %#lx+%#lx\n", start, size); 681 } else { 682 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 683 ch->ch_iobase + ch->ch_iosize - 1, 684 size, align, 0, 0, &pcihp->addr, 685 &pcihp->ioh)) { 686 DPRINTF("couldn't allocate %#lx\n", size); 687 return (1); 688 } 689 pcihp->flags = PCMCIA_IO_ALLOCATED; 690 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 691 } 692 693 pcihp->iot = ch->ch_iot; 694 pcihp->size = size; 695 696 return (0); 697 } 698 699 int 700 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 701 bus_addr_t offset, 702 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 703 { 704 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 705 #ifdef HD64461PCMCIA_DEBUG 706 static char *width_names[] = { "auto", "io8", "io16" }; 707 #endif 708 if (ch->ch_channel == CHANNEL_1) 709 return (1); 710 711 hd64461_set_bus_width(CHANNEL_0, width); 712 713 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 714 width_names[width]); 715 716 return (0); 717 } 718 719 void 720 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 721 struct pcmcia_io_handle *pcihp) 722 { 723 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 724 725 if (ch->ch_channel == CHANNEL_1) 726 return; 727 728 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 729 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 730 else 731 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 732 733 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 734 } 735 736 void 737 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 738 { 739 /* nothing to do */ 740 } 741 742 void 743 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 744 { 745 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 746 int channel = ch->ch_channel; 747 bus_addr_t isr, gcr; 748 u_int8_t r; 749 int cardtype; 750 751 DPRINTF("enable channel %d\n", channel); 752 isr = HD64461_PCCISR(channel); 753 gcr = HD64461_PCCGCR(channel); 754 755 hd64461pcmcia_power_off(channel); 756 hd64461pcmcia_power_on(channel); 757 #if notyet 758 { 759 int i; 760 /* assert reset */ 761 r = hd64461_reg_read_1(gcr); 762 r |= HD64461_PCCGCR_PCCR; 763 hd64461_reg_write_1(gcr, r); 764 765 /* 766 * hold RESET at least 10us. 767 */ 768 DELAY_MS(20); 769 770 /* clear the reset flag */ 771 r &= ~HD64461_PCCGCR_PCCR; 772 hd64461_reg_write_1(gcr, r); 773 DELAY_MS(2000); 774 775 /* wait for the chip to finish initializing */ 776 for (i = 0; i < 10000; i++) { 777 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 778 goto reset_ok; 779 DELAY_MS(500); 780 781 if ((i > 5000) && (i % 100 == 99)) 782 printf("."); 783 } 784 printf("reset failed.\n"); 785 hd64461pcmcia_power_off(channel); 786 return; 787 reset_ok: 788 } 789 #endif /* notyet */ 790 /* set Continuous 16-MB Area Mode */ 791 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 792 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 793 794 /* 795 * set Common memory area. 796 */ 797 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 798 799 /* set the card type */ 800 r = hd64461_reg_read_1(gcr); 801 if (channel == CHANNEL_0) { 802 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 803 if (cardtype == PCMCIA_IFTYPE_IO) 804 r |= HD64461_PCC0GCR_P0PCCT; 805 else 806 r &= ~HD64461_PCC0GCR_P0PCCT; 807 } else { 808 /* reserved bit must be 0 */ 809 r &= ~HD64461_PCC1GCR_RESERVED; 810 } 811 hd64461_reg_write_1(gcr, r); 812 813 DPRINTF("OK.\n"); 814 } 815 816 void 817 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 818 { 819 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 820 int channel = ch->ch_channel; 821 822 /* dont' disable CSC interrupt */ 823 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 824 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 825 826 /* power down the socket */ 827 hd64461pcmcia_power_off(channel); 828 } 829 830 /* 831 * Card detect 832 */ 833 void 834 hd64461pcmcia_power_off(enum controller_channel channel) 835 { 836 #if notyet 837 u_int8_t r; 838 u_int16_t r16; 839 bus_addr_t scr, gcr; 840 841 gcr = HD64461_PCCGCR(channel); 842 scr = HD64461_PCCSCR(channel); 843 844 /* DRV (external buffer) high level */ 845 r = hd64461_reg_read_1(gcr); 846 r &= ~HD64461_PCCGCR_DRVE; 847 hd64461_reg_write_1(gcr, r); 848 849 /* stop power */ 850 r = hd64461_reg_read_1(scr); 851 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 852 hd64461_reg_write_1(scr, r); 853 r = hd64461_reg_read_1(gcr); 854 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 855 hd64461_reg_write_1(gcr, r); 856 /* 857 * wait 300ms until power fails (Tpf). Then, wait 100ms since 858 * we are changing Vcc (Toff). 859 */ 860 DELAY_MS(300 + 100); 861 862 /* stop clock */ 863 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 864 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 865 HD64461_SYSSTBCR_SPC1ST); 866 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 867 868 if (channel == CHANNEL_0) { 869 /* GPIO Port A XXX Jornada690 specific? */ 870 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 871 r16 |= 0xf; 872 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 873 } 874 875 #endif /* notyet */ 876 } 877 878 void 879 hd64461pcmcia_power_on(enum controller_channel channel) 880 { 881 u_int8_t r; 882 u_int16_t r16; 883 bus_addr_t scr, gcr, isr; 884 885 isr = HD64461_PCCISR(channel); 886 gcr = HD64461_PCCGCR(channel); 887 scr = HD64461_PCCSCR(channel); 888 889 /* 890 * XXX to access attribute memory, this is required. 891 */ 892 if (channel == CHANNEL_0) { 893 /* GPIO Port A XXX Jonanada690 specific? */ 894 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 895 r16 &= ~0xf; 896 r16 |= 0x5; 897 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 898 } 899 900 if (channel == CHANNEL_1) { 901 /* GPIO Port C, Port D XXX HP620LX specific? */ 902 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 903 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 904 } 905 906 /* supply clock */ 907 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 908 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 909 HD64461_SYSSTBCR_SPC1ST); 910 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 911 DELAY_MS(200); 912 913 /* detect voltage and supply VCC */ 914 r = hd64461_reg_read_1(isr); 915 916 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 917 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 918 DPRINTF("5V card\n"); 919 hd64461pcmcia_power(channel, V_5, 1); 920 break; 921 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 922 /* FALLTHROUGH */ 923 case 0: /* x.x / 3.3 / 5 V */ 924 DPRINTF("3.3V card\n"); 925 hd64461pcmcia_power(channel, V_3_3, 1); 926 break; 927 case HD64461_PCCISR_VS1: /* x.x V */ 928 /* FALLTHROUGH */ 929 DPRINTF("x.x V card\n"); 930 hd64461pcmcia_power(channel, V_X_X, 1); 931 return; 932 default: 933 printf("\nunknown Voltage. don't attach.\n"); 934 return; 935 } 936 937 /* 938 * wait 100ms until power raise (Tpr) and 20ms to become 939 * stable (Tsu(Vcc)). 940 * 941 * some machines require some more time to be settled 942 * (300ms is added here). 943 */ 944 DELAY_MS(100 + 20 + 300); 945 946 /* DRV (external buffer) low level */ 947 r = hd64461_reg_read_1(gcr); 948 r |= HD64461_PCCGCR_DRVE; 949 hd64461_reg_write_1(gcr, r); 950 951 /* clear interrupt */ 952 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 953 HD64461_PCC1CSCR_REG8, 0); 954 } 955 956 enum hd64461pcmcia_event_type 957 detect_card(enum controller_channel channel) 958 { 959 u_int8_t r; 960 961 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 962 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 963 964 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 965 DPRINTF("remove\n"); 966 return EVENT_REMOVE; 967 } 968 if (r == 0) { 969 DPRINTF("insert\n"); 970 return EVENT_INSERT; 971 } 972 DPRINTF("transition\n"); 973 974 return EVENT_NONE; 975 } 976 977 /* 978 * Memory window access ops. 979 */ 980 void 981 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 982 enum memory_window_mode mode) 983 { 984 bus_addr_t a = HD64461_PCCGCR(channel); 985 u_int8_t r = hd64461_reg_read_1(a); 986 987 r &= ~HD64461_PCCGCR_MMOD; 988 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 989 HD64461_PCCGCR_MMOD_32M; 990 hd64461_reg_write_1(a, r); 991 } 992 993 void 994 hd64461pcmcia_memory_window_16(enum controller_channel channel, 995 enum memory_window_16 window) 996 { 997 bus_addr_t a = HD64461_PCCGCR(channel); 998 u_int8_t r; 999 1000 r = hd64461_reg_read_1(a); 1001 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1002 1003 switch (window) { 1004 case MEMWIN_16M_COMMON_0: 1005 break; 1006 case MEMWIN_16M_COMMON_1: 1007 r |= HD64461_PCCGCR_PA24; 1008 break; 1009 case MEMWIN_16M_COMMON_2: 1010 r |= HD64461_PCCGCR_PA25; 1011 break; 1012 case MEMWIN_16M_COMMON_3: 1013 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1014 break; 1015 } 1016 1017 hd64461_reg_write_1(a, r); 1018 } 1019 1020 #if unused 1021 void 1022 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1023 { 1024 bus_addr_t a = HD64461_PCCGCR(channel); 1025 u_int8_t r; 1026 1027 r = hd64461_reg_read_1(a); 1028 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1029 1030 switch (window) { 1031 case MEMWIN_32M_ATTR: 1032 break; 1033 case MEMWIN_32M_COMMON_0: 1034 r |= HD64461_PCCGCR_PREG; 1035 break; 1036 case MEMWIN_32M_COMMON_1: 1037 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1038 break; 1039 } 1040 1041 hd64461_reg_write_1(a, r); 1042 } 1043 #endif 1044 1045 void 1046 hd64461_set_bus_width(enum controller_channel channel, int width) 1047 { 1048 u_int16_t r16; 1049 1050 r16 = _reg_read_2(SH3_BCR2); 1051 if (channel == CHANNEL_0) { 1052 r16 &= ~((1 << 13)|(1 << 12)); 1053 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1054 } else { 1055 r16 &= ~((1 << 11)|(1 << 10)); 1056 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1057 } 1058 _reg_write_2(SH3_BCR2, r16); 1059 } 1060 1061 void 1062 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1063 { 1064 struct hpcsh_bus_space *hbs = (void *)t; 1065 1066 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1067 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1068 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1069 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1070 } 1071 1072 #ifdef HD64461PCMCIA_DEBUG 1073 void 1074 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1075 { 1076 u_int8_t r8; 1077 1078 dbg_banner_function(); 1079 /* 1080 * PCC0 1081 */ 1082 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1083 printf("PCC0 Interface Status Register\n"); 1084 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1085 1086 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1087 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1088 _(P0BVD2);_(P0BVD1); 1089 #undef _ 1090 printf("\n"); 1091 1092 printf("PCC0 General Control Register\n"); 1093 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1094 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1095 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1096 _(P0PA25);_(P0PA24);_(P0REG); 1097 #undef _ 1098 printf("\n"); 1099 1100 printf("PCC0 Card Status Change Register\n"); 1101 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1102 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1103 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1104 #undef _ 1105 printf("\n"); 1106 1107 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1108 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1109 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1110 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1111 #undef _ 1112 printf("\ninterrupt type: "); 1113 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1114 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1115 printf("none\n"); 1116 break; 1117 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1118 printf("level\n"); 1119 break; 1120 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1121 printf("falling edge\n"); 1122 break; 1123 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1124 printf("rising edge\n"); 1125 break; 1126 } 1127 1128 printf("PCC0 Software Control Register\n"); 1129 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1130 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1131 _(P0VCC1);_(P0SWP); 1132 #undef _ 1133 printf("\n"); 1134 1135 /* 1136 * PCC1 1137 */ 1138 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1139 printf("PCC1 Interface Status Register\n"); 1140 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1141 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1142 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1143 _(P1BVD2);_(P1BVD1); 1144 #undef _ 1145 printf("\n"); 1146 1147 printf("PCC1 General Contorol Register\n"); 1148 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1149 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1150 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1151 #undef _ 1152 printf("\n"); 1153 1154 printf("PCC1 Card Status Change Register\n"); 1155 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1156 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1157 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1158 #undef _ 1159 printf("\n"); 1160 1161 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1162 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1163 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1164 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1165 #undef _ 1166 printf("\n"); 1167 1168 printf("PCC1 Software Control Register\n"); 1169 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1170 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1171 _(P1VCC1);_(P1SWP); 1172 #undef _ 1173 printf("\n"); 1174 1175 /* 1176 * General Control 1177 */ 1178 printf("[General Control]\n"); 1179 printf("PCC0 Output pins Control Register\n"); 1180 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1181 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1182 _(P0DEPLUP);_(P0AEPLUP); 1183 #undef _ 1184 printf("\n"); 1185 1186 printf("PCC1 Output pins Control Register\n"); 1187 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1188 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1189 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1190 #undef _ 1191 printf("\n"); 1192 1193 printf("PC Card General Control Register\n"); 1194 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1195 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1196 _(PSSDIR);_(PSSRDWR); 1197 #undef _ 1198 printf("\n"); 1199 1200 dbg_banner_line(); 1201 } 1202 #endif /* HD64461PCMCIA_DEBUG */ 1203
Indexes created Thu Oct 02 01:09:59 GMT 2025