hd64461pcmcia.c revision 1.19
1 /* $NetBSD: hd64461pcmcia.c,v 1.19 2002/10/01 02:59:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "debug_hpcsh.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/kthread.h> 46 #include <sys/boot_flag.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/bscreg.h> 56 57 #include <hpcsh/dev/hd64461/hd64461reg.h> 58 #include <hpcsh/dev/hd64461/hd64461var.h> 59 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 60 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 61 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 62 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 63 64 #include "locators.h" 65 66 #ifdef HD64461PCMCIA_DEBUG 67 #define DPRINTF_ENABLE 68 #define DPRINTF_DEBUG hd64461pcmcia_debug 69 #endif 70 #include <machine/debug.h> 71 72 enum controller_channel { 73 CHANNEL_0 = 0, 74 CHANNEL_1 = 1, 75 CHANNEL_MAX = 2 76 }; 77 78 enum memory_window_mode { 79 MEMWIN_16M_MODE, 80 MEMWIN_32M_MODE 81 }; 82 83 enum memory_window_16 { 84 MEMWIN_16M_COMMON_0, 85 MEMWIN_16M_COMMON_1, 86 MEMWIN_16M_COMMON_2, 87 MEMWIN_16M_COMMON_3, 88 }; 89 #define MEMWIN_16M_MAX 4 90 91 enum memory_window_32 { 92 MEMWIN_32M_ATTR, 93 MEMWIN_32M_COMMON_0, 94 MEMWIN_32M_COMMON_1, 95 }; 96 #define MEMWIN_32M_MAX 3 97 98 enum hd64461pcmcia_event_type { 99 EVENT_NONE, 100 EVENT_INSERT, 101 EVENT_REMOVE, 102 }; 103 #define EVENT_QUEUE_MAX 5 104 105 struct hd64461pcmcia_softc; /* forward declaration */ 106 107 struct hd64461pcmcia_window_cookie { 108 bus_space_tag_t wc_tag; 109 bus_space_handle_t wc_handle; 110 int wc_size; 111 int wc_window; 112 }; 113 114 struct hd64461pcmcia_channel { 115 struct hd64461pcmcia_softc *ch_parent; 116 struct device *ch_pcmcia; 117 enum controller_channel ch_channel; 118 119 /* memory space */ 120 enum memory_window_mode ch_memory_window_mode; 121 bus_space_tag_t ch_memt; 122 bus_space_handle_t ch_memh; 123 bus_addr_t ch_membase_addr; 124 bus_size_t ch_memsize; 125 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 126 127 /* I/O space */ 128 bus_space_tag_t ch_iot; 129 bus_addr_t ch_iobase; 130 bus_size_t ch_iosize; 131 132 /* card interrupt */ 133 int (*ch_ih_card_func)(void *); 134 void *ch_ih_card_arg; 135 int ch_attached; 136 }; 137 138 struct hd64461pcmcia_event { 139 int __queued; 140 enum hd64461pcmcia_event_type pe_type; 141 struct hd64461pcmcia_channel *pe_ch; 142 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 143 }; 144 145 struct hd64461pcmcia_softc { 146 struct device sc_dev; 147 enum hd64461_module_id sc_module_id; 148 int sc_shutdown; 149 150 /* CSC event */ 151 struct proc *sc_event_thread; 152 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 153 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 154 155 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 156 }; 157 158 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 159 struct pcmcia_mem_handle *); 160 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 161 struct pcmcia_mem_handle *); 162 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 163 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 164 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 165 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 166 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 167 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 168 struct pcmcia_io_handle *); 169 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 170 bus_size_t, struct pcmcia_io_handle *, int *); 171 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 172 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 }; 193 194 STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 195 STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 196 STATIC int hd64461pcmcia_print(void *, const char *); 197 STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 198 199 CFATTACH_DECL(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 200 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL) 201 202 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 203 enum controller_channel); 204 /* hot plug */ 205 STATIC void hd64461pcmcia_create_event_thread(void *); 206 STATIC void hd64461pcmcia_event_thread(void *); 207 STATIC void queue_event(struct hd64461pcmcia_channel *, 208 enum hd64461pcmcia_event_type); 209 /* interrupt handler */ 210 STATIC int hd64461pcmcia_channel0_intr(void *); 211 STATIC int hd64461pcmcia_channel1_intr(void *); 212 /* card status */ 213 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 214 STATIC void hd64461pcmcia_power_off(enum controller_channel) 215 __attribute__((__unused__)); 216 STATIC void hd64461pcmcia_power_on(enum controller_channel) 217 __attribute__((__unused__)); 218 /* memory window access ops */ 219 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 220 enum memory_window_mode)__attribute__((__unused__)); 221 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 222 enum memory_window_16); 223 /* bus width */ 224 STATIC void hd64461_set_bus_width(enum controller_channel, int); 225 #ifdef HD64461PCMCIA_DEBUG 226 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 227 #endif 228 /* fix SH3 Area[56] bug */ 229 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 230 #define _BUS_SPACE_ACCESS_HOOK() \ 231 do { \ 232 u_int8_t dummy __attribute__((__unused__)) = \ 233 *(volatile u_int8_t *)0xba000000; \ 234 } while (/*CONSTCOND*/0) 235 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 236 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 237 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 238 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 239 #undef _BUS_SPACE_ACCESS_HOOK 240 241 #define DELAY_MS(x) delay((x) * 1000) 242 243 int 244 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 245 { 246 struct hd64461_attach_args *ha = aux; 247 248 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 249 } 250 251 void 252 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 253 { 254 struct hd64461_attach_args *ha = aux; 255 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 256 257 sc->sc_module_id = ha->ha_module_id; 258 259 printf("\n"); 260 261 #ifdef HD64461PCMCIA_DEBUG 262 hd64461pcmcia_info(sc); 263 #endif 264 /* Channel 0/1 common CSC event queue */ 265 SIMPLEQ_INIT (&sc->sc_event_head); 266 kthread_create(hd64461pcmcia_create_event_thread, sc); 267 268 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 269 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 270 } 271 272 void 273 hd64461pcmcia_create_event_thread(void *arg) 274 { 275 struct hd64461pcmcia_softc *sc = arg; 276 int error; 277 278 error = kthread_create1(hd64461pcmcia_event_thread, sc, 279 &sc->sc_event_thread, "%s", 280 sc->sc_dev.dv_xname); 281 KASSERT(error == 0); 282 } 283 284 void 285 hd64461pcmcia_event_thread(void *arg) 286 { 287 struct hd64461pcmcia_softc *sc = arg; 288 struct hd64461pcmcia_event *pe; 289 int s; 290 291 while (!sc->sc_shutdown) { 292 tsleep(sc, PWAIT, "CSC wait", 0); 293 s = splhigh(); 294 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 295 splx(s); 296 switch (pe->pe_type) { 297 default: 298 printf("%s: unknown event.\n", __FUNCTION__); 299 break; 300 case EVENT_INSERT: 301 DPRINTF("insert event.\n"); 302 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 303 break; 304 case EVENT_REMOVE: 305 DPRINTF("remove event.\n"); 306 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 307 DETACH_FORCE); 308 break; 309 } 310 s = splhigh(); 311 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 312 pe->__queued = 0; 313 } 314 splx(s); 315 } 316 /* NOTREACHED */ 317 } 318 319 int 320 hd64461pcmcia_print(void *arg, const char *pnp) 321 { 322 323 if (pnp) 324 printf("pcmcia at %s", pnp); 325 326 return (UNCONF); 327 } 328 329 int 330 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 331 { 332 struct pcmciabus_attach_args *paa = aux; 333 struct hd64461pcmcia_channel *ch = 334 (struct hd64461pcmcia_channel *)paa->pch; 335 336 if (ch->ch_channel == CHANNEL_0) { 337 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 338 PCMCIABUSCF_CONTROLLER_DEFAULT && 339 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 340 return 0; 341 } else { 342 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 343 PCMCIABUSCF_CONTROLLER_DEFAULT && 344 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 345 return 0; 346 } 347 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 348 349 return (config_match(parent, cf, aux)); 350 } 351 352 void 353 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 354 enum controller_channel channel) 355 { 356 struct device *parent = (struct device *)sc; 357 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 358 struct pcmciabus_attach_args paa; 359 bus_addr_t membase; 360 int i; 361 362 ch->ch_parent = sc; 363 ch->ch_channel = channel; 364 365 /* 366 * Continuous 16-MB Area Mode 367 */ 368 /* Attibute/Common memory extent */ 369 membase = (channel == CHANNEL_0) 370 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 371 372 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 373 membase, 0x01000000); /* 16MB */ 374 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 375 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 376 &ch->ch_memh); 377 fixup_sh3_pcmcia_area(ch->ch_memt); 378 379 /* Common memory space extent */ 380 ch->ch_memsize = 0x01000000; 381 for (i = 0; i < MEMWIN_16M_MAX; i++) { 382 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 383 membase + 0x01000000, 384 ch->ch_memsize); 385 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 386 } 387 388 /* I/O port extent and interrupt staff */ 389 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 390 391 if (channel == CHANNEL_0) { 392 ch->ch_iobase = 0; 393 ch->ch_iosize = HD64461_PCC0_IOSIZE; 394 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 395 HD64461_PCC0_IOBASE, 396 ch->ch_iosize); 397 fixup_sh3_pcmcia_area(ch->ch_iot); 398 399 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 400 hd64461pcmcia_channel0_intr, ch); 401 } else { 402 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 403 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 404 hd64461pcmcia_channel1_intr, ch); 405 } 406 407 paa.paa_busname = "pcmcia"; 408 paa.pch = (pcmcia_chipset_handle_t)ch; 409 paa.iobase = ch->ch_iobase; 410 paa.iosize = ch->ch_iosize; 411 412 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 413 hd64461pcmcia_submatch); 414 415 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 416 ch->ch_attached = 1; 417 pcmcia_card_attach(ch->ch_pcmcia); 418 } 419 } 420 421 int 422 hd64461pcmcia_channel0_intr(void *arg) 423 { 424 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 425 u_int8_t r; 426 int ret = 0; 427 428 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 429 /* clear interrtupt (edge source only) */ 430 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 431 432 if (r & HD64461_PCC0CSCR_P0IREQ) { 433 if (ch->ch_ih_card_func) { 434 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 435 } else 436 DPRINTF("spurious IREQ interrupt.\n"); 437 } 438 439 if (r & HD64461_PCC0CSCR_P0CDC) 440 queue_event(ch, detect_card(ch->ch_channel)); 441 442 return ret; 443 } 444 445 int 446 hd64461pcmcia_channel1_intr(void *arg) 447 { 448 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 449 u_int8_t r; 450 int ret = 0; 451 452 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 453 /* clear interrtupt */ 454 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 455 456 if (r & HD64461_PCC1CSCR_P1RC) { 457 if (ch->ch_ih_card_func) 458 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 459 else 460 DPRINTF("spurious READY interrupt.\n"); 461 } 462 463 if (r & HD64461_PCC1CSCR_P1CDC) 464 queue_event(ch, detect_card(ch->ch_channel)); 465 466 return ret; 467 } 468 469 void 470 queue_event(struct hd64461pcmcia_channel *ch, 471 enum hd64461pcmcia_event_type type) 472 { 473 struct hd64461pcmcia_event *pe, *pool; 474 struct hd64461pcmcia_softc *sc = ch->ch_parent; 475 int i; 476 int s = splhigh(); 477 478 if (type == EVENT_NONE) 479 goto out; 480 481 pe = 0; 482 pool = sc->sc_event_pool; 483 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 484 if (!pool[i].__queued) { 485 pe = &pool[i]; 486 break; 487 } 488 } 489 490 if (pe == 0) { 491 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 492 EVENT_QUEUE_MAX); 493 goto out; 494 } 495 496 if ((ch->ch_attached && (type == EVENT_INSERT)) || 497 (!ch->ch_attached && (type == EVENT_REMOVE))) { 498 DPRINTF("spurious CSC interrupt.\n"); 499 goto out; 500 } 501 502 ch->ch_attached = (type == EVENT_INSERT); 503 pe->__queued = 1; 504 pe->pe_type = type; 505 pe->pe_ch = ch; 506 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 507 wakeup(sc); 508 out: 509 splx(s); 510 } 511 512 /* 513 * interface for pcmcia driver. 514 */ 515 void * 516 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 517 struct pcmcia_function *pf, 518 int ipl, int (*ih_func)(void *), void *ih_arg) 519 { 520 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 521 int channel = ch->ch_channel; 522 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 523 int s = splhigh(); 524 u_int8_t r; 525 526 ch->ch_ih_card_func = ih_func; 527 ch->ch_ih_card_arg = ih_arg; 528 529 /* enable card interrupt */ 530 r = hd64461_reg_read_1(cscier); 531 if (channel == CHANNEL_0) { 532 /* set level mode */ 533 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 534 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 535 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 536 } else { 537 /* READY-pin LOW to HIGH changes generates interrupt */ 538 r |= HD64461_PCC1CSCIER_P1RE; 539 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 540 } 541 hd64461_reg_write_1(cscier, r); 542 543 splx(s); 544 545 return (void *)ih_func; 546 } 547 548 void 549 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 550 { 551 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 552 int channel = ch->ch_channel; 553 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 554 int s = splhigh(); 555 u_int8_t r; 556 557 /* disable card interrupt */ 558 r = hd64461_reg_read_1(cscier); 559 if (channel == CHANNEL_0) { 560 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 561 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 562 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 563 } else { 564 r &= ~HD64461_PCC1CSCIER_P1RE; 565 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 566 } 567 hd64461_reg_write_1(cscier, r); 568 569 ch->ch_ih_card_func = 0; 570 571 splx(s); 572 } 573 574 int 575 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 576 struct pcmcia_mem_handle *pcmhp) 577 { 578 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 579 580 pcmhp->memt = ch->ch_memt; 581 pcmhp->addr = ch->ch_membase_addr; 582 pcmhp->memh = ch->ch_memh; 583 pcmhp->size = size; 584 pcmhp->realsize = size; 585 586 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 587 588 return (0); 589 } 590 591 void 592 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 593 struct pcmcia_mem_handle *pcmhp) 594 { 595 /* nothing to do */ 596 } 597 598 int 599 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 600 bus_addr_t card_addr, 601 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 602 bus_size_t *offsetp, int *windowp) 603 { 604 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 605 struct hd64461pcmcia_window_cookie *cookie; 606 bus_addr_t ofs; 607 608 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 609 M_DEVBUF, M_NOWAIT); 610 KASSERT(cookie); 611 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 612 613 /* Address */ 614 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 615 cookie->wc_tag = ch->ch_memt; 616 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 617 size, &cookie->wc_handle) != 0) 618 goto bad; 619 620 *offsetp = card_addr; 621 cookie->wc_window = -1; 622 } else { 623 int window = card_addr / ch->ch_memsize; 624 KASSERT(window < MEMWIN_16M_MAX); 625 626 cookie->wc_tag = ch->ch_cmemt[window]; 627 ofs = card_addr - window * ch->ch_memsize; 628 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 629 &cookie->wc_handle) != 0) 630 goto bad; 631 632 /* XXX bogus. check window per common memory access. */ 633 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 634 *offsetp = ofs + 0x01000000; /* skip attribute area */ 635 cookie->wc_window = window; 636 } 637 cookie->wc_size = size; 638 *windowp = (int)cookie; 639 640 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 641 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 642 size); 643 644 return (0); 645 bad: 646 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 647 free(cookie, M_DEVBUF); 648 649 return (1); 650 } 651 652 void 653 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 654 { 655 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 656 657 if (cookie->wc_window != -1) 658 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 659 cookie->wc_size); 660 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 661 free(cookie, M_DEVBUF); 662 } 663 664 int 665 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 666 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 667 { 668 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 669 670 if (ch->ch_channel == CHANNEL_1) 671 return (1); 672 673 if (start) { 674 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 675 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 676 return (1); 677 } 678 DPRINTF("map %#lx+%#lx\n", start, size); 679 } else { 680 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 681 ch->ch_iobase + ch->ch_iosize - 1, 682 size, align, 0, 0, &pcihp->addr, 683 &pcihp->ioh)) { 684 DPRINTF("couldn't allocate %#lx\n", size); 685 return (1); 686 } 687 pcihp->flags = PCMCIA_IO_ALLOCATED; 688 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 689 } 690 691 pcihp->iot = ch->ch_iot; 692 pcihp->size = size; 693 694 return (0); 695 } 696 697 int 698 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 699 bus_addr_t offset, 700 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 701 { 702 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 703 #ifdef HD64461PCMCIA_DEBUG 704 static char *width_names[] = { "auto", "io8", "io16" }; 705 #endif 706 if (ch->ch_channel == CHANNEL_1) 707 return (1); 708 709 hd64461_set_bus_width(CHANNEL_0, width); 710 711 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 712 width_names[width]); 713 714 return (0); 715 } 716 717 void 718 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 719 struct pcmcia_io_handle *pcihp) 720 { 721 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 722 723 if (ch->ch_channel == CHANNEL_1) 724 return; 725 726 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 727 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 728 else 729 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 730 731 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 732 } 733 734 void 735 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 736 { 737 /* nothing to do */ 738 } 739 740 void 741 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 742 { 743 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 744 int channel = ch->ch_channel; 745 bus_addr_t isr, gcr; 746 u_int8_t r; 747 int cardtype; 748 749 DPRINTF("enable channel %d\n", channel); 750 isr = HD64461_PCCISR(channel); 751 gcr = HD64461_PCCGCR(channel); 752 753 hd64461pcmcia_power_off(channel); 754 hd64461pcmcia_power_on(channel); 755 #if notyet 756 { 757 int i; 758 /* assert reset */ 759 r = hd64461_reg_read_1(gcr); 760 r |= HD64461_PCCGCR_PCCR; 761 hd64461_reg_write_1(gcr, r); 762 763 /* 764 * hold RESET at least 10us. 765 */ 766 DELAY_MS(20); 767 768 /* clear the reset flag */ 769 r &= ~HD64461_PCCGCR_PCCR; 770 hd64461_reg_write_1(gcr, r); 771 DELAY_MS(2000); 772 773 /* wait for the chip to finish initializing */ 774 for (i = 0; i < 10000; i++) { 775 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 776 goto reset_ok; 777 DELAY_MS(500); 778 779 if ((i > 5000) && (i % 100 == 99)) 780 printf("."); 781 } 782 printf("reset failed.\n"); 783 hd64461pcmcia_power_off(channel); 784 return; 785 reset_ok: 786 } 787 #endif /* notyet */ 788 /* set Continuous 16-MB Area Mode */ 789 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 790 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 791 792 /* 793 * set Common memory area. 794 */ 795 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 796 797 /* set the card type */ 798 r = hd64461_reg_read_1(gcr); 799 if (channel == CHANNEL_0) { 800 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 801 if (cardtype == PCMCIA_IFTYPE_IO) 802 r |= HD64461_PCC0GCR_P0PCCT; 803 else 804 r &= ~HD64461_PCC0GCR_P0PCCT; 805 } else { 806 /* reserved bit must be 0 */ 807 r &= ~HD64461_PCC1GCR_RESERVED; 808 } 809 hd64461_reg_write_1(gcr, r); 810 811 DPRINTF("OK.\n"); 812 } 813 814 void 815 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 816 { 817 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 818 int channel = ch->ch_channel; 819 820 /* dont' disable CSC interrupt */ 821 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 822 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 823 824 /* power down the socket */ 825 hd64461pcmcia_power_off(channel); 826 } 827 828 /* 829 * Card detect 830 */ 831 void 832 hd64461pcmcia_power_off(enum controller_channel channel) 833 { 834 #if notyet 835 u_int8_t r; 836 u_int16_t r16; 837 bus_addr_t scr, gcr; 838 839 gcr = HD64461_PCCGCR(channel); 840 scr = HD64461_PCCSCR(channel); 841 842 /* DRV (external buffer) high level */ 843 r = hd64461_reg_read_1(gcr); 844 r &= ~HD64461_PCCGCR_DRVE; 845 hd64461_reg_write_1(gcr, r); 846 847 /* stop power */ 848 r = hd64461_reg_read_1(scr); 849 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 850 hd64461_reg_write_1(scr, r); 851 r = hd64461_reg_read_1(gcr); 852 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 853 hd64461_reg_write_1(gcr, r); 854 /* 855 * wait 300ms until power fails (Tpf). Then, wait 100ms since 856 * we are changing Vcc (Toff). 857 */ 858 DELAY_MS(300 + 100); 859 860 /* stop clock */ 861 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 862 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 863 HD64461_SYSSTBCR_SPC1ST); 864 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 865 866 if (channel == CHANNEL_0) { 867 /* GPIO Port A XXX Jornada690 specific? */ 868 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 869 r16 |= 0xf; 870 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 871 } 872 873 #endif /* notyet */ 874 } 875 876 void 877 hd64461pcmcia_power_on(enum controller_channel channel) 878 { 879 u_int8_t r; 880 u_int16_t r16; 881 bus_addr_t scr, gcr, isr; 882 883 isr = HD64461_PCCISR(channel); 884 gcr = HD64461_PCCGCR(channel); 885 scr = HD64461_PCCSCR(channel); 886 887 /* 888 * XXX to access attribute memory, this is required. 889 */ 890 if (channel == CHANNEL_0) { 891 /* GPIO Port A XXX Jonanada690 specific? */ 892 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 893 r16 &= ~0xf; 894 r16 |= 0x5; 895 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 896 } 897 898 if (channel == CHANNEL_1) { 899 /* GPIO Port C, Port D XXX HP620LX specific? */ 900 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 901 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 902 } 903 904 /* supply clock */ 905 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 906 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 907 HD64461_SYSSTBCR_SPC1ST); 908 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 909 DELAY_MS(200); 910 911 /* detect voltage and supply VCC */ 912 r = hd64461_reg_read_1(isr); 913 914 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 915 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 916 DPRINTF("5V card\n"); 917 hd64461pcmcia_power(channel, V_5, 1); 918 break; 919 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 920 /* FALLTHROUGH */ 921 case 0: /* x.x / 3.3 / 5 V */ 922 DPRINTF("3.3V card\n"); 923 hd64461pcmcia_power(channel, V_3_3, 1); 924 break; 925 case HD64461_PCCISR_VS1: /* x.x V */ 926 /* FALLTHROUGH */ 927 DPRINTF("x.x V card\n"); 928 hd64461pcmcia_power(channel, V_X_X, 1); 929 return; 930 default: 931 printf("\nunknown Voltage. don't attach.\n"); 932 return; 933 } 934 935 /* 936 * wait 100ms until power raise (Tpr) and 20ms to become 937 * stable (Tsu(Vcc)). 938 * 939 * some machines require some more time to be settled 940 * (300ms is added here). 941 */ 942 DELAY_MS(100 + 20 + 300); 943 944 /* DRV (external buffer) low level */ 945 r = hd64461_reg_read_1(gcr); 946 r |= HD64461_PCCGCR_DRVE; 947 hd64461_reg_write_1(gcr, r); 948 949 /* clear interrupt */ 950 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 951 HD64461_PCC1CSCR_REG8, 0); 952 } 953 954 enum hd64461pcmcia_event_type 955 detect_card(enum controller_channel channel) 956 { 957 u_int8_t r; 958 959 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 960 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 961 962 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 963 DPRINTF("remove\n"); 964 return EVENT_REMOVE; 965 } 966 if (r == 0) { 967 DPRINTF("insert\n"); 968 return EVENT_INSERT; 969 } 970 DPRINTF("transition\n"); 971 972 return EVENT_NONE; 973 } 974 975 /* 976 * Memory window access ops. 977 */ 978 void 979 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 980 enum memory_window_mode mode) 981 { 982 bus_addr_t a = HD64461_PCCGCR(channel); 983 u_int8_t r = hd64461_reg_read_1(a); 984 985 r &= ~HD64461_PCCGCR_MMOD; 986 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 987 HD64461_PCCGCR_MMOD_32M; 988 hd64461_reg_write_1(a, r); 989 } 990 991 void 992 hd64461pcmcia_memory_window_16(enum controller_channel channel, 993 enum memory_window_16 window) 994 { 995 bus_addr_t a = HD64461_PCCGCR(channel); 996 u_int8_t r; 997 998 r = hd64461_reg_read_1(a); 999 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1000 1001 switch (window) { 1002 case MEMWIN_16M_COMMON_0: 1003 break; 1004 case MEMWIN_16M_COMMON_1: 1005 r |= HD64461_PCCGCR_PA24; 1006 break; 1007 case MEMWIN_16M_COMMON_2: 1008 r |= HD64461_PCCGCR_PA25; 1009 break; 1010 case MEMWIN_16M_COMMON_3: 1011 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1012 break; 1013 } 1014 1015 hd64461_reg_write_1(a, r); 1016 } 1017 1018 #if unused 1019 void 1020 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1021 { 1022 bus_addr_t a = HD64461_PCCGCR(channel); 1023 u_int8_t r; 1024 1025 r = hd64461_reg_read_1(a); 1026 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1027 1028 switch (window) { 1029 case MEMWIN_32M_ATTR: 1030 break; 1031 case MEMWIN_32M_COMMON_0: 1032 r |= HD64461_PCCGCR_PREG; 1033 break; 1034 case MEMWIN_32M_COMMON_1: 1035 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1036 break; 1037 } 1038 1039 hd64461_reg_write_1(a, r); 1040 } 1041 #endif 1042 1043 void 1044 hd64461_set_bus_width(enum controller_channel channel, int width) 1045 { 1046 u_int16_t r16; 1047 1048 r16 = _reg_read_2(SH3_BCR2); 1049 if (channel == CHANNEL_0) { 1050 r16 &= ~((1 << 13)|(1 << 12)); 1051 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1052 } else { 1053 r16 &= ~((1 << 11)|(1 << 10)); 1054 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1055 } 1056 _reg_write_2(SH3_BCR2, r16); 1057 } 1058 1059 void 1060 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1061 { 1062 struct hpcsh_bus_space *hbs = (void *)t; 1063 1064 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1065 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1066 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1067 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1068 } 1069 1070 #ifdef HD64461PCMCIA_DEBUG 1071 void 1072 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1073 { 1074 u_int8_t r8; 1075 1076 dbg_banner_function(); 1077 /* 1078 * PCC0 1079 */ 1080 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1081 printf("PCC0 Interface Status Register\n"); 1082 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1083 1084 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1085 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1086 _(P0BVD2);_(P0BVD1); 1087 #undef _ 1088 printf("\n"); 1089 1090 printf("PCC0 General Control Register\n"); 1091 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1092 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1093 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1094 _(P0PA25);_(P0PA24);_(P0REG); 1095 #undef _ 1096 printf("\n"); 1097 1098 printf("PCC0 Card Status Change Register\n"); 1099 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1100 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1101 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1102 #undef _ 1103 printf("\n"); 1104 1105 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1106 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1107 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1108 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1109 #undef _ 1110 printf("\ninterrupt type: "); 1111 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1112 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1113 printf("none\n"); 1114 break; 1115 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1116 printf("level\n"); 1117 break; 1118 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1119 printf("falling edge\n"); 1120 break; 1121 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1122 printf("rising edge\n"); 1123 break; 1124 } 1125 1126 printf("PCC0 Software Control Register\n"); 1127 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1128 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1129 _(P0VCC1);_(P0SWP); 1130 #undef _ 1131 printf("\n"); 1132 1133 /* 1134 * PCC1 1135 */ 1136 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1137 printf("PCC1 Interface Status Register\n"); 1138 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1139 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1140 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1141 _(P1BVD2);_(P1BVD1); 1142 #undef _ 1143 printf("\n"); 1144 1145 printf("PCC1 General Contorol Register\n"); 1146 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1147 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1148 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1149 #undef _ 1150 printf("\n"); 1151 1152 printf("PCC1 Card Status Change Register\n"); 1153 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1154 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1155 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1156 #undef _ 1157 printf("\n"); 1158 1159 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1160 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1161 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1162 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1163 #undef _ 1164 printf("\n"); 1165 1166 printf("PCC1 Software Control Register\n"); 1167 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1168 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1169 _(P1VCC1);_(P1SWP); 1170 #undef _ 1171 printf("\n"); 1172 1173 /* 1174 * General Control 1175 */ 1176 printf("[General Control]\n"); 1177 printf("PCC0 Output pins Control Register\n"); 1178 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1179 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1180 _(P0DEPLUP);_(P0AEPLUP); 1181 #undef _ 1182 printf("\n"); 1183 1184 printf("PCC1 Output pins Control Register\n"); 1185 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1186 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1187 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1188 #undef _ 1189 printf("\n"); 1190 1191 printf("PC Card General Control Register\n"); 1192 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1193 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1194 _(PSSDIR);_(PSSRDWR); 1195 #undef _ 1196 printf("\n"); 1197 1198 dbg_banner_line(); 1199 } 1200 #endif /* HD64461PCMCIA_DEBUG */ 1201
Indexes created Thu Oct 02 01:09:59 GMT 2025