hd64461pcmcia.c revision 1.2
1 /* $NetBSD: hd64461pcmcia.c,v 1.2 2001/03/08 15:13:14 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #define HD64461PCMCIA_DEBUG 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 #include <sys/boot_flag.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #ifdef DEBUG 51 #include <hpcsh/hpcsh/debug.h> 52 #endif 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcvar.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64461PCMCIA_DEBUG 69 int hd64461pcmcia_debug = 1; 70 #define DPRINTF(fmt, args...) \ 71 if (hd64461pcmcia_debug) \ 72 printf("%s: " fmt, __FUNCTION__ , ##args) 73 #define DPRINTFN(n, arg) \ 74 if (hd64461pcmcia_debug > (n)) \ 75 printf("%s: " fmt, __FUNCTION__ , ##args) 76 #else 77 #define DPRINTF(arg...) ((void)0) 78 #define DPRINTFN(n, arg...) ((void)0) 79 #endif 80 81 enum controller_channel { 82 CHANNEL_0 = 0, 83 CHANNEL_1 = 1, 84 CHANNEL_MAX = 2 85 }; 86 87 enum memory_window_mode { 88 MEMWIN_16M_MODE, 89 MEMWIN_32M_MODE 90 }; 91 92 enum memory_window_16 { 93 MEMWIN_16M_COMMON_0, 94 MEMWIN_16M_COMMON_1, 95 MEMWIN_16M_COMMON_2, 96 MEMWIN_16M_COMMON_3, 97 }; 98 #define MEMWIN_16M_MAX 4 99 100 enum memory_window_32 { 101 MEMWIN_32M_ATTR, 102 MEMWIN_32M_COMMON_0, 103 MEMWIN_32M_COMMON_1, 104 }; 105 #define MEMWIN_32M_MAX 3 106 107 enum hd64461pcmcia_event_type { 108 EVENT_NONE, 109 EVENT_INSERT, 110 EVENT_REMOVE, 111 }; 112 #define EVENT_QUEUE_MAX 5 113 114 struct hd64461pcmcia_softc; /* forward declaration */ 115 116 struct hd64461pcmcia_window_cookie { 117 bus_space_tag_t wc_tag; 118 bus_space_handle_t wc_handle; 119 int wc_size; 120 int wc_window; 121 }; 122 123 struct hd64461pcmcia_channel { 124 struct hd64461pcmcia_softc *ch_parent; 125 struct device *ch_pcmcia; 126 enum controller_channel ch_channel; 127 128 /* memory space */ 129 enum memory_window_mode ch_memory_window_mode; 130 bus_space_tag_t ch_memt; 131 bus_space_handle_t ch_memh; 132 bus_addr_t ch_membase_addr; 133 bus_size_t ch_memsize; 134 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 135 136 /* I/O space */ 137 bus_space_tag_t ch_iot; 138 bus_addr_t ch_iobase; 139 bus_size_t ch_iosize; 140 141 /* card interrupt */ 142 int (*ch_ih_card_func)(void *); 143 void *ch_ih_card_arg; 144 int ch_attached; 145 }; 146 147 struct hd64461pcmcia_event { 148 int __queued; 149 enum hd64461pcmcia_event_type pe_type; 150 struct hd64461pcmcia_channel *pe_ch; 151 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 152 }; 153 154 struct hd64461pcmcia_softc { 155 struct device sc_dev; 156 enum hd64461_module_id sc_module_id; 157 int sc_shutdown; 158 159 /* CSC event */ 160 struct proc *sc_event_thread; 161 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 162 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 163 164 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 165 }; 166 167 static int _chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *); 169 static void _chip_mem_free(pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *); 171 static int _chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, 173 bus_addr_t *, int *); 174 static void _chip_mem_unmap(pcmcia_chipset_handle_t, int); 175 static int _chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 176 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 177 static void _chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 178 static int _chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 static void _chip_io_unmap(pcmcia_chipset_handle_t, int); 181 static void _chip_socket_enable(pcmcia_chipset_handle_t); 182 static void _chip_socket_disable(pcmcia_chipset_handle_t); 183 static void *_chip_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, 185 int (*)(void *), void *); 186 static void _chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 187 188 static struct pcmcia_chip_functions hd64461pcmcia_functions = { 189 _chip_mem_alloc, 190 _chip_mem_free, 191 _chip_mem_map, 192 _chip_mem_unmap, 193 _chip_io_alloc, 194 _chip_io_free, 195 _chip_io_map, 196 _chip_io_unmap, 197 _chip_intr_establish, 198 _chip_intr_disestablish, 199 _chip_socket_enable, 200 _chip_socket_disable, 201 }; 202 203 static int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 204 static void hd64461pcmcia_attach(struct device *, struct device *, void *); 205 static int hd64461pcmcia_print(void *, const char *); 206 static int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 207 208 struct cfattach hd64461pcmcia_ca = { 209 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 210 hd64461pcmcia_attach 211 }; 212 213 static void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 214 enum controller_channel); 215 /* hot plug */ 216 static void hd64461pcmcia_create_event_thread(void *); 217 static void hd64461pcmcia_event_thread(void *); 218 static void queue_event(struct hd64461pcmcia_channel *, 219 enum hd64461pcmcia_event_type); 220 /* interrupt handler */ 221 static int hd64461pcmcia_channel0_intr(void *); 222 static int hd64461pcmcia_channel1_intr(void *); 223 /* card status */ 224 static enum hd64461pcmcia_event_type detect_card(enum controller_channel); 225 static void power_off(enum controller_channel); 226 static void power_on(enum controller_channel); 227 /* memory window access ops */ 228 static void memory_window_mode(enum controller_channel, 229 enum memory_window_mode); 230 static void memory_window_16(enum controller_channel, enum memory_window_16); 231 /* bus width */ 232 static void set_bus_width(enum controller_channel, int); 233 #ifdef DEBUG 234 static void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 235 #endif 236 237 #define DELAY_MS(x) delay((x) * 1000) 238 239 static int 240 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 241 { 242 struct hd64461_attach_args *ha = aux; 243 244 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 245 } 246 247 static void 248 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 249 { 250 struct hd64461_attach_args *ha = aux; 251 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 252 253 sc->sc_module_id = ha->ha_module_id; 254 255 printf("\n"); 256 257 #ifdef DEBUG 258 if (bootverbose) 259 hd64461pcmcia_info(sc); 260 #endif 261 /* Channel 0/1 common CSC event queue */ 262 SIMPLEQ_INIT (&sc->sc_event_head); 263 kthread_create(hd64461pcmcia_create_event_thread, sc); 264 265 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 266 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 267 } 268 269 static void 270 hd64461pcmcia_create_event_thread(void *arg) 271 { 272 struct hd64461pcmcia_softc *sc = arg; 273 int error; 274 275 error = kthread_create1(hd64461pcmcia_event_thread, sc, 276 &sc->sc_event_thread, "%s", 277 sc->sc_dev.dv_xname); 278 KASSERT(error == 0); 279 } 280 281 static void 282 hd64461pcmcia_event_thread(void *arg) 283 { 284 struct hd64461pcmcia_softc *sc = arg; 285 struct hd64461pcmcia_event *pe; 286 int s; 287 288 while (!sc->sc_shutdown) { 289 tsleep(sc, PWAIT, "CSC wait", 0); 290 s = splhigh(); 291 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 292 splx(s); 293 switch (pe->pe_type) { 294 default: 295 printf("%s: unknown event.\n", __FUNCTION__); 296 break; 297 case EVENT_INSERT: 298 DPRINTF("insert event.\n"); 299 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 300 break; 301 case EVENT_REMOVE: 302 DPRINTF("remove event.\n"); 303 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 304 DETACH_FORCE); 305 break; 306 } 307 s = splhigh(); 308 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 309 pe->__queued = 0; 310 } 311 splx(s); 312 } 313 /* NOTREACHED */ 314 } 315 316 static int 317 hd64461pcmcia_print(void *arg, const char *pnp) 318 { 319 if (pnp) 320 printf("pcmcia at %s", pnp); 321 322 return (UNCONF); 323 } 324 325 static int 326 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 327 { 328 struct pcmciabus_attach_args *paa = aux; 329 struct hd64461pcmcia_channel *ch = 330 (struct hd64461pcmcia_channel *)paa->pch; 331 332 if (ch->ch_channel == CHANNEL_0) { 333 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 334 PCMCIABUSCF_CONTROLLER_DEFAULT && 335 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 336 return 0; 337 } else { 338 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 339 PCMCIABUSCF_CONTROLLER_DEFAULT && 340 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 341 return 0; 342 } 343 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 344 345 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 346 } 347 348 static void 349 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 350 enum controller_channel channel) 351 { 352 struct device *parent = (struct device *)sc; 353 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 354 struct pcmciabus_attach_args paa; 355 bus_addr_t membase; 356 int i; 357 358 ch->ch_parent = sc; 359 ch->ch_channel = channel; 360 361 /* 362 * Continuous 16-MB Area Mode 363 */ 364 /* Attibute/Common memory extent */ 365 membase = (channel == CHANNEL_0) 366 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 367 ch->ch_memt = bus_space_create("PCMCIA attribute memory", 368 membase, 0x01000000); /* 16MB */ 369 bus_space_alloc(ch->ch_memt, 0, 0x01000000, 0x01000000, 370 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 371 &ch->ch_memh); 372 373 /* Common memory space extent */ 374 ch->ch_memsize = 0x01000000; 375 for (i = 0; i < MEMWIN_16M_MAX; i++) { 376 ch->ch_cmemt[i] = bus_space_create("PCMCIA common memory", 377 membase + 0x01000000, 378 ch->ch_memsize); 379 } 380 381 /* I/O port extent and interrupt staff */ 382 _chip_socket_disable(ch); /* enable CSC interrupt only */ 383 384 if (channel == CHANNEL_0) { 385 ch->ch_iobase = 0; 386 ch->ch_iosize = HD64461_PCC0_IOSIZE; 387 ch->ch_iot = bus_space_create("PCMCIA I/O port", 388 HD64461_PCC0_IOBASE, 389 ch->ch_iosize); 390 391 392 hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 393 hd64461pcmcia_channel0_intr, ch); 394 } else { 395 set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 396 hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 397 hd64461pcmcia_channel1_intr, ch); 398 } 399 400 paa.paa_busname = "pcmcia"; 401 paa.pch = (pcmcia_chipset_handle_t)ch; 402 paa.iobase = ch->ch_iobase; 403 paa.iosize = ch->ch_iosize; 404 405 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 406 hd64461pcmcia_submatch); 407 408 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 409 ch->ch_attached = 1; 410 pcmcia_card_attach(ch->ch_pcmcia); 411 } 412 } 413 414 static int 415 hd64461pcmcia_channel0_intr(void *arg) 416 { 417 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 418 u_int8_t r; 419 int ret = 0; 420 421 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 422 /* clear interrtupt (edge source only) */ 423 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 424 425 if (r & HD64461_PCC0CSCR_P0IREQ) { 426 if (ch->ch_ih_card_func) 427 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 428 else 429 DPRINTF("spurious IREQ interrupt.\n"); 430 } 431 432 if (r & HD64461_PCC0CSCR_P0CDC) 433 queue_event(ch, detect_card(ch->ch_channel)); 434 435 return ret; 436 } 437 438 static int 439 hd64461pcmcia_channel1_intr(void *arg) 440 { 441 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 442 u_int8_t r; 443 int ret = 0; 444 445 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 446 /* clear interrtupt */ 447 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 448 449 if (r & HD64461_PCC1CSCR_P1RC) { 450 if (ch->ch_ih_card_func) 451 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 452 else 453 DPRINTF("spurious READY interrupt.\n"); 454 } 455 456 if (r & HD64461_PCC1CSCR_P1CDC) 457 queue_event(ch, detect_card(ch->ch_channel)); 458 459 return ret; 460 } 461 462 static void 463 queue_event(struct hd64461pcmcia_channel *ch, 464 enum hd64461pcmcia_event_type type) 465 { 466 struct hd64461pcmcia_event *pe, *pool; 467 struct hd64461pcmcia_softc *sc = ch->ch_parent; 468 int i; 469 int s = splhigh(); 470 471 if (type == EVENT_NONE) 472 goto out; 473 474 pe = 0; 475 pool = sc->sc_event_pool; 476 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 477 if (!pool[i].__queued) { 478 pe = &pool[i]; 479 break; 480 } 481 } 482 483 if (pe == 0) { 484 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 485 EVENT_QUEUE_MAX); 486 goto out; 487 } 488 489 if ((ch->ch_attached && (type == EVENT_INSERT)) || 490 (!ch->ch_attached && (type == EVENT_REMOVE))) { 491 DPRINTF("spurious CSC interrupt.\n"); 492 goto out; 493 } 494 495 ch->ch_attached = (type == EVENT_INSERT); 496 pe->__queued = 1; 497 pe->pe_type = type; 498 pe->pe_ch = ch; 499 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 500 wakeup(sc); 501 out: 502 splx(s); 503 } 504 505 /* 506 * interface for pcmcia driver. 507 */ 508 static void * 509 _chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, 510 int ipl, int (*ih_func)(void *), void *ih_arg) 511 { 512 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 513 int channel = ch->ch_channel; 514 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 515 int s = splhigh(); 516 u_int8_t r; 517 518 ch->ch_ih_card_func = ih_func; 519 ch->ch_ih_card_arg = ih_arg; 520 521 /* enable card interrupt */ 522 r = hd64461_reg_read_1(cscier); 523 if (channel == CHANNEL_0) { 524 /* set level mode */ 525 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 526 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 527 } else { 528 /* READY-pin LOW to HIGH changes generates interrupt */ 529 r |= HD64461_PCC1CSCIER_P1RE; 530 } 531 hd64461_reg_write_1(cscier, r); 532 533 splx(s); 534 535 return (void *)ih_func; 536 } 537 538 static void 539 _chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 540 { 541 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 542 int channel = ch->ch_channel; 543 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 544 int s = splhigh(); 545 u_int8_t r; 546 547 /* disable card interrupt */ 548 r = hd64461_reg_read_1(cscier); 549 if (channel == CHANNEL_0) { 550 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 551 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 552 } else { 553 r &= ~HD64461_PCC1CSCIER_P1RE; 554 } 555 hd64461_reg_write_1(cscier, r); 556 557 ch->ch_ih_card_func = 0; 558 559 splx(s); 560 } 561 562 static int 563 _chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 564 struct pcmcia_mem_handle *pcmhp) 565 { 566 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 567 568 pcmhp->memt = ch->ch_memt; 569 pcmhp->addr = ch->ch_membase_addr; 570 pcmhp->memh = ch->ch_memh; 571 pcmhp->size = size; 572 pcmhp->realsize = size; 573 574 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 575 576 return (0); 577 } 578 579 static void 580 _chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 581 { 582 /* nothing to do */ 583 } 584 585 static int 586 _chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, 587 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 588 bus_addr_t *offsetp, int *windowp) 589 { 590 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 591 struct hd64461pcmcia_window_cookie *cookie; 592 bus_addr_t ofs; 593 594 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 595 M_DEVBUF, M_NOWAIT); 596 KASSERT(cookie); 597 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 598 599 /* Address */ 600 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 601 cookie->wc_tag = ch->ch_memt; 602 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 603 size, &cookie->wc_handle) != 0) 604 goto bad; 605 606 *offsetp = card_addr; 607 cookie->wc_window = -1; 608 } else { 609 int window = card_addr / ch->ch_memsize; 610 KASSERT(window < MEMWIN_16M_MAX); 611 612 cookie->wc_tag = ch->ch_cmemt[window]; 613 ofs = card_addr - window * ch->ch_memsize; 614 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 615 &cookie->wc_handle) != 0) 616 goto bad; 617 618 // XXX bogus. bus_space_tag should be vtbl... 619 memory_window_16(ch->ch_channel, window); 620 *offsetp = ofs + 0x01000000; /* skip attribute area */ 621 cookie->wc_window = window; 622 } 623 cookie->wc_size = size; 624 *windowp = (int)cookie; 625 626 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 627 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 628 size); 629 630 return (0); 631 bad: 632 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 633 free(cookie, M_DEVBUF); 634 635 return (1); 636 } 637 638 static void 639 _chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 640 { 641 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 642 643 if (cookie->wc_window != -1) 644 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 645 cookie->wc_size); 646 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 647 free(cookie, M_DEVBUF); 648 } 649 650 static int 651 _chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, 652 bus_size_t align, struct pcmcia_io_handle *pcihp) 653 { 654 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 655 656 if (ch->ch_channel == CHANNEL_1) 657 return (1); 658 659 if (start) { 660 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 661 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 662 return (1); 663 } 664 DPRINTF("map %#lx+%#lx\n", start, size); 665 } else { 666 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 667 ch->ch_iobase + ch->ch_iosize, 668 size, align, 0, 0, &pcihp->addr, 669 &pcihp->ioh)) { 670 DPRINTF("couldn't allocate %#lx\n", size); 671 return (1); 672 } 673 pcihp->flags = PCMCIA_IO_ALLOCATED; 674 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 675 } 676 677 pcihp->iot = ch->ch_iot; 678 pcihp->size = size; 679 680 return (0); 681 } 682 683 static int 684 _chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 685 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 686 { 687 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 688 #ifdef HD64461PCMCIA_DEBUG 689 static char *width_names[] = { "auto", "io8", "io16" }; 690 #endif 691 if (ch->ch_channel == CHANNEL_1) 692 return (1); 693 694 set_bus_width(CHANNEL_0, width); 695 696 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 697 width_names[width]); 698 699 return (0); 700 } 701 702 static void 703 _chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 704 { 705 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 706 707 if (ch->ch_channel == CHANNEL_1) 708 return; 709 710 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 711 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 712 else 713 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 714 715 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 716 } 717 718 static void 719 _chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 720 { 721 /* nothing to do */ 722 } 723 724 static void 725 _chip_socket_enable(pcmcia_chipset_handle_t pch) 726 { 727 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 728 int channel = ch->ch_channel; 729 bus_addr_t isr, gcr; 730 u_int8_t r; 731 int cardtype; 732 int i; 733 734 DPRINTF("enable channel %d\n", channel); 735 isr = HD64461_PCCISR(channel); 736 gcr = HD64461_PCCGCR(channel); 737 738 power_off(channel); 739 power_on(channel); 740 741 /* assert reset */ 742 r = hd64461_reg_read_1(gcr); 743 r |= HD64461_PCCGCR_PCCR; 744 hd64461_reg_write_1(gcr, r); 745 746 /* 747 * hold RESET at least 10us. 748 */ 749 DELAY_MS(20); 750 751 /* clear the reset flag */ 752 r &= ~HD64461_PCCGCR_PCCR; 753 hd64461_reg_write_1(gcr, r); 754 DELAY_MS(2000); 755 756 /* wait for the chip to finish initializing */ 757 for (i = 0; i < 10000; i++) { 758 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 759 goto reset_ok; 760 DELAY_MS(500); 761 762 if ((i > 5000) && (i % 100 == 99)) 763 printf("."); 764 } 765 printf("reset failed.\n"); 766 power_off(channel); 767 return; 768 reset_ok: 769 770 /* set Continuous 16-MB Area Mode */ 771 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 772 memory_window_mode(channel, ch->ch_memory_window_mode); 773 774 /* 775 * set Common memory area. 776 */ 777 memory_window_16(channel, MEMWIN_16M_COMMON_0); 778 779 /* set the card type */ 780 if (channel == CHANNEL_0) { 781 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 782 r = hd64461_reg_read_1(gcr); 783 if (cardtype == PCMCIA_IFTYPE_IO) 784 r |= HD64461_PCC0GCR_P0PCCT; 785 else 786 r &= ~HD64461_PCC0GCR_P0PCCT; 787 hd64461_reg_write_1(gcr, r); 788 } 789 790 791 DPRINTF("OK.\n"); 792 } 793 794 static void 795 _chip_socket_disable(pcmcia_chipset_handle_t pch) 796 { 797 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 798 int channel = ch->ch_channel; 799 800 /* dont' disable CSC interrupt */ 801 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 802 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 803 804 /* power down the socket */ 805 power_off(channel); 806 } 807 808 /* 809 * Card detect 810 */ 811 static void 812 power_off(enum controller_channel channel) 813 { 814 u_int8_t r; 815 u_int16_t r16; 816 bus_addr_t scr, gcr; 817 818 gcr = HD64461_PCCGCR(channel); 819 scr = HD64461_PCCSCR(channel); 820 821 /* DRV (external buffer) high level */ 822 r = hd64461_reg_read_1(gcr); 823 r &= ~HD64461_PCCGCR_DRVE; 824 hd64461_reg_write_1(gcr, r); 825 826 /* stop power */ 827 r = hd64461_reg_read_1(scr); 828 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 829 hd64461_reg_write_1(scr, r); 830 r = hd64461_reg_read_1(gcr); 831 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 832 hd64461_reg_write_1(gcr, r); 833 /* 834 * wait 300ms until power fails (Tpf). Then, wait 100ms since 835 * we are changing Vcc (Toff). 836 */ 837 DELAY_MS(300 + 100); 838 839 /* stop clock */ 840 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 841 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 842 HD64461_SYSSTBCR_SPC1ST); 843 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 844 845 if (channel == CHANNEL_0) { 846 /* GPIO Port A XXX Jonanada690 specific? */ 847 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 848 r16 |= 0xf; 849 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 850 } 851 } 852 853 static void 854 power_on(enum controller_channel channel) 855 { 856 u_int8_t r; 857 u_int16_t r16; 858 bus_addr_t scr, gcr, isr; 859 860 isr = HD64461_PCCISR(channel); 861 gcr = HD64461_PCCGCR(channel); 862 scr = HD64461_PCCSCR(channel); 863 864 if (channel == CHANNEL_0) { 865 /* GPIO Port A XXX Jonanada690 specific? */ 866 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 867 r16 &= ~0xf; 868 r16 |= 0x5; 869 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 870 } 871 872 /* supply clock */ 873 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 874 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 875 HD64461_SYSSTBCR_SPC1ST); 876 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 877 DELAY_MS(200); 878 879 /* detect voltage and supply VCC */ 880 r = hd64461_reg_read_1(isr); 881 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 882 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): 883 DPRINTF("5V card\n"); 884 r = hd64461_reg_read_1(gcr); 885 r &= ~HD64461_PCCGCR_VCC0; 886 hd64461_reg_write_1(gcr, r); 887 r = hd64461_reg_read_1(scr); 888 r &= ~HD64461_PCCSCR_VCC1; 889 hd64461_reg_write_1(scr, r); 890 break; 891 case HD64461_PCCISR_VS2: 892 DPRINTF("3.3V card\n"); 893 if (channel == CHANNEL_1) { 894 r = hd64461_reg_read_1(gcr); 895 r &= ~HD64461_PCCGCR_VCC0; 896 hd64461_reg_write_1(gcr, r); 897 } 898 r = hd64461_reg_read_1(scr); 899 r &= ~HD64461_PCCSCR_VCC1; 900 hd64461_reg_write_1(scr, r); 901 break; 902 default: 903 printf("\nunknown Voltage. don't attach.\n"); 904 return; 905 } 906 /* 907 * wait 100ms until power raise (Tpr) and 20ms to become 908 * stable (Tsu(Vcc)). 909 * 910 * some machines require some more time to be settled 911 * (300ms is added here). 912 */ 913 DELAY_MS(100 + 20 + 300); 914 915 /* DRV (external buffer) low level */ 916 r = hd64461_reg_read_1(gcr); 917 r |= HD64461_PCCGCR_DRVE; 918 hd64461_reg_write_1(gcr, r); 919 920 /* clear interrupt */ 921 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 922 HD64461_PCC1CSCR_REG8, 0); 923 } 924 925 static enum hd64461pcmcia_event_type 926 detect_card(enum controller_channel channel) 927 { 928 u_int8_t r; 929 930 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 931 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 932 933 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 934 DPRINTF("remove\n"); 935 return EVENT_REMOVE; 936 } 937 if (r == 0) { 938 DPRINTF("insert\n"); 939 return EVENT_INSERT; 940 } 941 DPRINTF("transition\n"); 942 943 return EVENT_NONE; 944 } 945 946 /* 947 * Memory window access ops. 948 */ 949 static void 950 memory_window_mode(enum controller_channel channel, 951 enum memory_window_mode mode) 952 { 953 bus_addr_t a = HD64461_PCCGCR(channel); 954 u_int8_t r = hd64461_reg_read_1(a); 955 956 r &= ~HD64461_PCCGCR_MMOD; 957 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 958 HD64461_PCCGCR_MMOD_32M; 959 hd64461_reg_write_1(a, r); 960 } 961 962 static void 963 memory_window_16(enum controller_channel channel, enum memory_window_16 window) 964 { 965 bus_addr_t a = HD64461_PCCGCR(channel); 966 u_int8_t r; 967 968 r = hd64461_reg_read_1(a); 969 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 970 971 switch (window) { 972 case MEMWIN_16M_COMMON_0: 973 break; 974 case MEMWIN_16M_COMMON_1: 975 r |= HD64461_PCCGCR_PA24; 976 break; 977 case MEMWIN_16M_COMMON_2: 978 r |= HD64461_PCCGCR_PA25; 979 break; 980 case MEMWIN_16M_COMMON_3: 981 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 982 break; 983 } 984 985 hd64461_reg_write_1(a, r); 986 } 987 988 #if unused 989 static void 990 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 991 { 992 bus_addr_t a = HD64461_PCCGCR(channel); 993 u_int8_t r; 994 995 r = hd64461_reg_read_1(a); 996 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 997 998 switch (window) { 999 case MEMWIN_32M_ATTR: 1000 break; 1001 case MEMWIN_32M_COMMON_0: 1002 r |= HD64461_PCCGCR_PREG; 1003 break; 1004 case MEMWIN_32M_COMMON_1: 1005 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1006 break; 1007 } 1008 1009 hd64461_reg_write_1(a, r); 1010 } 1011 #endif 1012 1013 static void 1014 set_bus_width(enum controller_channel channel, int width) 1015 { 1016 u_int16_t r16; 1017 1018 r16 = SHREG_BCR2; 1019 if (channel == CHANNEL_0) { 1020 r16 &= ~((1 << 13)|(1 << 12)); 1021 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1022 } else { 1023 r16 &= ~((1 << 11)|(1 << 10)); 1024 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1025 } 1026 SHREG_BCR2 = r16; 1027 } 1028 1029 #ifdef DEBUG 1030 static void 1031 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1032 { 1033 const char name[] = __FUNCTION__; 1034 u_int8_t r8; 1035 1036 dbg_banner_start(name, sizeof name); 1037 /* 1038 * PCC0 1039 */ 1040 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1041 printf("PCC0 Interface Status Register\n"); 1042 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1043 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 1044 DBG_BIT_PRINT(r8, P0READY); 1045 DBG_BIT_PRINT(r8, P0MWP); 1046 DBG_BIT_PRINT(r8, P0VS2); 1047 DBG_BIT_PRINT(r8, P0VS1); 1048 DBG_BIT_PRINT(r8, P0CD2); 1049 DBG_BIT_PRINT(r8, P0CD1); 1050 DBG_BIT_PRINT(r8, P0BVD2); 1051 DBG_BIT_PRINT(r8, P0BVD1); 1052 #undef DBG_BIT_PRINT 1053 printf("\n"); 1054 1055 printf("PCC0 General Control Register\n"); 1056 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1057 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 1058 DBG_BIT_PRINT(r8, P0DRVE); 1059 DBG_BIT_PRINT(r8, P0PCCR); 1060 DBG_BIT_PRINT(r8, P0PCCT); 1061 DBG_BIT_PRINT(r8, P0VCC0); 1062 DBG_BIT_PRINT(r8, P0MMOD); 1063 DBG_BIT_PRINT(r8, P0PA25); 1064 DBG_BIT_PRINT(r8, P0PA24); 1065 DBG_BIT_PRINT(r8, P0REG); 1066 #undef DBG_BIT_PRINT 1067 printf("\n"); 1068 1069 printf("PCC0 Card Status Change Register\n"); 1070 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1071 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 1072 DBG_BIT_PRINT(r8, P0SCDI); 1073 DBG_BIT_PRINT(r8, P0IREQ); 1074 DBG_BIT_PRINT(r8, P0SC); 1075 DBG_BIT_PRINT(r8, P0CDC); 1076 DBG_BIT_PRINT(r8, P0RC); 1077 DBG_BIT_PRINT(r8, P0BW); 1078 DBG_BIT_PRINT(r8, P0BD); 1079 #undef DBG_BIT_PRINT 1080 printf("\n"); 1081 1082 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1083 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1084 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 1085 DBG_BIT_PRINT(r8, P0CRE); 1086 DBG_BIT_PRINT(r8, P0SCE); 1087 DBG_BIT_PRINT(r8, P0CDE); 1088 DBG_BIT_PRINT(r8, P0RE); 1089 DBG_BIT_PRINT(r8, P0BWE); 1090 DBG_BIT_PRINT(r8, P0BDE); 1091 #undef DBG_BIT_PRINT 1092 printf("\ninterrupt type: "); 1093 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1094 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1095 printf("none\n"); 1096 break; 1097 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1098 printf("level\n"); 1099 break; 1100 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1101 printf("falling edge\n"); 1102 break; 1103 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1104 printf("rising edge\n"); 1105 break; 1106 } 1107 1108 printf("PCC0 Software Control Register\n"); 1109 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1110 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 1111 DBG_BIT_PRINT(r8, P0VCC1); 1112 DBG_BIT_PRINT(r8, P0SWP); 1113 #undef DBG_BIT_PRINT 1114 printf("\n"); 1115 1116 /* 1117 * PCC1 1118 */ 1119 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1120 printf("PCC1 Interface Status Register\n"); 1121 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1122 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 1123 DBG_BIT_PRINT(r8, P1READY); 1124 DBG_BIT_PRINT(r8, P1MWP); 1125 DBG_BIT_PRINT(r8, P1VS2); 1126 DBG_BIT_PRINT(r8, P1VS1); 1127 DBG_BIT_PRINT(r8, P1CD2); 1128 DBG_BIT_PRINT(r8, P1CD1); 1129 DBG_BIT_PRINT(r8, P1BVD2); 1130 DBG_BIT_PRINT(r8, P1BVD1); 1131 #undef DBG_BIT_PRINT 1132 printf("\n"); 1133 1134 printf("PCC1 General Contorol Register\n"); 1135 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1136 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 1137 DBG_BIT_PRINT(r8, P1DRVE); 1138 DBG_BIT_PRINT(r8, P1PCCR); 1139 DBG_BIT_PRINT(r8, P1VCC0); 1140 DBG_BIT_PRINT(r8, P1MMOD); 1141 DBG_BIT_PRINT(r8, P1PA25); 1142 DBG_BIT_PRINT(r8, P1PA24); 1143 DBG_BIT_PRINT(r8, P1REG); 1144 #undef DBG_BIT_PRINT 1145 printf("\n"); 1146 1147 printf("PCC1 Card Status Change Register\n"); 1148 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1149 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 1150 DBG_BIT_PRINT(r8, P1SCDI); 1151 DBG_BIT_PRINT(r8, P1CDC); 1152 DBG_BIT_PRINT(r8, P1RC); 1153 DBG_BIT_PRINT(r8, P1BW); 1154 DBG_BIT_PRINT(r8, P1BD); 1155 #undef DBG_BIT_PRINT 1156 printf("\n"); 1157 1158 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1159 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1160 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 1161 DBG_BIT_PRINT(r8, P1CRE); 1162 DBG_BIT_PRINT(r8, P1CDE); 1163 DBG_BIT_PRINT(r8, P1RE); 1164 DBG_BIT_PRINT(r8, P1BWE); 1165 DBG_BIT_PRINT(r8, P1BDE); 1166 #undef DBG_BIT_PRINT 1167 printf("\n"); 1168 1169 printf("PCC1 Software Control Register\n"); 1170 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1171 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 1172 DBG_BIT_PRINT(r8, P1VCC1); 1173 DBG_BIT_PRINT(r8, P1SWP); 1174 #undef DBG_BIT_PRINT 1175 printf("\n"); 1176 1177 /* 1178 * General Control 1179 */ 1180 printf("[General Control]\n"); 1181 printf("PCC0 Output pins Control Register\n"); 1182 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1183 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 1184 DBG_BIT_PRINT(r8, P0DEPLUP); 1185 DBG_BIT_PRINT(r8, P0AEPLUP); 1186 #undef DBG_BIT_PRINT 1187 printf("\n"); 1188 1189 printf("PCC1 Output pins Control Register\n"); 1190 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1191 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 1192 DBG_BIT_PRINT(r8, P1RST8MA); 1193 DBG_BIT_PRINT(r8, P1RST4MA); 1194 DBG_BIT_PRINT(r8, P1RAS8MA); 1195 DBG_BIT_PRINT(r8, P1RAS4MA); 1196 #undef DBG_BIT_PRINT 1197 printf("\n"); 1198 1199 printf("PC Card General Control Register\n"); 1200 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1201 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 1202 DBG_BIT_PRINT(r8, PSSDIR); 1203 DBG_BIT_PRINT(r8, PSSRDWR); 1204 #undef DBG_BIT_PRINT 1205 printf("\n"); 1206 1207 dbg_banner_end(); 1208 } 1209 #endif /* DEBUG */ 1210 1211
Indexes created Thu Oct 02 01:09:59 GMT 2025