hd64461pcmcia.c revision 1.41
1 /* $NetBSD: hd64461pcmcia.c,v 1.41 2008/02/17 06:03:13 uwe Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.41 2008/02/17 06:03:13 uwe Exp $"); 41 42 #include "opt_hd64461pcmcia.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/kthread.h> 49 #include <sys/boot_flag.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 65 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 66 67 #include "locators.h" 68 69 #ifdef HD64461PCMCIA_DEBUG 70 #define DPRINTF_ENABLE 71 #define DPRINTF_DEBUG hd64461pcmcia_debug 72 #endif 73 #include <machine/debug.h> 74 75 enum controller_channel { 76 CHANNEL_0 = 0, 77 CHANNEL_1 = 1, 78 CHANNEL_MAX = 2 79 }; 80 81 enum memory_window_mode { 82 MEMWIN_16M_MODE, 83 MEMWIN_32M_MODE 84 }; 85 86 enum memory_window_16 { 87 MEMWIN_16M_COMMON_0, 88 MEMWIN_16M_COMMON_1, 89 MEMWIN_16M_COMMON_2, 90 MEMWIN_16M_COMMON_3, 91 }; 92 #define MEMWIN_16M_MAX 4 93 94 enum memory_window_32 { 95 MEMWIN_32M_ATTR, 96 MEMWIN_32M_COMMON_0, 97 MEMWIN_32M_COMMON_1, 98 }; 99 #define MEMWIN_32M_MAX 3 100 101 enum hd64461pcmcia_event_type { 102 EVENT_NONE, 103 EVENT_INSERT, 104 EVENT_REMOVE, 105 }; 106 #define EVENT_QUEUE_MAX 5 107 108 struct hd64461pcmcia_softc; /* forward declaration */ 109 110 struct hd64461pcmcia_window_cookie { 111 bus_space_tag_t wc_tag; 112 bus_space_handle_t wc_handle; 113 int wc_size; 114 int wc_window; 115 }; 116 117 struct hd64461pcmcia_channel { 118 struct hd64461pcmcia_softc *ch_parent; 119 struct device *ch_pcmcia; 120 enum controller_channel ch_channel; 121 122 /* memory space */ 123 enum memory_window_mode ch_memory_window_mode; 124 bus_space_tag_t ch_memt; 125 bus_space_handle_t ch_memh; 126 bus_addr_t ch_membase_addr; 127 bus_size_t ch_memsize; 128 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 129 130 /* I/O space */ 131 bus_space_tag_t ch_iot; 132 bus_addr_t ch_iobase; 133 bus_size_t ch_iosize; 134 135 /* card interrupt */ 136 int (*ch_ih_card_func)(void *); 137 void *ch_ih_card_arg; 138 int ch_attached; 139 }; 140 141 struct hd64461pcmcia_event { 142 int __queued; 143 enum hd64461pcmcia_event_type pe_type; 144 struct hd64461pcmcia_channel *pe_ch; 145 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 146 }; 147 148 struct hd64461pcmcia_softc { 149 struct device sc_dev; 150 enum hd64461_module_id sc_module_id; 151 int sc_shutdown; 152 153 /* CSC event */ 154 lwp_t *sc_event_thread; 155 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 156 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 157 158 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 159 }; 160 161 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 162 struct pcmcia_mem_handle *); 163 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 164 struct pcmcia_mem_handle *); 165 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 166 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 167 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 168 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 169 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 170 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 171 struct pcmcia_io_handle *); 172 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 173 bus_size_t, struct pcmcia_io_handle *, int *); 174 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 175 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 176 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 177 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 178 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 179 struct pcmcia_function *, int, int (*)(void *), void *); 180 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 181 void *); 182 183 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 184 hd64461pcmcia_chip_mem_alloc, 185 hd64461pcmcia_chip_mem_free, 186 hd64461pcmcia_chip_mem_map, 187 hd64461pcmcia_chip_mem_unmap, 188 hd64461pcmcia_chip_io_alloc, 189 hd64461pcmcia_chip_io_free, 190 hd64461pcmcia_chip_io_map, 191 hd64461pcmcia_chip_io_unmap, 192 hd64461pcmcia_chip_intr_establish, 193 hd64461pcmcia_chip_intr_disestablish, 194 hd64461pcmcia_chip_socket_enable, 195 hd64461pcmcia_chip_socket_disable, 196 hd64461pcmcia_chip_socket_settype, 197 }; 198 199 STATIC int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 200 STATIC void hd64461pcmcia_attach(struct device *, struct device *, void *); 201 STATIC int hd64461pcmcia_print(void *, const char *); 202 STATIC int hd64461pcmcia_submatch(struct device *, struct cfdata *, 203 const int *, void *); 204 205 CFATTACH_DECL(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 206 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 207 208 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 209 enum controller_channel); 210 /* hot plug */ 211 STATIC void hd64461pcmcia_event_thread(void *); 212 STATIC void queue_event(struct hd64461pcmcia_channel *, 213 enum hd64461pcmcia_event_type); 214 /* interrupt handler */ 215 STATIC int hd64461pcmcia_channel0_intr(void *); 216 STATIC int hd64461pcmcia_channel1_intr(void *); 217 /* card status */ 218 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 219 STATIC void hd64461pcmcia_power_off(enum controller_channel); 220 STATIC void hd64461pcmcia_power_on(enum controller_channel); 221 /* memory window access ops */ 222 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 223 enum memory_window_mode)__attribute__((__unused__)); 224 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 225 enum memory_window_16); 226 /* bus width */ 227 STATIC void hd64461_set_bus_width(enum controller_channel, int); 228 #ifdef HD64461PCMCIA_DEBUG 229 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 230 #endif 231 /* fix SH3 Area[56] bug */ 232 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 233 #define _BUS_SPACE_ACCESS_HOOK() \ 234 do { \ 235 uint8_t dummy __attribute__((__unused__)) = \ 236 *(volatile uint8_t *)0xba000000; \ 237 } while (/*CONSTCOND*/0) 238 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 239 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 240 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 241 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 242 #undef _BUS_SPACE_ACCESS_HOOK 243 244 #define DELAY_MS(x) delay((x) * 1000) 245 246 STATIC int 247 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 248 { 249 struct hd64461_attach_args *ha = aux; 250 251 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 252 } 253 254 STATIC void 255 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 256 { 257 struct hd64461_attach_args *ha = aux; 258 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 259 int error; 260 261 sc->sc_module_id = ha->ha_module_id; 262 263 aprint_naive("\n"); 264 aprint_normal("\n"); 265 266 #ifdef HD64461PCMCIA_DEBUG 267 hd64461pcmcia_info(sc); 268 #endif 269 /* Channel 0/1 common CSC event queue */ 270 SIMPLEQ_INIT (&sc->sc_event_head); 271 error = kthread_create(PRI_NONE, 0, NULL, 272 hd64461pcmcia_event_thread, sc, 273 &sc->sc_event_thread, 274 "%s", device_xname(self)); 275 KASSERT(error == 0); 276 277 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 278 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 279 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 280 #else 281 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 282 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 283 #endif 284 } 285 286 STATIC void 287 hd64461pcmcia_event_thread(void *arg) 288 { 289 struct hd64461pcmcia_softc *sc = arg; 290 struct hd64461pcmcia_event *pe; 291 int s; 292 293 while (!sc->sc_shutdown) { 294 tsleep(sc, PWAIT, "CSC wait", 0); 295 s = splhigh(); 296 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 297 splx(s); 298 switch (pe->pe_type) { 299 default: 300 printf("%s: unknown event.\n", __func__); 301 break; 302 case EVENT_INSERT: 303 DPRINTF("insert event.\n"); 304 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 305 break; 306 case EVENT_REMOVE: 307 DPRINTF("remove event.\n"); 308 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 309 DETACH_FORCE); 310 break; 311 } 312 s = splhigh(); 313 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 314 pe->__queued = 0; 315 } 316 splx(s); 317 } 318 /* NOTREACHED */ 319 } 320 321 STATIC int 322 hd64461pcmcia_print(void *arg, const char *pnp) 323 { 324 325 if (pnp) 326 aprint_normal("pcmcia at %s", pnp); 327 328 return (UNCONF); 329 } 330 331 STATIC int 332 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, 333 const int *ldesc, void *aux) 334 { 335 struct pcmciabus_attach_args *paa = aux; 336 struct hd64461pcmcia_channel *ch = 337 (struct hd64461pcmcia_channel *)paa->pch; 338 339 if (ch->ch_channel == CHANNEL_0) { 340 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 341 PCMCIABUSCF_CONTROLLER_DEFAULT && 342 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 343 return 0; 344 } else { 345 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 346 PCMCIABUSCF_CONTROLLER_DEFAULT && 347 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 348 return 0; 349 } 350 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 351 352 return (config_match(parent, cf, aux)); 353 } 354 355 STATIC void 356 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 357 enum controller_channel channel) 358 { 359 struct device *parent = (struct device *)sc; 360 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 361 struct pcmciabus_attach_args paa; 362 bus_addr_t membase; 363 int i; 364 365 ch->ch_parent = sc; 366 ch->ch_channel = channel; 367 368 /* 369 * Continuous 16-MB Area Mode 370 */ 371 /* Attibute/Common memory extent */ 372 membase = (channel == CHANNEL_0) 373 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 374 375 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 376 membase, 0x01000000); /* 16MB */ 377 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 378 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 379 &ch->ch_memh); 380 fixup_sh3_pcmcia_area(ch->ch_memt); 381 382 /* Common memory space extent */ 383 ch->ch_memsize = 0x01000000; 384 for (i = 0; i < MEMWIN_16M_MAX; i++) { 385 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 386 membase + 0x01000000, 387 ch->ch_memsize); 388 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 389 } 390 391 /* I/O port extent and interrupt staff */ 392 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 393 394 if (channel == CHANNEL_0) { 395 ch->ch_iobase = 0; 396 ch->ch_iosize = HD64461_PCC0_IOSIZE; 397 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 398 HD64461_PCC0_IOBASE, 399 ch->ch_iosize); 400 fixup_sh3_pcmcia_area(ch->ch_iot); 401 402 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 403 hd64461pcmcia_channel0_intr, ch); 404 } else { 405 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 406 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 407 hd64461pcmcia_channel1_intr, ch); 408 } 409 410 paa.paa_busname = "pcmcia"; 411 paa.pch = (pcmcia_chipset_handle_t)ch; 412 paa.iobase = ch->ch_iobase; 413 paa.iosize = ch->ch_iosize; 414 415 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 416 hd64461pcmcia_print, hd64461pcmcia_submatch); 417 418 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 419 ch->ch_attached = 1; 420 pcmcia_card_attach(ch->ch_pcmcia); 421 } 422 } 423 424 STATIC int 425 hd64461pcmcia_channel0_intr(void *arg) 426 { 427 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 428 uint8_t r; 429 int ret = 0; 430 431 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 432 /* clear interrtupt (edge source only) */ 433 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 434 435 if (r & HD64461_PCC0CSCR_P0IREQ) { 436 if (ch->ch_ih_card_func) { 437 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 438 } else 439 DPRINTF("spurious IREQ interrupt.\n"); 440 } 441 442 if (r & HD64461_PCC0CSCR_P0CDC) 443 queue_event(ch, detect_card(ch->ch_channel)); 444 445 return ret; 446 } 447 448 STATIC int 449 hd64461pcmcia_channel1_intr(void *arg) 450 { 451 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 452 uint8_t r; 453 int ret = 0; 454 455 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 456 /* clear interrtupt */ 457 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 458 459 if (r & HD64461_PCC1CSCR_P1RC) { 460 if (ch->ch_ih_card_func) 461 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 462 else 463 DPRINTF("spurious READY interrupt.\n"); 464 } 465 466 if (r & HD64461_PCC1CSCR_P1CDC) 467 queue_event(ch, detect_card(ch->ch_channel)); 468 469 return ret; 470 } 471 472 STATIC void 473 queue_event(struct hd64461pcmcia_channel *ch, 474 enum hd64461pcmcia_event_type type) 475 { 476 struct hd64461pcmcia_event *pe, *pool; 477 struct hd64461pcmcia_softc *sc = ch->ch_parent; 478 int i; 479 int s = splhigh(); 480 481 if (type == EVENT_NONE) 482 goto out; 483 484 pe = 0; 485 pool = sc->sc_event_pool; 486 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 487 if (!pool[i].__queued) { 488 pe = &pool[i]; 489 break; 490 } 491 } 492 493 if (pe == 0) { 494 printf("%s: event FIFO overflow (max %d).\n", __func__, 495 EVENT_QUEUE_MAX); 496 goto out; 497 } 498 499 if ((ch->ch_attached && (type == EVENT_INSERT)) || 500 (!ch->ch_attached && (type == EVENT_REMOVE))) { 501 DPRINTF("spurious CSC interrupt.\n"); 502 goto out; 503 } 504 505 ch->ch_attached = (type == EVENT_INSERT); 506 pe->__queued = 1; 507 pe->pe_type = type; 508 pe->pe_ch = ch; 509 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 510 wakeup(sc); 511 out: 512 splx(s); 513 } 514 515 /* 516 * interface for pcmcia driver. 517 */ 518 STATIC void * 519 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 520 struct pcmcia_function *pf, 521 int ipl, int (*ih_func)(void *), void *ih_arg) 522 { 523 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 524 int channel = ch->ch_channel; 525 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 526 int s = splhigh(); 527 uint8_t r; 528 529 ch->ch_ih_card_func = ih_func; 530 ch->ch_ih_card_arg = ih_arg; 531 532 /* enable card interrupt */ 533 r = hd64461_reg_read_1(cscier); 534 if (channel == CHANNEL_0) { 535 /* set level mode */ 536 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 537 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 538 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 539 } else { 540 /* READY-pin LOW to HIGH changes generates interrupt */ 541 r |= HD64461_PCC1CSCIER_P1RE; 542 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 543 } 544 hd64461_reg_write_1(cscier, r); 545 546 splx(s); 547 548 return (void *)ih_func; 549 } 550 551 STATIC void 552 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 553 { 554 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 555 int channel = ch->ch_channel; 556 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 557 int s = splhigh(); 558 uint8_t r; 559 560 /* disable card interrupt */ 561 r = hd64461_reg_read_1(cscier); 562 if (channel == CHANNEL_0) { 563 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 564 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 565 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 566 } else { 567 r &= ~HD64461_PCC1CSCIER_P1RE; 568 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 569 } 570 hd64461_reg_write_1(cscier, r); 571 572 ch->ch_ih_card_func = 0; 573 574 splx(s); 575 } 576 577 STATIC int 578 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 579 struct pcmcia_mem_handle *pcmhp) 580 { 581 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 582 583 pcmhp->memt = ch->ch_memt; 584 pcmhp->addr = ch->ch_membase_addr; 585 pcmhp->memh = ch->ch_memh; 586 pcmhp->size = size; 587 pcmhp->realsize = size; 588 589 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 590 591 return (0); 592 } 593 594 STATIC void 595 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 596 struct pcmcia_mem_handle *pcmhp) 597 { 598 /* nothing to do */ 599 } 600 601 STATIC int 602 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 603 bus_addr_t card_addr, 604 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 605 bus_size_t *offsetp, int *windowp) 606 { 607 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 608 struct hd64461pcmcia_window_cookie *cookie; 609 bus_addr_t ofs; 610 611 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 612 M_DEVBUF, M_NOWAIT); 613 KASSERT(cookie); 614 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 615 616 /* Address */ 617 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 618 cookie->wc_tag = ch->ch_memt; 619 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 620 size, &cookie->wc_handle) != 0) 621 goto bad; 622 623 *offsetp = card_addr; 624 cookie->wc_window = -1; 625 } else { 626 int window = card_addr / ch->ch_memsize; 627 KASSERT(window < MEMWIN_16M_MAX); 628 629 cookie->wc_tag = ch->ch_cmemt[window]; 630 ofs = card_addr - window * ch->ch_memsize; 631 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 632 &cookie->wc_handle) != 0) 633 goto bad; 634 635 /* XXX bogus. check window per common memory access. */ 636 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 637 *offsetp = ofs + 0x01000000; /* skip attribute area */ 638 cookie->wc_window = window; 639 } 640 cookie->wc_size = size; 641 *windowp = (int)cookie; 642 643 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 644 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 645 size); 646 647 return (0); 648 bad: 649 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 650 free(cookie, M_DEVBUF); 651 652 return (1); 653 } 654 655 STATIC void 656 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 657 { 658 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 659 660 if (cookie->wc_window != -1) 661 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 662 cookie->wc_size); 663 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 664 free(cookie, M_DEVBUF); 665 } 666 667 STATIC int 668 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 669 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 670 { 671 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 672 673 if (ch->ch_channel == CHANNEL_1) 674 return (1); 675 676 if (start) { 677 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 678 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 679 return (1); 680 } 681 DPRINTF("map %#lx+%#lx\n", start, size); 682 } else { 683 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 684 ch->ch_iobase + ch->ch_iosize - 1, 685 size, align, 0, 0, &pcihp->addr, 686 &pcihp->ioh)) { 687 DPRINTF("couldn't allocate %#lx\n", size); 688 return (1); 689 } 690 pcihp->flags = PCMCIA_IO_ALLOCATED; 691 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 692 } 693 694 pcihp->iot = ch->ch_iot; 695 pcihp->size = size; 696 697 return (0); 698 } 699 700 STATIC int 701 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 702 bus_addr_t offset, 703 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 704 { 705 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 706 #ifdef HD64461PCMCIA_DEBUG 707 static const char *width_names[] = { "auto", "io8", "io16" }; 708 #endif 709 if (ch->ch_channel == CHANNEL_1) 710 return (1); 711 712 hd64461_set_bus_width(CHANNEL_0, width); 713 714 /* fake. drivers init that to -1 and check if it was changed. */ 715 *windowp = 0; 716 717 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 718 width_names[width]); 719 720 return (0); 721 } 722 723 STATIC void 724 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 725 struct pcmcia_io_handle *pcihp) 726 { 727 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 728 729 if (ch->ch_channel == CHANNEL_1) 730 return; 731 732 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 733 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 734 else 735 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 736 737 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 738 } 739 740 STATIC void 741 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 742 { 743 744 /* nothing to do */ 745 } 746 747 STATIC void 748 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 749 { 750 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 751 int channel = ch->ch_channel; 752 bus_addr_t isr, gcr; 753 uint8_t r; 754 int i; 755 756 DPRINTF("enable channel %d\n", channel); 757 isr = HD64461_PCCISR(channel); 758 gcr = HD64461_PCCGCR(channel); 759 760 hd64461pcmcia_power_off(channel); 761 hd64461pcmcia_power_on(channel); 762 763 /* assert reset, set card type to memory */ 764 r = hd64461_reg_read_1(gcr); 765 r |= HD64461_PCCGCR_PCCR; 766 r &= ~HD64461_PCC0GCR_P0PCCT; 767 hd64461_reg_write_1(gcr, r); 768 769 /* 770 * hold RESET at least 10us. 771 */ 772 DELAY_MS(20); 773 774 /* clear the reset flag */ 775 r &= ~HD64461_PCCGCR_PCCR; 776 hd64461_reg_write_1(gcr, r); 777 DELAY_MS(2000); 778 779 /* wait for the chip to finish initializing */ 780 for (i = 0; i < 10000; i++) { 781 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 782 goto reset_ok; 783 DELAY_MS(500); 784 785 if ((i > 5000) && (i % 100 == 99)) 786 printf("."); 787 } 788 printf("reset failed.\n"); 789 hd64461pcmcia_power_off(channel); 790 return; 791 792 reset_ok: 793 /* set Continuous 16-MB Area Mode */ 794 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 795 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 796 797 /* 798 * set Common memory area. 799 */ 800 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 801 802 DPRINTF("OK.\n"); 803 } 804 805 STATIC void 806 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 807 { 808 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 809 int channel = ch->ch_channel; 810 bus_addr_t gcr; 811 uint8_t r; 812 813 DPRINTF("settype channel %d\n", channel); 814 gcr = HD64461_PCCGCR(channel); 815 816 /* set the card type */ 817 r = hd64461_reg_read_1(gcr); 818 if (channel == CHANNEL_0) { 819 if (type == PCMCIA_IFTYPE_IO) 820 r |= HD64461_PCC0GCR_P0PCCT; 821 else 822 r &= ~HD64461_PCC0GCR_P0PCCT; 823 } else { 824 /* reserved bit must be 0 */ 825 r &= ~HD64461_PCC1GCR_RESERVED; 826 } 827 hd64461_reg_write_1(gcr, r); 828 829 DPRINTF("OK.\n"); 830 } 831 832 STATIC void 833 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 834 { 835 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 836 int channel = ch->ch_channel; 837 838 /* dont' disable CSC interrupt */ 839 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 840 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 841 842 /* power down the socket */ 843 hd64461pcmcia_power_off(channel); 844 } 845 846 /* 847 * Card detect 848 */ 849 STATIC void 850 hd64461pcmcia_power_off(enum controller_channel channel) 851 { 852 uint8_t r; 853 uint16_t r16; 854 bus_addr_t scr, gcr; 855 856 gcr = HD64461_PCCGCR(channel); 857 scr = HD64461_PCCSCR(channel); 858 859 /* DRV (external buffer) high level */ 860 r = hd64461_reg_read_1(gcr); 861 r &= ~HD64461_PCCGCR_DRVE; 862 hd64461_reg_write_1(gcr, r); 863 864 /* stop power */ 865 r = hd64461_reg_read_1(scr); 866 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 867 hd64461_reg_write_1(scr, r); 868 r = hd64461_reg_read_1(gcr); 869 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 870 hd64461_reg_write_1(gcr, r); 871 /* 872 * wait 300ms until power fails (Tpf). Then, wait 100ms since 873 * we are changing Vcc (Toff). 874 */ 875 DELAY_MS(300 + 100); 876 877 /* stop clock */ 878 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 879 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 880 HD64461_SYSSTBCR_SPC1ST); 881 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 882 } 883 884 STATIC void 885 hd64461pcmcia_power_on(enum controller_channel channel) 886 { 887 uint8_t r; 888 uint16_t r16; 889 bus_addr_t scr, gcr, isr; 890 891 isr = HD64461_PCCISR(channel); 892 gcr = HD64461_PCCGCR(channel); 893 scr = HD64461_PCCSCR(channel); 894 895 /* 896 * XXX to access attribute memory, this is required. 897 */ 898 if (channel == CHANNEL_0) { 899 /* GPIO Port A XXX Jonanada690 specific? */ 900 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 901 r16 &= ~0xf; 902 r16 |= 0x5; 903 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 904 } 905 906 if (channel == CHANNEL_1) { 907 /* GPIO Port C, Port D -> PCC1 pin 908 * I assume SYSCR[1:0] == 0 909 */ 910 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 911 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 912 } 913 914 /* supply clock */ 915 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 916 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 917 HD64461_SYSSTBCR_SPC1ST); 918 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 919 DELAY_MS(200); 920 921 /* detect voltage and supply VCC */ 922 r = hd64461_reg_read_1(isr); 923 924 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 925 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 926 DPRINTF("5V card\n"); 927 hd64461pcmcia_power(channel, V_5, 1); 928 break; 929 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 930 /* FALLTHROUGH */ 931 case 0: /* x.x / 3.3 / 5 V */ 932 DPRINTF("3.3V card\n"); 933 hd64461pcmcia_power(channel, V_3_3, 1); 934 break; 935 case HD64461_PCCISR_VS1: /* x.x V */ 936 /* FALLTHROUGH */ 937 DPRINTF("x.x V card\n"); 938 hd64461pcmcia_power(channel, V_X_X, 1); 939 return; 940 default: 941 printf("\nunknown Voltage. don't attach.\n"); 942 return; 943 } 944 945 /* 946 * wait 100ms until power raise (Tpr) and 20ms to become 947 * stable (Tsu(Vcc)). 948 * 949 * some machines require some more time to be settled 950 * (300ms is added here). 951 */ 952 DELAY_MS(100 + 20 + 300); 953 954 /* DRV (external buffer) low level */ 955 r = hd64461_reg_read_1(gcr); 956 r |= HD64461_PCCGCR_DRVE; 957 hd64461_reg_write_1(gcr, r); 958 959 /* clear interrupt */ 960 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 961 HD64461_PCC1CSCR_REG8, 0); 962 } 963 964 STATIC enum hd64461pcmcia_event_type 965 detect_card(enum controller_channel channel) 966 { 967 uint8_t r; 968 969 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 970 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 971 972 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 973 DPRINTF("remove\n"); 974 return EVENT_REMOVE; 975 } 976 if (r == 0) { 977 DPRINTF("insert\n"); 978 return EVENT_INSERT; 979 } 980 DPRINTF("transition\n"); 981 982 return EVENT_NONE; 983 } 984 985 /* 986 * Memory window access ops. 987 */ 988 STATIC void 989 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 990 enum memory_window_mode mode) 991 { 992 bus_addr_t a = HD64461_PCCGCR(channel); 993 uint8_t r = hd64461_reg_read_1(a); 994 995 r &= ~HD64461_PCCGCR_MMOD; 996 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 997 HD64461_PCCGCR_MMOD_32M; 998 hd64461_reg_write_1(a, r); 999 } 1000 1001 STATIC void 1002 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1003 enum memory_window_16 window) 1004 { 1005 bus_addr_t a = HD64461_PCCGCR(channel); 1006 uint8_t r; 1007 1008 r = hd64461_reg_read_1(a); 1009 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1010 1011 switch (window) { 1012 case MEMWIN_16M_COMMON_0: 1013 break; 1014 case MEMWIN_16M_COMMON_1: 1015 r |= HD64461_PCCGCR_PA24; 1016 break; 1017 case MEMWIN_16M_COMMON_2: 1018 r |= HD64461_PCCGCR_PA25; 1019 break; 1020 case MEMWIN_16M_COMMON_3: 1021 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1022 break; 1023 } 1024 1025 hd64461_reg_write_1(a, r); 1026 } 1027 1028 #if unused 1029 STATIC void 1030 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1031 { 1032 bus_addr_t a = HD64461_PCCGCR(channel); 1033 uint8_t r; 1034 1035 r = hd64461_reg_read_1(a); 1036 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1037 1038 switch (window) { 1039 case MEMWIN_32M_ATTR: 1040 break; 1041 case MEMWIN_32M_COMMON_0: 1042 r |= HD64461_PCCGCR_PREG; 1043 break; 1044 case MEMWIN_32M_COMMON_1: 1045 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1046 break; 1047 } 1048 1049 hd64461_reg_write_1(a, r); 1050 } 1051 #endif 1052 1053 STATIC void 1054 hd64461_set_bus_width(enum controller_channel channel, int width) 1055 { 1056 unsigned int area, buswidth; 1057 uint16_t bcr2; 1058 1059 if (channel == CHANNEL_0) 1060 area = BCR2_AREA6_SHIFT; 1061 else 1062 area = BCR2_AREA5_SHIFT; 1063 1064 if (width == PCMCIA_WIDTH_IO8) 1065 buswidth = BCR2_AREA_WIDTH_8; 1066 else 1067 buswidth = BCR2_AREA_WIDTH_16; 1068 1069 bcr2 = _reg_read_2(SH3_BCR2); 1070 1071 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1072 bcr2 |= buswidth << area; 1073 1074 _reg_write_2(SH3_BCR2, bcr2); 1075 } 1076 1077 STATIC void 1078 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1079 { 1080 struct hpcsh_bus_space *hbs = (void *)t; 1081 1082 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1083 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1084 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1085 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1086 } 1087 1088 #ifdef HD64461PCMCIA_DEBUG 1089 STATIC void 1090 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1091 { 1092 uint8_t r8; 1093 1094 dbg_banner_function(); 1095 /* 1096 * PCC0 1097 */ 1098 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1099 printf("PCC0 Interface Status Register\n"); 1100 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1101 1102 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1103 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1104 _(P0BVD2);_(P0BVD1); 1105 #undef _ 1106 printf("\n"); 1107 1108 printf("PCC0 General Control Register\n"); 1109 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1110 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1111 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1112 _(P0PA25);_(P0PA24);_(P0REG); 1113 #undef _ 1114 printf("\n"); 1115 1116 printf("PCC0 Card Status Change Register\n"); 1117 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1118 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1119 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1120 #undef _ 1121 printf("\n"); 1122 1123 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1124 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1125 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1126 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1127 #undef _ 1128 printf("\ninterrupt type: "); 1129 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1130 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1131 printf("none\n"); 1132 break; 1133 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1134 printf("level\n"); 1135 break; 1136 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1137 printf("falling edge\n"); 1138 break; 1139 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1140 printf("rising edge\n"); 1141 break; 1142 } 1143 1144 printf("PCC0 Software Control Register\n"); 1145 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1146 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1147 _(P0VCC1);_(P0SWP); 1148 #undef _ 1149 printf("\n"); 1150 1151 /* 1152 * PCC1 1153 */ 1154 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1155 printf("PCC1 Interface Status Register\n"); 1156 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1157 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1158 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1159 _(P1BVD2);_(P1BVD1); 1160 #undef _ 1161 printf("\n"); 1162 1163 printf("PCC1 General Contorol Register\n"); 1164 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1165 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1166 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1167 #undef _ 1168 printf("\n"); 1169 1170 printf("PCC1 Card Status Change Register\n"); 1171 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1172 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1173 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1174 #undef _ 1175 printf("\n"); 1176 1177 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1178 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1179 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1180 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1181 #undef _ 1182 printf("\n"); 1183 1184 printf("PCC1 Software Control Register\n"); 1185 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1186 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1187 _(P1VCC1);_(P1SWP); 1188 #undef _ 1189 printf("\n"); 1190 1191 /* 1192 * General Control 1193 */ 1194 printf("[General Control]\n"); 1195 printf("PCC0 Output pins Control Register\n"); 1196 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1197 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1198 _(P0DEPLUP);_(P0AEPLUP); 1199 #undef _ 1200 printf("\n"); 1201 1202 printf("PCC1 Output pins Control Register\n"); 1203 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1204 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1205 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1206 #undef _ 1207 printf("\n"); 1208 1209 printf("PC Card General Control Register\n"); 1210 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1211 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1212 _(PSSDIR);_(PSSRDWR); 1213 #undef _ 1214 printf("\n"); 1215 1216 dbg_banner_line(); 1217 } 1218 #endif /* HD64461PCMCIA_DEBUG */ 1219
Indexes created Thu Oct 02 01:09:59 GMT 2025