hd64461pcmcia.c revision 1.41.6.2
1 /* $NetBSD: hd64461pcmcia.c,v 1.41.6.2 2008/06/02 13:22:12 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.41.6.2 2008/06/02 13:22:12 mjf Exp $"); 34 35 #include "opt_hd64461pcmcia.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 #include <sys/boot_flag.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 53 #include <hpcsh/dev/hd64461/hd64461reg.h> 54 #include <hpcsh/dev/hd64461/hd64461var.h> 55 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 56 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 58 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 59 60 #include "locators.h" 61 62 #ifdef HD64461PCMCIA_DEBUG 63 #define DPRINTF_ENABLE 64 #define DPRINTF_DEBUG hd64461pcmcia_debug 65 #endif 66 #include <machine/debug.h> 67 68 enum controller_channel { 69 CHANNEL_0 = 0, 70 CHANNEL_1 = 1, 71 CHANNEL_MAX = 2 72 }; 73 74 enum memory_window_mode { 75 MEMWIN_16M_MODE, 76 MEMWIN_32M_MODE 77 }; 78 79 enum memory_window_16 { 80 MEMWIN_16M_COMMON_0, 81 MEMWIN_16M_COMMON_1, 82 MEMWIN_16M_COMMON_2, 83 MEMWIN_16M_COMMON_3, 84 }; 85 #define MEMWIN_16M_MAX 4 86 87 enum memory_window_32 { 88 MEMWIN_32M_ATTR, 89 MEMWIN_32M_COMMON_0, 90 MEMWIN_32M_COMMON_1, 91 }; 92 #define MEMWIN_32M_MAX 3 93 94 enum hd64461pcmcia_event_type { 95 EVENT_NONE, 96 EVENT_INSERT, 97 EVENT_REMOVE, 98 }; 99 #define EVENT_QUEUE_MAX 5 100 101 struct hd64461pcmcia_softc; /* forward declaration */ 102 103 struct hd64461pcmcia_window_cookie { 104 bus_space_tag_t wc_tag; 105 bus_space_handle_t wc_handle; 106 int wc_size; 107 int wc_window; 108 }; 109 110 struct hd64461pcmcia_channel { 111 struct hd64461pcmcia_softc *ch_parent; 112 device_t ch_pcmcia; 113 enum controller_channel ch_channel; 114 115 /* memory space */ 116 enum memory_window_mode ch_memory_window_mode; 117 bus_space_tag_t ch_memt; 118 bus_space_handle_t ch_memh; 119 bus_addr_t ch_membase_addr; 120 bus_size_t ch_memsize; 121 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 122 123 /* I/O space */ 124 bus_space_tag_t ch_iot; 125 bus_addr_t ch_iobase; 126 bus_size_t ch_iosize; 127 128 /* card interrupt */ 129 int (*ch_ih_card_func)(void *); 130 void *ch_ih_card_arg; 131 int ch_attached; 132 }; 133 134 struct hd64461pcmcia_event { 135 int __queued; 136 enum hd64461pcmcia_event_type pe_type; 137 struct hd64461pcmcia_channel *pe_ch; 138 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 139 }; 140 141 struct hd64461pcmcia_softc { 142 device_t sc_dev; 143 144 enum hd64461_module_id sc_module_id; 145 int sc_shutdown; 146 147 /* CSC event */ 148 lwp_t *sc_event_thread; 149 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 150 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 151 152 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 153 }; 154 155 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 156 struct pcmcia_mem_handle *); 157 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 158 struct pcmcia_mem_handle *); 159 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 160 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 161 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 162 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 163 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 164 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 165 struct pcmcia_io_handle *); 166 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_io_handle *, int *); 168 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 169 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 170 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 171 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 172 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 173 struct pcmcia_function *, int, int (*)(void *), void *); 174 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 175 void *); 176 177 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 178 hd64461pcmcia_chip_mem_alloc, 179 hd64461pcmcia_chip_mem_free, 180 hd64461pcmcia_chip_mem_map, 181 hd64461pcmcia_chip_mem_unmap, 182 hd64461pcmcia_chip_io_alloc, 183 hd64461pcmcia_chip_io_free, 184 hd64461pcmcia_chip_io_map, 185 hd64461pcmcia_chip_io_unmap, 186 hd64461pcmcia_chip_intr_establish, 187 hd64461pcmcia_chip_intr_disestablish, 188 hd64461pcmcia_chip_socket_enable, 189 hd64461pcmcia_chip_socket_disable, 190 hd64461pcmcia_chip_socket_settype, 191 }; 192 193 STATIC int hd64461pcmcia_match(device_t, cfdata_t, void *); 194 STATIC void hd64461pcmcia_attach(device_t, device_t, void *); 195 STATIC int hd64461pcmcia_print(void *, const char *); 196 STATIC int hd64461pcmcia_submatch(device_t, cfdata_t, const int *, void *); 197 198 CFATTACH_DECL_NEW(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 199 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 200 201 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 202 enum controller_channel); 203 /* hot plug */ 204 STATIC void hd64461pcmcia_event_thread(void *); 205 STATIC void queue_event(struct hd64461pcmcia_channel *, 206 enum hd64461pcmcia_event_type); 207 /* interrupt handler */ 208 STATIC int hd64461pcmcia_channel0_intr(void *); 209 STATIC int hd64461pcmcia_channel1_intr(void *); 210 /* card status */ 211 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 212 STATIC void hd64461pcmcia_power_off(enum controller_channel); 213 STATIC void hd64461pcmcia_power_on(enum controller_channel); 214 /* memory window access ops */ 215 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 216 enum memory_window_mode)__attribute__((__unused__)); 217 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 218 enum memory_window_16); 219 /* bus width */ 220 STATIC void hd64461_set_bus_width(enum controller_channel, int); 221 #ifdef HD64461PCMCIA_DEBUG 222 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 223 #endif 224 /* fix SH3 Area[56] bug */ 225 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 226 #define _BUS_SPACE_ACCESS_HOOK() \ 227 do { \ 228 uint8_t dummy __attribute__((__unused__)) = \ 229 *(volatile uint8_t *)0xba000000; \ 230 } while (/*CONSTCOND*/0) 231 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 232 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 233 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 234 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 235 #undef _BUS_SPACE_ACCESS_HOOK 236 237 #define DELAY_MS(x) delay((x) * 1000) 238 239 STATIC int 240 hd64461pcmcia_match(device_t parent, cfdata_t cf, void *aux) 241 { 242 struct hd64461_attach_args *ha = aux; 243 244 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 245 } 246 247 STATIC void 248 hd64461pcmcia_attach(device_t parent, device_t self, void *aux) 249 { 250 struct hd64461_attach_args *ha = aux; 251 struct hd64461pcmcia_softc *sc; 252 int error; 253 254 sc = device_private(self); 255 sc->sc_dev = self; 256 257 sc->sc_module_id = ha->ha_module_id; 258 259 aprint_naive("\n"); 260 aprint_normal("\n"); 261 262 #ifdef HD64461PCMCIA_DEBUG 263 hd64461pcmcia_info(sc); 264 #endif 265 /* Channel 0/1 common CSC event queue */ 266 SIMPLEQ_INIT (&sc->sc_event_head); 267 error = kthread_create(PRI_NONE, 0, NULL, 268 hd64461pcmcia_event_thread, sc, 269 &sc->sc_event_thread, 270 "%s", device_xname(self)); 271 KASSERT(error == 0); 272 273 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 274 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 275 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 276 #else 277 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 278 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 279 #endif 280 } 281 282 STATIC void 283 hd64461pcmcia_event_thread(void *arg) 284 { 285 struct hd64461pcmcia_softc *sc = arg; 286 struct hd64461pcmcia_event *pe; 287 int s; 288 289 while (!sc->sc_shutdown) { 290 tsleep(sc, PWAIT, "CSC wait", 0); 291 s = splhigh(); 292 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 293 splx(s); 294 switch (pe->pe_type) { 295 default: 296 printf("%s: unknown event.\n", __func__); 297 break; 298 case EVENT_INSERT: 299 DPRINTF("insert event.\n"); 300 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 301 break; 302 case EVENT_REMOVE: 303 DPRINTF("remove event.\n"); 304 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 305 DETACH_FORCE); 306 break; 307 } 308 s = splhigh(); 309 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 310 pe->__queued = 0; 311 } 312 splx(s); 313 } 314 /* NOTREACHED */ 315 } 316 317 STATIC int 318 hd64461pcmcia_print(void *arg, const char *pnp) 319 { 320 321 if (pnp) 322 aprint_normal("pcmcia at %s", pnp); 323 324 return (UNCONF); 325 } 326 327 STATIC int 328 hd64461pcmcia_submatch(device_t parent, cfdata_t cf, 329 const int *ldesc, void *aux) 330 { 331 struct pcmciabus_attach_args *paa = aux; 332 struct hd64461pcmcia_channel *ch = 333 (struct hd64461pcmcia_channel *)paa->pch; 334 335 if (ch->ch_channel == CHANNEL_0) { 336 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 337 PCMCIABUSCF_CONTROLLER_DEFAULT && 338 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 339 return 0; 340 } else { 341 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 342 PCMCIABUSCF_CONTROLLER_DEFAULT && 343 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 344 return 0; 345 } 346 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 347 348 return (config_match(parent, cf, aux)); 349 } 350 351 STATIC void 352 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 353 enum controller_channel channel) 354 { 355 device_t parent = sc->sc_dev; 356 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 357 struct pcmciabus_attach_args paa; 358 bus_addr_t membase; 359 int i; 360 361 ch->ch_parent = sc; 362 ch->ch_channel = channel; 363 364 /* 365 * Continuous 16-MB Area Mode 366 */ 367 /* Attibute/Common memory extent */ 368 membase = (channel == CHANNEL_0) 369 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 370 371 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 372 membase, 0x01000000); /* 16MB */ 373 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 374 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 375 &ch->ch_memh); 376 fixup_sh3_pcmcia_area(ch->ch_memt); 377 378 /* Common memory space extent */ 379 ch->ch_memsize = 0x01000000; 380 for (i = 0; i < MEMWIN_16M_MAX; i++) { 381 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 382 membase + 0x01000000, 383 ch->ch_memsize); 384 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 385 } 386 387 /* I/O port extent and interrupt staff */ 388 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 389 390 if (channel == CHANNEL_0) { 391 ch->ch_iobase = 0; 392 ch->ch_iosize = HD64461_PCC0_IOSIZE; 393 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 394 HD64461_PCC0_IOBASE, 395 ch->ch_iosize); 396 fixup_sh3_pcmcia_area(ch->ch_iot); 397 398 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 399 hd64461pcmcia_channel0_intr, ch); 400 } else { 401 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 402 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 403 hd64461pcmcia_channel1_intr, ch); 404 } 405 406 paa.paa_busname = "pcmcia"; 407 paa.pch = (pcmcia_chipset_handle_t)ch; 408 paa.iobase = ch->ch_iobase; 409 paa.iosize = ch->ch_iosize; 410 411 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 412 hd64461pcmcia_print, hd64461pcmcia_submatch); 413 414 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 415 ch->ch_attached = 1; 416 pcmcia_card_attach(ch->ch_pcmcia); 417 } 418 } 419 420 STATIC int 421 hd64461pcmcia_channel0_intr(void *arg) 422 { 423 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 424 uint8_t r; 425 int ret = 0; 426 427 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 428 /* clear interrtupt (edge source only) */ 429 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 430 431 if (r & HD64461_PCC0CSCR_P0IREQ) { 432 if (ch->ch_ih_card_func) { 433 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 434 } else 435 DPRINTF("spurious IREQ interrupt.\n"); 436 } 437 438 if (r & HD64461_PCC0CSCR_P0CDC) 439 queue_event(ch, detect_card(ch->ch_channel)); 440 441 return ret; 442 } 443 444 STATIC int 445 hd64461pcmcia_channel1_intr(void *arg) 446 { 447 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 448 uint8_t r; 449 int ret = 0; 450 451 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 452 /* clear interrtupt */ 453 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 454 455 if (r & HD64461_PCC1CSCR_P1RC) { 456 if (ch->ch_ih_card_func) 457 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 458 else 459 DPRINTF("spurious READY interrupt.\n"); 460 } 461 462 if (r & HD64461_PCC1CSCR_P1CDC) 463 queue_event(ch, detect_card(ch->ch_channel)); 464 465 return ret; 466 } 467 468 STATIC void 469 queue_event(struct hd64461pcmcia_channel *ch, 470 enum hd64461pcmcia_event_type type) 471 { 472 struct hd64461pcmcia_event *pe, *pool; 473 struct hd64461pcmcia_softc *sc = ch->ch_parent; 474 int i; 475 int s = splhigh(); 476 477 if (type == EVENT_NONE) 478 goto out; 479 480 pe = 0; 481 pool = sc->sc_event_pool; 482 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 483 if (!pool[i].__queued) { 484 pe = &pool[i]; 485 break; 486 } 487 } 488 489 if (pe == 0) { 490 printf("%s: event FIFO overflow (max %d).\n", __func__, 491 EVENT_QUEUE_MAX); 492 goto out; 493 } 494 495 if ((ch->ch_attached && (type == EVENT_INSERT)) || 496 (!ch->ch_attached && (type == EVENT_REMOVE))) { 497 DPRINTF("spurious CSC interrupt.\n"); 498 goto out; 499 } 500 501 ch->ch_attached = (type == EVENT_INSERT); 502 pe->__queued = 1; 503 pe->pe_type = type; 504 pe->pe_ch = ch; 505 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 506 wakeup(sc); 507 out: 508 splx(s); 509 } 510 511 /* 512 * interface for pcmcia driver. 513 */ 514 STATIC void * 515 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 516 struct pcmcia_function *pf, 517 int ipl, int (*ih_func)(void *), void *ih_arg) 518 { 519 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 520 int channel = ch->ch_channel; 521 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 522 int s = splhigh(); 523 uint8_t r; 524 525 ch->ch_ih_card_func = ih_func; 526 ch->ch_ih_card_arg = ih_arg; 527 528 /* enable card interrupt */ 529 r = hd64461_reg_read_1(cscier); 530 if (channel == CHANNEL_0) { 531 /* set level mode */ 532 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 533 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 534 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 535 } else { 536 /* READY-pin LOW to HIGH changes generates interrupt */ 537 r |= HD64461_PCC1CSCIER_P1RE; 538 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 539 } 540 hd64461_reg_write_1(cscier, r); 541 542 splx(s); 543 544 return (void *)ih_func; 545 } 546 547 STATIC void 548 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 549 { 550 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 551 int channel = ch->ch_channel; 552 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 553 int s = splhigh(); 554 uint8_t r; 555 556 /* disable card interrupt */ 557 r = hd64461_reg_read_1(cscier); 558 if (channel == CHANNEL_0) { 559 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 560 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 561 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 562 } else { 563 r &= ~HD64461_PCC1CSCIER_P1RE; 564 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 565 } 566 hd64461_reg_write_1(cscier, r); 567 568 ch->ch_ih_card_func = 0; 569 570 splx(s); 571 } 572 573 STATIC int 574 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 575 struct pcmcia_mem_handle *pcmhp) 576 { 577 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 578 579 pcmhp->memt = ch->ch_memt; 580 pcmhp->addr = ch->ch_membase_addr; 581 pcmhp->memh = ch->ch_memh; 582 pcmhp->size = size; 583 pcmhp->realsize = size; 584 585 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 586 587 return (0); 588 } 589 590 STATIC void 591 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 592 struct pcmcia_mem_handle *pcmhp) 593 { 594 /* nothing to do */ 595 } 596 597 STATIC int 598 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 599 bus_addr_t card_addr, 600 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 601 bus_size_t *offsetp, int *windowp) 602 { 603 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 604 struct hd64461pcmcia_window_cookie *cookie; 605 bus_addr_t ofs; 606 607 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 608 M_DEVBUF, M_NOWAIT); 609 KASSERT(cookie); 610 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 611 612 /* Address */ 613 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 614 cookie->wc_tag = ch->ch_memt; 615 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 616 size, &cookie->wc_handle) != 0) 617 goto bad; 618 619 *offsetp = card_addr; 620 cookie->wc_window = -1; 621 } else { 622 int window = card_addr / ch->ch_memsize; 623 KASSERT(window < MEMWIN_16M_MAX); 624 625 cookie->wc_tag = ch->ch_cmemt[window]; 626 ofs = card_addr - window * ch->ch_memsize; 627 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 628 &cookie->wc_handle) != 0) 629 goto bad; 630 631 /* XXX bogus. check window per common memory access. */ 632 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 633 *offsetp = ofs + 0x01000000; /* skip attribute area */ 634 cookie->wc_window = window; 635 } 636 cookie->wc_size = size; 637 *windowp = (int)cookie; 638 639 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 640 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 641 size); 642 643 return (0); 644 bad: 645 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 646 free(cookie, M_DEVBUF); 647 648 return (1); 649 } 650 651 STATIC void 652 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 653 { 654 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 655 656 if (cookie->wc_window != -1) 657 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 658 cookie->wc_size); 659 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 660 free(cookie, M_DEVBUF); 661 } 662 663 STATIC int 664 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 665 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 666 { 667 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 668 669 if (ch->ch_channel == CHANNEL_1) 670 return (1); 671 672 if (start) { 673 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 674 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 675 return (1); 676 } 677 DPRINTF("map %#lx+%#lx\n", start, size); 678 } else { 679 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 680 ch->ch_iobase + ch->ch_iosize - 1, 681 size, align, 0, 0, &pcihp->addr, 682 &pcihp->ioh)) { 683 DPRINTF("couldn't allocate %#lx\n", size); 684 return (1); 685 } 686 pcihp->flags = PCMCIA_IO_ALLOCATED; 687 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 688 } 689 690 pcihp->iot = ch->ch_iot; 691 pcihp->size = size; 692 693 return (0); 694 } 695 696 STATIC int 697 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 698 bus_addr_t offset, 699 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 700 { 701 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 702 #ifdef HD64461PCMCIA_DEBUG 703 static const char *width_names[] = { "auto", "io8", "io16" }; 704 #endif 705 if (ch->ch_channel == CHANNEL_1) 706 return (1); 707 708 hd64461_set_bus_width(CHANNEL_0, width); 709 710 /* fake. drivers init that to -1 and check if it was changed. */ 711 *windowp = 0; 712 713 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 714 width_names[width]); 715 716 return (0); 717 } 718 719 STATIC void 720 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 721 struct pcmcia_io_handle *pcihp) 722 { 723 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 724 725 if (ch->ch_channel == CHANNEL_1) 726 return; 727 728 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 729 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 730 else 731 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 732 733 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 734 } 735 736 STATIC void 737 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 738 { 739 740 /* nothing to do */ 741 } 742 743 STATIC void 744 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 745 { 746 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 747 int channel = ch->ch_channel; 748 bus_addr_t isr, gcr; 749 uint8_t r; 750 int i; 751 752 DPRINTF("enable channel %d\n", channel); 753 isr = HD64461_PCCISR(channel); 754 gcr = HD64461_PCCGCR(channel); 755 756 hd64461pcmcia_power_off(channel); 757 hd64461pcmcia_power_on(channel); 758 759 /* assert reset, set card type to memory */ 760 r = hd64461_reg_read_1(gcr); 761 r |= HD64461_PCCGCR_PCCR; 762 r &= ~HD64461_PCC0GCR_P0PCCT; 763 hd64461_reg_write_1(gcr, r); 764 765 /* 766 * hold RESET at least 10us. 767 */ 768 DELAY_MS(20); 769 770 /* clear the reset flag */ 771 r &= ~HD64461_PCCGCR_PCCR; 772 hd64461_reg_write_1(gcr, r); 773 DELAY_MS(2000); 774 775 /* wait for the chip to finish initializing */ 776 for (i = 0; i < 10000; i++) { 777 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 778 goto reset_ok; 779 DELAY_MS(500); 780 781 if ((i > 5000) && (i % 100 == 99)) 782 printf("."); 783 } 784 printf("reset failed.\n"); 785 hd64461pcmcia_power_off(channel); 786 return; 787 788 reset_ok: 789 /* set Continuous 16-MB Area Mode */ 790 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 791 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 792 793 /* 794 * set Common memory area. 795 */ 796 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 797 798 DPRINTF("OK.\n"); 799 } 800 801 STATIC void 802 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 803 { 804 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 805 int channel = ch->ch_channel; 806 bus_addr_t gcr; 807 uint8_t r; 808 809 DPRINTF("settype channel %d\n", channel); 810 gcr = HD64461_PCCGCR(channel); 811 812 /* set the card type */ 813 r = hd64461_reg_read_1(gcr); 814 if (channel == CHANNEL_0) { 815 if (type == PCMCIA_IFTYPE_IO) 816 r |= HD64461_PCC0GCR_P0PCCT; 817 else 818 r &= ~HD64461_PCC0GCR_P0PCCT; 819 } else { 820 /* reserved bit must be 0 */ 821 r &= ~HD64461_PCC1GCR_RESERVED; 822 } 823 hd64461_reg_write_1(gcr, r); 824 825 DPRINTF("OK.\n"); 826 } 827 828 STATIC void 829 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 830 { 831 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 832 int channel = ch->ch_channel; 833 834 /* dont' disable CSC interrupt */ 835 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 836 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 837 838 /* power down the socket */ 839 hd64461pcmcia_power_off(channel); 840 } 841 842 /* 843 * Card detect 844 */ 845 STATIC void 846 hd64461pcmcia_power_off(enum controller_channel channel) 847 { 848 uint8_t r; 849 uint16_t r16; 850 bus_addr_t scr, gcr; 851 852 gcr = HD64461_PCCGCR(channel); 853 scr = HD64461_PCCSCR(channel); 854 855 /* DRV (external buffer) high level */ 856 r = hd64461_reg_read_1(gcr); 857 r &= ~HD64461_PCCGCR_DRVE; 858 hd64461_reg_write_1(gcr, r); 859 860 /* stop power */ 861 r = hd64461_reg_read_1(scr); 862 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 863 hd64461_reg_write_1(scr, r); 864 r = hd64461_reg_read_1(gcr); 865 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 866 hd64461_reg_write_1(gcr, r); 867 /* 868 * wait 300ms until power fails (Tpf). Then, wait 100ms since 869 * we are changing Vcc (Toff). 870 */ 871 DELAY_MS(300 + 100); 872 873 /* stop clock */ 874 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 875 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 876 HD64461_SYSSTBCR_SPC1ST); 877 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 878 } 879 880 STATIC void 881 hd64461pcmcia_power_on(enum controller_channel channel) 882 { 883 uint8_t r; 884 uint16_t r16; 885 bus_addr_t scr, gcr, isr; 886 887 isr = HD64461_PCCISR(channel); 888 gcr = HD64461_PCCGCR(channel); 889 scr = HD64461_PCCSCR(channel); 890 891 /* 892 * XXX to access attribute memory, this is required. 893 */ 894 if (channel == CHANNEL_0) { 895 /* GPIO Port A XXX Jonanada690 specific? */ 896 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 897 r16 &= ~0xf; 898 r16 |= 0x5; 899 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 900 } 901 902 if (channel == CHANNEL_1) { 903 /* GPIO Port C, Port D -> PCC1 pin 904 * I assume SYSCR[1:0] == 0 905 */ 906 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 907 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 908 } 909 910 /* supply clock */ 911 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 912 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 913 HD64461_SYSSTBCR_SPC1ST); 914 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 915 DELAY_MS(200); 916 917 /* detect voltage and supply VCC */ 918 r = hd64461_reg_read_1(isr); 919 920 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 921 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 922 DPRINTF("5V card\n"); 923 hd64461pcmcia_power(channel, V_5, 1); 924 break; 925 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 926 /* FALLTHROUGH */ 927 case 0: /* x.x / 3.3 / 5 V */ 928 DPRINTF("3.3V card\n"); 929 hd64461pcmcia_power(channel, V_3_3, 1); 930 break; 931 case HD64461_PCCISR_VS1: /* x.x V */ 932 /* FALLTHROUGH */ 933 DPRINTF("x.x V card\n"); 934 hd64461pcmcia_power(channel, V_X_X, 1); 935 return; 936 default: 937 printf("\nunknown Voltage. don't attach.\n"); 938 return; 939 } 940 941 /* 942 * wait 100ms until power raise (Tpr) and 20ms to become 943 * stable (Tsu(Vcc)). 944 * 945 * some machines require some more time to be settled 946 * (300ms is added here). 947 */ 948 DELAY_MS(100 + 20 + 300); 949 950 /* DRV (external buffer) low level */ 951 r = hd64461_reg_read_1(gcr); 952 r |= HD64461_PCCGCR_DRVE; 953 hd64461_reg_write_1(gcr, r); 954 955 /* clear interrupt */ 956 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 957 HD64461_PCC1CSCR_REG8, 0); 958 } 959 960 STATIC enum hd64461pcmcia_event_type 961 detect_card(enum controller_channel channel) 962 { 963 uint8_t r; 964 965 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 966 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 967 968 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 969 DPRINTF("remove\n"); 970 return EVENT_REMOVE; 971 } 972 if (r == 0) { 973 DPRINTF("insert\n"); 974 return EVENT_INSERT; 975 } 976 DPRINTF("transition\n"); 977 978 return EVENT_NONE; 979 } 980 981 /* 982 * Memory window access ops. 983 */ 984 STATIC void 985 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 986 enum memory_window_mode mode) 987 { 988 bus_addr_t a = HD64461_PCCGCR(channel); 989 uint8_t r = hd64461_reg_read_1(a); 990 991 r &= ~HD64461_PCCGCR_MMOD; 992 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 993 HD64461_PCCGCR_MMOD_32M; 994 hd64461_reg_write_1(a, r); 995 } 996 997 STATIC void 998 hd64461pcmcia_memory_window_16(enum controller_channel channel, 999 enum memory_window_16 window) 1000 { 1001 bus_addr_t a = HD64461_PCCGCR(channel); 1002 uint8_t r; 1003 1004 r = hd64461_reg_read_1(a); 1005 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1006 1007 switch (window) { 1008 case MEMWIN_16M_COMMON_0: 1009 break; 1010 case MEMWIN_16M_COMMON_1: 1011 r |= HD64461_PCCGCR_PA24; 1012 break; 1013 case MEMWIN_16M_COMMON_2: 1014 r |= HD64461_PCCGCR_PA25; 1015 break; 1016 case MEMWIN_16M_COMMON_3: 1017 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1018 break; 1019 } 1020 1021 hd64461_reg_write_1(a, r); 1022 } 1023 1024 #if unused 1025 STATIC void 1026 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1027 { 1028 bus_addr_t a = HD64461_PCCGCR(channel); 1029 uint8_t r; 1030 1031 r = hd64461_reg_read_1(a); 1032 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1033 1034 switch (window) { 1035 case MEMWIN_32M_ATTR: 1036 break; 1037 case MEMWIN_32M_COMMON_0: 1038 r |= HD64461_PCCGCR_PREG; 1039 break; 1040 case MEMWIN_32M_COMMON_1: 1041 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1042 break; 1043 } 1044 1045 hd64461_reg_write_1(a, r); 1046 } 1047 #endif 1048 1049 STATIC void 1050 hd64461_set_bus_width(enum controller_channel channel, int width) 1051 { 1052 unsigned int area, buswidth; 1053 uint16_t bcr2; 1054 1055 if (channel == CHANNEL_0) 1056 area = BCR2_AREA6_SHIFT; 1057 else 1058 area = BCR2_AREA5_SHIFT; 1059 1060 if (width == PCMCIA_WIDTH_IO8) 1061 buswidth = BCR2_AREA_WIDTH_8; 1062 else 1063 buswidth = BCR2_AREA_WIDTH_16; 1064 1065 bcr2 = _reg_read_2(SH3_BCR2); 1066 1067 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1068 bcr2 |= buswidth << area; 1069 1070 _reg_write_2(SH3_BCR2, bcr2); 1071 } 1072 1073 STATIC void 1074 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1075 { 1076 struct hpcsh_bus_space *hbs = (void *)t; 1077 1078 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1079 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1080 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1081 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1082 } 1083 1084 #ifdef HD64461PCMCIA_DEBUG 1085 STATIC void 1086 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1087 { 1088 uint8_t r8; 1089 1090 dbg_banner_function(); 1091 /* 1092 * PCC0 1093 */ 1094 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1095 printf("PCC0 Interface Status Register\n"); 1096 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1097 1098 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1099 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1100 _(P0BVD2);_(P0BVD1); 1101 #undef _ 1102 printf("\n"); 1103 1104 printf("PCC0 General Control Register\n"); 1105 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1106 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1107 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1108 _(P0PA25);_(P0PA24);_(P0REG); 1109 #undef _ 1110 printf("\n"); 1111 1112 printf("PCC0 Card Status Change Register\n"); 1113 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1114 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1115 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1116 #undef _ 1117 printf("\n"); 1118 1119 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1120 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1121 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1122 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1123 #undef _ 1124 printf("\ninterrupt type: "); 1125 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1126 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1127 printf("none\n"); 1128 break; 1129 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1130 printf("level\n"); 1131 break; 1132 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1133 printf("falling edge\n"); 1134 break; 1135 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1136 printf("rising edge\n"); 1137 break; 1138 } 1139 1140 printf("PCC0 Software Control Register\n"); 1141 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1142 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1143 _(P0VCC1);_(P0SWP); 1144 #undef _ 1145 printf("\n"); 1146 1147 /* 1148 * PCC1 1149 */ 1150 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1151 printf("PCC1 Interface Status Register\n"); 1152 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1153 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1154 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1155 _(P1BVD2);_(P1BVD1); 1156 #undef _ 1157 printf("\n"); 1158 1159 printf("PCC1 General Contorol Register\n"); 1160 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1161 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1162 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1163 #undef _ 1164 printf("\n"); 1165 1166 printf("PCC1 Card Status Change Register\n"); 1167 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1168 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1169 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1170 #undef _ 1171 printf("\n"); 1172 1173 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1174 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1175 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1176 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1177 #undef _ 1178 printf("\n"); 1179 1180 printf("PCC1 Software Control Register\n"); 1181 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1182 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1183 _(P1VCC1);_(P1SWP); 1184 #undef _ 1185 printf("\n"); 1186 1187 /* 1188 * General Control 1189 */ 1190 printf("[General Control]\n"); 1191 printf("PCC0 Output pins Control Register\n"); 1192 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1193 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1194 _(P0DEPLUP);_(P0AEPLUP); 1195 #undef _ 1196 printf("\n"); 1197 1198 printf("PCC1 Output pins Control Register\n"); 1199 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1200 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1201 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1202 #undef _ 1203 printf("\n"); 1204 1205 printf("PC Card General Control Register\n"); 1206 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1207 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1208 _(PSSDIR);_(PSSRDWR); 1209 #undef _ 1210 printf("\n"); 1211 1212 dbg_banner_line(); 1213 } 1214 #endif /* HD64461PCMCIA_DEBUG */ 1215
Indexes created Sun Oct 19 02:09:48 GMT 2025