hd64461pcmcia.c revision 1.42
1 /* $NetBSD: hd64461pcmcia.c,v 1.42 2008/03/27 23:57:21 uwe Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.42 2008/03/27 23:57:21 uwe Exp $"); 41 42 #include "opt_hd64461pcmcia.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/kthread.h> 49 #include <sys/boot_flag.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 65 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 66 67 #include "locators.h" 68 69 #ifdef HD64461PCMCIA_DEBUG 70 #define DPRINTF_ENABLE 71 #define DPRINTF_DEBUG hd64461pcmcia_debug 72 #endif 73 #include <machine/debug.h> 74 75 enum controller_channel { 76 CHANNEL_0 = 0, 77 CHANNEL_1 = 1, 78 CHANNEL_MAX = 2 79 }; 80 81 enum memory_window_mode { 82 MEMWIN_16M_MODE, 83 MEMWIN_32M_MODE 84 }; 85 86 enum memory_window_16 { 87 MEMWIN_16M_COMMON_0, 88 MEMWIN_16M_COMMON_1, 89 MEMWIN_16M_COMMON_2, 90 MEMWIN_16M_COMMON_3, 91 }; 92 #define MEMWIN_16M_MAX 4 93 94 enum memory_window_32 { 95 MEMWIN_32M_ATTR, 96 MEMWIN_32M_COMMON_0, 97 MEMWIN_32M_COMMON_1, 98 }; 99 #define MEMWIN_32M_MAX 3 100 101 enum hd64461pcmcia_event_type { 102 EVENT_NONE, 103 EVENT_INSERT, 104 EVENT_REMOVE, 105 }; 106 #define EVENT_QUEUE_MAX 5 107 108 struct hd64461pcmcia_softc; /* forward declaration */ 109 110 struct hd64461pcmcia_window_cookie { 111 bus_space_tag_t wc_tag; 112 bus_space_handle_t wc_handle; 113 int wc_size; 114 int wc_window; 115 }; 116 117 struct hd64461pcmcia_channel { 118 struct hd64461pcmcia_softc *ch_parent; 119 device_t ch_pcmcia; 120 enum controller_channel ch_channel; 121 122 /* memory space */ 123 enum memory_window_mode ch_memory_window_mode; 124 bus_space_tag_t ch_memt; 125 bus_space_handle_t ch_memh; 126 bus_addr_t ch_membase_addr; 127 bus_size_t ch_memsize; 128 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 129 130 /* I/O space */ 131 bus_space_tag_t ch_iot; 132 bus_addr_t ch_iobase; 133 bus_size_t ch_iosize; 134 135 /* card interrupt */ 136 int (*ch_ih_card_func)(void *); 137 void *ch_ih_card_arg; 138 int ch_attached; 139 }; 140 141 struct hd64461pcmcia_event { 142 int __queued; 143 enum hd64461pcmcia_event_type pe_type; 144 struct hd64461pcmcia_channel *pe_ch; 145 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 146 }; 147 148 struct hd64461pcmcia_softc { 149 device_t sc_dev; 150 151 enum hd64461_module_id sc_module_id; 152 int sc_shutdown; 153 154 /* CSC event */ 155 lwp_t *sc_event_thread; 156 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 157 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 158 159 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 160 }; 161 162 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 163 struct pcmcia_mem_handle *); 164 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 165 struct pcmcia_mem_handle *); 166 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 168 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 169 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 170 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 171 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 172 struct pcmcia_io_handle *); 173 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 174 bus_size_t, struct pcmcia_io_handle *, int *); 175 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 176 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 177 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 178 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 179 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 180 struct pcmcia_function *, int, int (*)(void *), void *); 181 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 182 void *); 183 184 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 185 hd64461pcmcia_chip_mem_alloc, 186 hd64461pcmcia_chip_mem_free, 187 hd64461pcmcia_chip_mem_map, 188 hd64461pcmcia_chip_mem_unmap, 189 hd64461pcmcia_chip_io_alloc, 190 hd64461pcmcia_chip_io_free, 191 hd64461pcmcia_chip_io_map, 192 hd64461pcmcia_chip_io_unmap, 193 hd64461pcmcia_chip_intr_establish, 194 hd64461pcmcia_chip_intr_disestablish, 195 hd64461pcmcia_chip_socket_enable, 196 hd64461pcmcia_chip_socket_disable, 197 hd64461pcmcia_chip_socket_settype, 198 }; 199 200 STATIC int hd64461pcmcia_match(device_t, cfdata_t, void *); 201 STATIC void hd64461pcmcia_attach(device_t, device_t, void *); 202 STATIC int hd64461pcmcia_print(void *, const char *); 203 STATIC int hd64461pcmcia_submatch(device_t, cfdata_t, const int *, void *); 204 205 CFATTACH_DECL_NEW(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 206 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 207 208 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 209 enum controller_channel); 210 /* hot plug */ 211 STATIC void hd64461pcmcia_event_thread(void *); 212 STATIC void queue_event(struct hd64461pcmcia_channel *, 213 enum hd64461pcmcia_event_type); 214 /* interrupt handler */ 215 STATIC int hd64461pcmcia_channel0_intr(void *); 216 STATIC int hd64461pcmcia_channel1_intr(void *); 217 /* card status */ 218 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 219 STATIC void hd64461pcmcia_power_off(enum controller_channel); 220 STATIC void hd64461pcmcia_power_on(enum controller_channel); 221 /* memory window access ops */ 222 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 223 enum memory_window_mode)__attribute__((__unused__)); 224 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 225 enum memory_window_16); 226 /* bus width */ 227 STATIC void hd64461_set_bus_width(enum controller_channel, int); 228 #ifdef HD64461PCMCIA_DEBUG 229 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 230 #endif 231 /* fix SH3 Area[56] bug */ 232 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 233 #define _BUS_SPACE_ACCESS_HOOK() \ 234 do { \ 235 uint8_t dummy __attribute__((__unused__)) = \ 236 *(volatile uint8_t *)0xba000000; \ 237 } while (/*CONSTCOND*/0) 238 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 239 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 240 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 241 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 242 #undef _BUS_SPACE_ACCESS_HOOK 243 244 #define DELAY_MS(x) delay((x) * 1000) 245 246 STATIC int 247 hd64461pcmcia_match(device_t parent, cfdata_t cf, void *aux) 248 { 249 struct hd64461_attach_args *ha = aux; 250 251 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 252 } 253 254 STATIC void 255 hd64461pcmcia_attach(device_t parent, device_t self, void *aux) 256 { 257 struct hd64461_attach_args *ha = aux; 258 struct hd64461pcmcia_softc *sc; 259 int error; 260 261 sc = device_private(self); 262 sc->sc_dev = self; 263 264 sc->sc_module_id = ha->ha_module_id; 265 266 aprint_naive("\n"); 267 aprint_normal("\n"); 268 269 #ifdef HD64461PCMCIA_DEBUG 270 hd64461pcmcia_info(sc); 271 #endif 272 /* Channel 0/1 common CSC event queue */ 273 SIMPLEQ_INIT (&sc->sc_event_head); 274 error = kthread_create(PRI_NONE, 0, NULL, 275 hd64461pcmcia_event_thread, sc, 276 &sc->sc_event_thread, 277 "%s", device_xname(self)); 278 KASSERT(error == 0); 279 280 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 281 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 282 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 283 #else 284 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 285 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 286 #endif 287 } 288 289 STATIC void 290 hd64461pcmcia_event_thread(void *arg) 291 { 292 struct hd64461pcmcia_softc *sc = arg; 293 struct hd64461pcmcia_event *pe; 294 int s; 295 296 while (!sc->sc_shutdown) { 297 tsleep(sc, PWAIT, "CSC wait", 0); 298 s = splhigh(); 299 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 300 splx(s); 301 switch (pe->pe_type) { 302 default: 303 printf("%s: unknown event.\n", __func__); 304 break; 305 case EVENT_INSERT: 306 DPRINTF("insert event.\n"); 307 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 308 break; 309 case EVENT_REMOVE: 310 DPRINTF("remove event.\n"); 311 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 312 DETACH_FORCE); 313 break; 314 } 315 s = splhigh(); 316 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 317 pe->__queued = 0; 318 } 319 splx(s); 320 } 321 /* NOTREACHED */ 322 } 323 324 STATIC int 325 hd64461pcmcia_print(void *arg, const char *pnp) 326 { 327 328 if (pnp) 329 aprint_normal("pcmcia at %s", pnp); 330 331 return (UNCONF); 332 } 333 334 STATIC int 335 hd64461pcmcia_submatch(device_t parent, cfdata_t cf, 336 const int *ldesc, void *aux) 337 { 338 struct pcmciabus_attach_args *paa = aux; 339 struct hd64461pcmcia_channel *ch = 340 (struct hd64461pcmcia_channel *)paa->pch; 341 342 if (ch->ch_channel == CHANNEL_0) { 343 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 344 PCMCIABUSCF_CONTROLLER_DEFAULT && 345 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 346 return 0; 347 } else { 348 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 349 PCMCIABUSCF_CONTROLLER_DEFAULT && 350 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 351 return 0; 352 } 353 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 354 355 return (config_match(parent, cf, aux)); 356 } 357 358 STATIC void 359 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 360 enum controller_channel channel) 361 { 362 device_t parent = sc->sc_dev; 363 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 364 struct pcmciabus_attach_args paa; 365 bus_addr_t membase; 366 int i; 367 368 ch->ch_parent = sc; 369 ch->ch_channel = channel; 370 371 /* 372 * Continuous 16-MB Area Mode 373 */ 374 /* Attibute/Common memory extent */ 375 membase = (channel == CHANNEL_0) 376 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 377 378 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 379 membase, 0x01000000); /* 16MB */ 380 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 381 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 382 &ch->ch_memh); 383 fixup_sh3_pcmcia_area(ch->ch_memt); 384 385 /* Common memory space extent */ 386 ch->ch_memsize = 0x01000000; 387 for (i = 0; i < MEMWIN_16M_MAX; i++) { 388 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 389 membase + 0x01000000, 390 ch->ch_memsize); 391 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 392 } 393 394 /* I/O port extent and interrupt staff */ 395 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 396 397 if (channel == CHANNEL_0) { 398 ch->ch_iobase = 0; 399 ch->ch_iosize = HD64461_PCC0_IOSIZE; 400 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 401 HD64461_PCC0_IOBASE, 402 ch->ch_iosize); 403 fixup_sh3_pcmcia_area(ch->ch_iot); 404 405 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 406 hd64461pcmcia_channel0_intr, ch); 407 } else { 408 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 409 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 410 hd64461pcmcia_channel1_intr, ch); 411 } 412 413 paa.paa_busname = "pcmcia"; 414 paa.pch = (pcmcia_chipset_handle_t)ch; 415 paa.iobase = ch->ch_iobase; 416 paa.iosize = ch->ch_iosize; 417 418 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 419 hd64461pcmcia_print, hd64461pcmcia_submatch); 420 421 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 422 ch->ch_attached = 1; 423 pcmcia_card_attach(ch->ch_pcmcia); 424 } 425 } 426 427 STATIC int 428 hd64461pcmcia_channel0_intr(void *arg) 429 { 430 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 431 uint8_t r; 432 int ret = 0; 433 434 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 435 /* clear interrtupt (edge source only) */ 436 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 437 438 if (r & HD64461_PCC0CSCR_P0IREQ) { 439 if (ch->ch_ih_card_func) { 440 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 441 } else 442 DPRINTF("spurious IREQ interrupt.\n"); 443 } 444 445 if (r & HD64461_PCC0CSCR_P0CDC) 446 queue_event(ch, detect_card(ch->ch_channel)); 447 448 return ret; 449 } 450 451 STATIC int 452 hd64461pcmcia_channel1_intr(void *arg) 453 { 454 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 455 uint8_t r; 456 int ret = 0; 457 458 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 459 /* clear interrtupt */ 460 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 461 462 if (r & HD64461_PCC1CSCR_P1RC) { 463 if (ch->ch_ih_card_func) 464 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 465 else 466 DPRINTF("spurious READY interrupt.\n"); 467 } 468 469 if (r & HD64461_PCC1CSCR_P1CDC) 470 queue_event(ch, detect_card(ch->ch_channel)); 471 472 return ret; 473 } 474 475 STATIC void 476 queue_event(struct hd64461pcmcia_channel *ch, 477 enum hd64461pcmcia_event_type type) 478 { 479 struct hd64461pcmcia_event *pe, *pool; 480 struct hd64461pcmcia_softc *sc = ch->ch_parent; 481 int i; 482 int s = splhigh(); 483 484 if (type == EVENT_NONE) 485 goto out; 486 487 pe = 0; 488 pool = sc->sc_event_pool; 489 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 490 if (!pool[i].__queued) { 491 pe = &pool[i]; 492 break; 493 } 494 } 495 496 if (pe == 0) { 497 printf("%s: event FIFO overflow (max %d).\n", __func__, 498 EVENT_QUEUE_MAX); 499 goto out; 500 } 501 502 if ((ch->ch_attached && (type == EVENT_INSERT)) || 503 (!ch->ch_attached && (type == EVENT_REMOVE))) { 504 DPRINTF("spurious CSC interrupt.\n"); 505 goto out; 506 } 507 508 ch->ch_attached = (type == EVENT_INSERT); 509 pe->__queued = 1; 510 pe->pe_type = type; 511 pe->pe_ch = ch; 512 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 513 wakeup(sc); 514 out: 515 splx(s); 516 } 517 518 /* 519 * interface for pcmcia driver. 520 */ 521 STATIC void * 522 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 523 struct pcmcia_function *pf, 524 int ipl, int (*ih_func)(void *), void *ih_arg) 525 { 526 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 527 int channel = ch->ch_channel; 528 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 529 int s = splhigh(); 530 uint8_t r; 531 532 ch->ch_ih_card_func = ih_func; 533 ch->ch_ih_card_arg = ih_arg; 534 535 /* enable card interrupt */ 536 r = hd64461_reg_read_1(cscier); 537 if (channel == CHANNEL_0) { 538 /* set level mode */ 539 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 540 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 541 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 542 } else { 543 /* READY-pin LOW to HIGH changes generates interrupt */ 544 r |= HD64461_PCC1CSCIER_P1RE; 545 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 546 } 547 hd64461_reg_write_1(cscier, r); 548 549 splx(s); 550 551 return (void *)ih_func; 552 } 553 554 STATIC void 555 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 556 { 557 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 558 int channel = ch->ch_channel; 559 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 560 int s = splhigh(); 561 uint8_t r; 562 563 /* disable card interrupt */ 564 r = hd64461_reg_read_1(cscier); 565 if (channel == CHANNEL_0) { 566 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 567 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 568 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 569 } else { 570 r &= ~HD64461_PCC1CSCIER_P1RE; 571 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 572 } 573 hd64461_reg_write_1(cscier, r); 574 575 ch->ch_ih_card_func = 0; 576 577 splx(s); 578 } 579 580 STATIC int 581 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 582 struct pcmcia_mem_handle *pcmhp) 583 { 584 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 585 586 pcmhp->memt = ch->ch_memt; 587 pcmhp->addr = ch->ch_membase_addr; 588 pcmhp->memh = ch->ch_memh; 589 pcmhp->size = size; 590 pcmhp->realsize = size; 591 592 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 593 594 return (0); 595 } 596 597 STATIC void 598 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 599 struct pcmcia_mem_handle *pcmhp) 600 { 601 /* nothing to do */ 602 } 603 604 STATIC int 605 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 606 bus_addr_t card_addr, 607 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 608 bus_size_t *offsetp, int *windowp) 609 { 610 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 611 struct hd64461pcmcia_window_cookie *cookie; 612 bus_addr_t ofs; 613 614 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 615 M_DEVBUF, M_NOWAIT); 616 KASSERT(cookie); 617 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 618 619 /* Address */ 620 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 621 cookie->wc_tag = ch->ch_memt; 622 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 623 size, &cookie->wc_handle) != 0) 624 goto bad; 625 626 *offsetp = card_addr; 627 cookie->wc_window = -1; 628 } else { 629 int window = card_addr / ch->ch_memsize; 630 KASSERT(window < MEMWIN_16M_MAX); 631 632 cookie->wc_tag = ch->ch_cmemt[window]; 633 ofs = card_addr - window * ch->ch_memsize; 634 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 635 &cookie->wc_handle) != 0) 636 goto bad; 637 638 /* XXX bogus. check window per common memory access. */ 639 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 640 *offsetp = ofs + 0x01000000; /* skip attribute area */ 641 cookie->wc_window = window; 642 } 643 cookie->wc_size = size; 644 *windowp = (int)cookie; 645 646 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 647 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 648 size); 649 650 return (0); 651 bad: 652 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 653 free(cookie, M_DEVBUF); 654 655 return (1); 656 } 657 658 STATIC void 659 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 660 { 661 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 662 663 if (cookie->wc_window != -1) 664 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 665 cookie->wc_size); 666 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 667 free(cookie, M_DEVBUF); 668 } 669 670 STATIC int 671 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 672 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 673 { 674 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 675 676 if (ch->ch_channel == CHANNEL_1) 677 return (1); 678 679 if (start) { 680 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 681 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 682 return (1); 683 } 684 DPRINTF("map %#lx+%#lx\n", start, size); 685 } else { 686 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 687 ch->ch_iobase + ch->ch_iosize - 1, 688 size, align, 0, 0, &pcihp->addr, 689 &pcihp->ioh)) { 690 DPRINTF("couldn't allocate %#lx\n", size); 691 return (1); 692 } 693 pcihp->flags = PCMCIA_IO_ALLOCATED; 694 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 695 } 696 697 pcihp->iot = ch->ch_iot; 698 pcihp->size = size; 699 700 return (0); 701 } 702 703 STATIC int 704 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 705 bus_addr_t offset, 706 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 707 { 708 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 709 #ifdef HD64461PCMCIA_DEBUG 710 static const char *width_names[] = { "auto", "io8", "io16" }; 711 #endif 712 if (ch->ch_channel == CHANNEL_1) 713 return (1); 714 715 hd64461_set_bus_width(CHANNEL_0, width); 716 717 /* fake. drivers init that to -1 and check if it was changed. */ 718 *windowp = 0; 719 720 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 721 width_names[width]); 722 723 return (0); 724 } 725 726 STATIC void 727 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 728 struct pcmcia_io_handle *pcihp) 729 { 730 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 731 732 if (ch->ch_channel == CHANNEL_1) 733 return; 734 735 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 736 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 737 else 738 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 739 740 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 741 } 742 743 STATIC void 744 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 745 { 746 747 /* nothing to do */ 748 } 749 750 STATIC void 751 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 752 { 753 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 754 int channel = ch->ch_channel; 755 bus_addr_t isr, gcr; 756 uint8_t r; 757 int i; 758 759 DPRINTF("enable channel %d\n", channel); 760 isr = HD64461_PCCISR(channel); 761 gcr = HD64461_PCCGCR(channel); 762 763 hd64461pcmcia_power_off(channel); 764 hd64461pcmcia_power_on(channel); 765 766 /* assert reset, set card type to memory */ 767 r = hd64461_reg_read_1(gcr); 768 r |= HD64461_PCCGCR_PCCR; 769 r &= ~HD64461_PCC0GCR_P0PCCT; 770 hd64461_reg_write_1(gcr, r); 771 772 /* 773 * hold RESET at least 10us. 774 */ 775 DELAY_MS(20); 776 777 /* clear the reset flag */ 778 r &= ~HD64461_PCCGCR_PCCR; 779 hd64461_reg_write_1(gcr, r); 780 DELAY_MS(2000); 781 782 /* wait for the chip to finish initializing */ 783 for (i = 0; i < 10000; i++) { 784 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 785 goto reset_ok; 786 DELAY_MS(500); 787 788 if ((i > 5000) && (i % 100 == 99)) 789 printf("."); 790 } 791 printf("reset failed.\n"); 792 hd64461pcmcia_power_off(channel); 793 return; 794 795 reset_ok: 796 /* set Continuous 16-MB Area Mode */ 797 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 798 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 799 800 /* 801 * set Common memory area. 802 */ 803 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 804 805 DPRINTF("OK.\n"); 806 } 807 808 STATIC void 809 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 810 { 811 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 812 int channel = ch->ch_channel; 813 bus_addr_t gcr; 814 uint8_t r; 815 816 DPRINTF("settype channel %d\n", channel); 817 gcr = HD64461_PCCGCR(channel); 818 819 /* set the card type */ 820 r = hd64461_reg_read_1(gcr); 821 if (channel == CHANNEL_0) { 822 if (type == PCMCIA_IFTYPE_IO) 823 r |= HD64461_PCC0GCR_P0PCCT; 824 else 825 r &= ~HD64461_PCC0GCR_P0PCCT; 826 } else { 827 /* reserved bit must be 0 */ 828 r &= ~HD64461_PCC1GCR_RESERVED; 829 } 830 hd64461_reg_write_1(gcr, r); 831 832 DPRINTF("OK.\n"); 833 } 834 835 STATIC void 836 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 837 { 838 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 839 int channel = ch->ch_channel; 840 841 /* dont' disable CSC interrupt */ 842 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 843 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 844 845 /* power down the socket */ 846 hd64461pcmcia_power_off(channel); 847 } 848 849 /* 850 * Card detect 851 */ 852 STATIC void 853 hd64461pcmcia_power_off(enum controller_channel channel) 854 { 855 uint8_t r; 856 uint16_t r16; 857 bus_addr_t scr, gcr; 858 859 gcr = HD64461_PCCGCR(channel); 860 scr = HD64461_PCCSCR(channel); 861 862 /* DRV (external buffer) high level */ 863 r = hd64461_reg_read_1(gcr); 864 r &= ~HD64461_PCCGCR_DRVE; 865 hd64461_reg_write_1(gcr, r); 866 867 /* stop power */ 868 r = hd64461_reg_read_1(scr); 869 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 870 hd64461_reg_write_1(scr, r); 871 r = hd64461_reg_read_1(gcr); 872 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 873 hd64461_reg_write_1(gcr, r); 874 /* 875 * wait 300ms until power fails (Tpf). Then, wait 100ms since 876 * we are changing Vcc (Toff). 877 */ 878 DELAY_MS(300 + 100); 879 880 /* stop clock */ 881 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 882 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 883 HD64461_SYSSTBCR_SPC1ST); 884 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 885 } 886 887 STATIC void 888 hd64461pcmcia_power_on(enum controller_channel channel) 889 { 890 uint8_t r; 891 uint16_t r16; 892 bus_addr_t scr, gcr, isr; 893 894 isr = HD64461_PCCISR(channel); 895 gcr = HD64461_PCCGCR(channel); 896 scr = HD64461_PCCSCR(channel); 897 898 /* 899 * XXX to access attribute memory, this is required. 900 */ 901 if (channel == CHANNEL_0) { 902 /* GPIO Port A XXX Jonanada690 specific? */ 903 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 904 r16 &= ~0xf; 905 r16 |= 0x5; 906 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 907 } 908 909 if (channel == CHANNEL_1) { 910 /* GPIO Port C, Port D -> PCC1 pin 911 * I assume SYSCR[1:0] == 0 912 */ 913 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 914 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 915 } 916 917 /* supply clock */ 918 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 919 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 920 HD64461_SYSSTBCR_SPC1ST); 921 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 922 DELAY_MS(200); 923 924 /* detect voltage and supply VCC */ 925 r = hd64461_reg_read_1(isr); 926 927 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 928 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 929 DPRINTF("5V card\n"); 930 hd64461pcmcia_power(channel, V_5, 1); 931 break; 932 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 933 /* FALLTHROUGH */ 934 case 0: /* x.x / 3.3 / 5 V */ 935 DPRINTF("3.3V card\n"); 936 hd64461pcmcia_power(channel, V_3_3, 1); 937 break; 938 case HD64461_PCCISR_VS1: /* x.x V */ 939 /* FALLTHROUGH */ 940 DPRINTF("x.x V card\n"); 941 hd64461pcmcia_power(channel, V_X_X, 1); 942 return; 943 default: 944 printf("\nunknown Voltage. don't attach.\n"); 945 return; 946 } 947 948 /* 949 * wait 100ms until power raise (Tpr) and 20ms to become 950 * stable (Tsu(Vcc)). 951 * 952 * some machines require some more time to be settled 953 * (300ms is added here). 954 */ 955 DELAY_MS(100 + 20 + 300); 956 957 /* DRV (external buffer) low level */ 958 r = hd64461_reg_read_1(gcr); 959 r |= HD64461_PCCGCR_DRVE; 960 hd64461_reg_write_1(gcr, r); 961 962 /* clear interrupt */ 963 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 964 HD64461_PCC1CSCR_REG8, 0); 965 } 966 967 STATIC enum hd64461pcmcia_event_type 968 detect_card(enum controller_channel channel) 969 { 970 uint8_t r; 971 972 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 973 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 974 975 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 976 DPRINTF("remove\n"); 977 return EVENT_REMOVE; 978 } 979 if (r == 0) { 980 DPRINTF("insert\n"); 981 return EVENT_INSERT; 982 } 983 DPRINTF("transition\n"); 984 985 return EVENT_NONE; 986 } 987 988 /* 989 * Memory window access ops. 990 */ 991 STATIC void 992 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 993 enum memory_window_mode mode) 994 { 995 bus_addr_t a = HD64461_PCCGCR(channel); 996 uint8_t r = hd64461_reg_read_1(a); 997 998 r &= ~HD64461_PCCGCR_MMOD; 999 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 1000 HD64461_PCCGCR_MMOD_32M; 1001 hd64461_reg_write_1(a, r); 1002 } 1003 1004 STATIC void 1005 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1006 enum memory_window_16 window) 1007 { 1008 bus_addr_t a = HD64461_PCCGCR(channel); 1009 uint8_t r; 1010 1011 r = hd64461_reg_read_1(a); 1012 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1013 1014 switch (window) { 1015 case MEMWIN_16M_COMMON_0: 1016 break; 1017 case MEMWIN_16M_COMMON_1: 1018 r |= HD64461_PCCGCR_PA24; 1019 break; 1020 case MEMWIN_16M_COMMON_2: 1021 r |= HD64461_PCCGCR_PA25; 1022 break; 1023 case MEMWIN_16M_COMMON_3: 1024 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1025 break; 1026 } 1027 1028 hd64461_reg_write_1(a, r); 1029 } 1030 1031 #if unused 1032 STATIC void 1033 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1034 { 1035 bus_addr_t a = HD64461_PCCGCR(channel); 1036 uint8_t r; 1037 1038 r = hd64461_reg_read_1(a); 1039 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1040 1041 switch (window) { 1042 case MEMWIN_32M_ATTR: 1043 break; 1044 case MEMWIN_32M_COMMON_0: 1045 r |= HD64461_PCCGCR_PREG; 1046 break; 1047 case MEMWIN_32M_COMMON_1: 1048 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1049 break; 1050 } 1051 1052 hd64461_reg_write_1(a, r); 1053 } 1054 #endif 1055 1056 STATIC void 1057 hd64461_set_bus_width(enum controller_channel channel, int width) 1058 { 1059 unsigned int area, buswidth; 1060 uint16_t bcr2; 1061 1062 if (channel == CHANNEL_0) 1063 area = BCR2_AREA6_SHIFT; 1064 else 1065 area = BCR2_AREA5_SHIFT; 1066 1067 if (width == PCMCIA_WIDTH_IO8) 1068 buswidth = BCR2_AREA_WIDTH_8; 1069 else 1070 buswidth = BCR2_AREA_WIDTH_16; 1071 1072 bcr2 = _reg_read_2(SH3_BCR2); 1073 1074 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1075 bcr2 |= buswidth << area; 1076 1077 _reg_write_2(SH3_BCR2, bcr2); 1078 } 1079 1080 STATIC void 1081 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1082 { 1083 struct hpcsh_bus_space *hbs = (void *)t; 1084 1085 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1086 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1087 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1088 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1089 } 1090 1091 #ifdef HD64461PCMCIA_DEBUG 1092 STATIC void 1093 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1094 { 1095 uint8_t r8; 1096 1097 dbg_banner_function(); 1098 /* 1099 * PCC0 1100 */ 1101 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1102 printf("PCC0 Interface Status Register\n"); 1103 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1104 1105 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1106 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1107 _(P0BVD2);_(P0BVD1); 1108 #undef _ 1109 printf("\n"); 1110 1111 printf("PCC0 General Control Register\n"); 1112 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1113 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1114 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1115 _(P0PA25);_(P0PA24);_(P0REG); 1116 #undef _ 1117 printf("\n"); 1118 1119 printf("PCC0 Card Status Change Register\n"); 1120 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1121 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1122 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1123 #undef _ 1124 printf("\n"); 1125 1126 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1127 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1128 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1129 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1130 #undef _ 1131 printf("\ninterrupt type: "); 1132 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1133 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1134 printf("none\n"); 1135 break; 1136 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1137 printf("level\n"); 1138 break; 1139 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1140 printf("falling edge\n"); 1141 break; 1142 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1143 printf("rising edge\n"); 1144 break; 1145 } 1146 1147 printf("PCC0 Software Control Register\n"); 1148 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1149 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1150 _(P0VCC1);_(P0SWP); 1151 #undef _ 1152 printf("\n"); 1153 1154 /* 1155 * PCC1 1156 */ 1157 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1158 printf("PCC1 Interface Status Register\n"); 1159 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1160 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1161 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1162 _(P1BVD2);_(P1BVD1); 1163 #undef _ 1164 printf("\n"); 1165 1166 printf("PCC1 General Contorol Register\n"); 1167 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1168 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1169 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1170 #undef _ 1171 printf("\n"); 1172 1173 printf("PCC1 Card Status Change Register\n"); 1174 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1175 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1176 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1177 #undef _ 1178 printf("\n"); 1179 1180 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1181 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1182 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1183 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1184 #undef _ 1185 printf("\n"); 1186 1187 printf("PCC1 Software Control Register\n"); 1188 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1189 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1190 _(P1VCC1);_(P1SWP); 1191 #undef _ 1192 printf("\n"); 1193 1194 /* 1195 * General Control 1196 */ 1197 printf("[General Control]\n"); 1198 printf("PCC0 Output pins Control Register\n"); 1199 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1200 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1201 _(P0DEPLUP);_(P0AEPLUP); 1202 #undef _ 1203 printf("\n"); 1204 1205 printf("PCC1 Output pins Control Register\n"); 1206 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1207 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1208 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1209 #undef _ 1210 printf("\n"); 1211 1212 printf("PC Card General Control Register\n"); 1213 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1214 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1215 _(PSSDIR);_(PSSRDWR); 1216 #undef _ 1217 printf("\n"); 1218 1219 dbg_banner_line(); 1220 } 1221 #endif /* HD64461PCMCIA_DEBUG */ 1222
Indexes created Thu Oct 02 01:09:59 GMT 2025