hd64461pcmcia.c revision 1.48
1 /* $NetBSD: hd64461pcmcia.c,v 1.48 2011/07/20 20:46:49 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.48 2011/07/20 20:46:49 dyoung Exp $"); 34 35 #include "opt_hd64461pcmcia.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 #include <sys/boot_flag.h> 43 #include <sys/bus.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 53 #include <hpcsh/dev/hd64461/hd64461reg.h> 54 #include <hpcsh/dev/hd64461/hd64461var.h> 55 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 56 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 58 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 59 60 #include <hpcsh/bus_util.h> /* for _BUS_SPACE_WRITE(), et cetera */ 61 62 #include "locators.h" 63 64 #ifdef HD64461PCMCIA_DEBUG 65 #define DPRINTF_ENABLE 66 #define DPRINTF_DEBUG hd64461pcmcia_debug 67 #endif 68 #include <machine/debug.h> 69 70 enum controller_channel { 71 CHANNEL_0 = 0, 72 CHANNEL_1 = 1, 73 CHANNEL_MAX = 2 74 }; 75 76 enum memory_window_mode { 77 MEMWIN_16M_MODE, 78 MEMWIN_32M_MODE 79 }; 80 81 enum memory_window_16 { 82 MEMWIN_16M_COMMON_0, 83 MEMWIN_16M_COMMON_1, 84 MEMWIN_16M_COMMON_2, 85 MEMWIN_16M_COMMON_3, 86 }; 87 #define MEMWIN_16M_MAX 4 88 89 enum memory_window_32 { 90 MEMWIN_32M_ATTR, 91 MEMWIN_32M_COMMON_0, 92 MEMWIN_32M_COMMON_1, 93 }; 94 #define MEMWIN_32M_MAX 3 95 96 enum hd64461pcmcia_event_type { 97 EVENT_NONE, 98 EVENT_INSERT, 99 EVENT_REMOVE, 100 }; 101 #define EVENT_QUEUE_MAX 5 102 103 struct hd64461pcmcia_softc; /* forward declaration */ 104 105 struct hd64461pcmcia_window_cookie { 106 bus_space_tag_t wc_tag; 107 bus_space_handle_t wc_handle; 108 int wc_size; 109 int wc_window; 110 }; 111 112 struct hd64461pcmcia_channel { 113 struct hd64461pcmcia_softc *ch_parent; 114 device_t ch_pcmcia; 115 enum controller_channel ch_channel; 116 117 /* memory space */ 118 enum memory_window_mode ch_memory_window_mode; 119 bus_space_tag_t ch_memt; 120 bus_space_handle_t ch_memh; 121 bus_addr_t ch_membase_addr; 122 bus_size_t ch_memsize; 123 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 124 125 /* I/O space */ 126 bus_space_tag_t ch_iot; 127 bus_addr_t ch_iobase; 128 bus_size_t ch_iosize; 129 130 /* card interrupt */ 131 int (*ch_ih_card_func)(void *); 132 void *ch_ih_card_arg; 133 int ch_attached; 134 }; 135 136 struct hd64461pcmcia_event { 137 int __queued; 138 enum hd64461pcmcia_event_type pe_type; 139 struct hd64461pcmcia_channel *pe_ch; 140 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 141 }; 142 143 struct hd64461pcmcia_softc { 144 device_t sc_dev; 145 146 enum hd64461_module_id sc_module_id; 147 int sc_shutdown; 148 149 /* CSC event */ 150 lwp_t *sc_event_thread; 151 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 152 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 153 154 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 155 }; 156 157 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 158 struct pcmcia_mem_handle *); 159 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 160 struct pcmcia_mem_handle *); 161 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 162 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 163 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 164 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 165 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 166 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 167 struct pcmcia_io_handle *); 168 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_io_handle *, int *); 170 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 171 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 172 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 hd64461pcmcia_chip_socket_settype, 193 }; 194 195 STATIC int hd64461pcmcia_match(device_t, cfdata_t, void *); 196 STATIC void hd64461pcmcia_attach(device_t, device_t, void *); 197 STATIC int hd64461pcmcia_print(void *, const char *); 198 STATIC int hd64461pcmcia_submatch(device_t, cfdata_t, const int *, void *); 199 200 CFATTACH_DECL_NEW(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 201 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 202 203 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 204 enum controller_channel); 205 /* hot plug */ 206 STATIC void hd64461pcmcia_event_thread(void *); 207 STATIC void queue_event(struct hd64461pcmcia_channel *, 208 enum hd64461pcmcia_event_type); 209 /* interrupt handler */ 210 STATIC int hd64461pcmcia_channel0_intr(void *); 211 STATIC int hd64461pcmcia_channel1_intr(void *); 212 /* card status */ 213 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 214 STATIC void hd64461pcmcia_power_off(enum controller_channel); 215 STATIC void hd64461pcmcia_power_on(enum controller_channel); 216 /* memory window access ops */ 217 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 218 enum memory_window_mode)__attribute__((__unused__)); 219 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 220 enum memory_window_16); 221 /* bus width */ 222 STATIC void hd64461_set_bus_width(enum controller_channel, int); 223 #ifdef HD64461PCMCIA_DEBUG 224 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 225 #endif 226 /* fix SH3 Area[56] bug */ 227 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 228 #define _BUS_SPACE_ACCESS_HOOK() \ 229 do { \ 230 uint8_t dummy __attribute__((__unused__)) = \ 231 *(volatile uint8_t *)0xba000000; \ 232 } while (/*CONSTCOND*/0) 233 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 234 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 235 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 236 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 237 #undef _BUS_SPACE_ACCESS_HOOK 238 239 #define DELAY_MS(x) delay((x) * 1000) 240 241 STATIC int 242 hd64461pcmcia_match(device_t parent, cfdata_t cf, void *aux) 243 { 244 struct hd64461_attach_args *ha = aux; 245 246 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 247 } 248 249 STATIC void 250 hd64461pcmcia_attach(device_t parent, device_t self, void *aux) 251 { 252 struct hd64461_attach_args *ha = aux; 253 struct hd64461pcmcia_softc *sc; 254 int error; 255 256 sc = device_private(self); 257 sc->sc_dev = self; 258 259 sc->sc_module_id = ha->ha_module_id; 260 261 aprint_naive("\n"); 262 aprint_normal("\n"); 263 264 #ifdef HD64461PCMCIA_DEBUG 265 hd64461pcmcia_info(sc); 266 #endif 267 /* Channel 0/1 common CSC event queue */ 268 SIMPLEQ_INIT (&sc->sc_event_head); 269 270 error = kthread_create(PRI_NONE, 0, NULL, 271 hd64461pcmcia_event_thread, sc, 272 &sc->sc_event_thread, 273 "%s", device_xname(self)); 274 KASSERT(error == 0); 275 276 config_pending_incr(); 277 278 /* XXX: TODO */ 279 if (!pmf_device_register(self, NULL, NULL)) 280 aprint_error_dev(self, "unable to establish power handler\n"); 281 } 282 283 STATIC void 284 hd64461pcmcia_event_thread(void *arg) 285 { 286 struct hd64461pcmcia_softc *sc = arg; 287 struct hd64461pcmcia_event *pe; 288 int s; 289 290 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 291 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 292 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 293 #else 294 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 295 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 296 #endif 297 config_pending_decr(); 298 299 while (!sc->sc_shutdown) { 300 tsleep(sc, PWAIT, "CSC wait", 0); 301 s = splhigh(); 302 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 303 splx(s); 304 switch (pe->pe_type) { 305 default: 306 printf("%s: unknown event.\n", __func__); 307 break; 308 case EVENT_INSERT: 309 DPRINTF("insert event.\n"); 310 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 311 break; 312 case EVENT_REMOVE: 313 DPRINTF("remove event.\n"); 314 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 315 DETACH_FORCE); 316 break; 317 } 318 s = splhigh(); 319 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 320 pe->__queued = 0; 321 } 322 splx(s); 323 } 324 325 sc->sc_event_thread = NULL; 326 kthread_exit(0); 327 /* NOTREACHED */ 328 } 329 330 STATIC int 331 hd64461pcmcia_print(void *arg, const char *pnp) 332 { 333 334 if (pnp) 335 aprint_normal("pcmcia at %s", pnp); 336 337 return (UNCONF); 338 } 339 340 STATIC int 341 hd64461pcmcia_submatch(device_t parent, cfdata_t cf, 342 const int *ldesc, void *aux) 343 { 344 struct pcmciabus_attach_args *paa = aux; 345 struct hd64461pcmcia_channel *ch = 346 (struct hd64461pcmcia_channel *)paa->pch; 347 348 if (ch->ch_channel == CHANNEL_0) { 349 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 350 PCMCIABUSCF_CONTROLLER_DEFAULT && 351 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 352 return 0; 353 } else { 354 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 355 PCMCIABUSCF_CONTROLLER_DEFAULT && 356 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 357 return 0; 358 } 359 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 360 361 return (config_match(parent, cf, aux)); 362 } 363 364 STATIC void 365 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 366 enum controller_channel channel) 367 { 368 device_t parent = sc->sc_dev; 369 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 370 struct pcmciabus_attach_args paa; 371 bus_addr_t membase; 372 int i; 373 374 ch->ch_parent = sc; 375 ch->ch_channel = channel; 376 377 /* 378 * Continuous 16-MB Area Mode 379 */ 380 /* Attibute/Common memory extent */ 381 membase = (channel == CHANNEL_0) 382 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 383 384 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 385 membase, 0x01000000); /* 16MB */ 386 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 387 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 388 &ch->ch_memh); 389 fixup_sh3_pcmcia_area(ch->ch_memt); 390 391 /* Common memory space extent */ 392 ch->ch_memsize = 0x01000000; 393 for (i = 0; i < MEMWIN_16M_MAX; i++) { 394 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 395 membase + 0x01000000, 396 ch->ch_memsize); 397 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 398 } 399 400 /* I/O port extent and interrupt staff */ 401 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 402 403 if (channel == CHANNEL_0) { 404 ch->ch_iobase = 0; 405 ch->ch_iosize = HD64461_PCC0_IOSIZE; 406 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 407 HD64461_PCC0_IOBASE, 408 ch->ch_iosize); 409 fixup_sh3_pcmcia_area(ch->ch_iot); 410 411 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 412 hd64461pcmcia_channel0_intr, ch); 413 } else { 414 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 415 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 416 hd64461pcmcia_channel1_intr, ch); 417 } 418 419 paa.paa_busname = "pcmcia"; 420 paa.pch = (pcmcia_chipset_handle_t)ch; 421 paa.iobase = ch->ch_iobase; 422 paa.iosize = ch->ch_iosize; 423 424 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 425 hd64461pcmcia_print, hd64461pcmcia_submatch); 426 427 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 428 ch->ch_attached = 1; 429 pcmcia_card_attach(ch->ch_pcmcia); 430 } 431 } 432 433 STATIC int 434 hd64461pcmcia_channel0_intr(void *arg) 435 { 436 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 437 uint8_t r; 438 int ret = 0; 439 440 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 441 /* clear interrtupt (edge source only) */ 442 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 443 444 if (r & HD64461_PCC0CSCR_P0IREQ) { 445 if (ch->ch_ih_card_func) { 446 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 447 } else 448 DPRINTF("spurious IREQ interrupt.\n"); 449 } 450 451 if (r & HD64461_PCC0CSCR_P0CDC) 452 queue_event(ch, detect_card(ch->ch_channel)); 453 454 return ret; 455 } 456 457 STATIC int 458 hd64461pcmcia_channel1_intr(void *arg) 459 { 460 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 461 uint8_t r; 462 int ret = 0; 463 464 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 465 /* clear interrtupt */ 466 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 467 468 if (r & HD64461_PCC1CSCR_P1RC) { 469 if (ch->ch_ih_card_func) 470 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 471 else 472 DPRINTF("spurious READY interrupt.\n"); 473 } 474 475 if (r & HD64461_PCC1CSCR_P1CDC) 476 queue_event(ch, detect_card(ch->ch_channel)); 477 478 return ret; 479 } 480 481 STATIC void 482 queue_event(struct hd64461pcmcia_channel *ch, 483 enum hd64461pcmcia_event_type type) 484 { 485 struct hd64461pcmcia_event *pe, *pool; 486 struct hd64461pcmcia_softc *sc = ch->ch_parent; 487 int i; 488 int s = splhigh(); 489 490 if (type == EVENT_NONE) 491 goto out; 492 493 pe = 0; 494 pool = sc->sc_event_pool; 495 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 496 if (!pool[i].__queued) { 497 pe = &pool[i]; 498 break; 499 } 500 } 501 502 if (pe == 0) { 503 printf("%s: event FIFO overflow (max %d).\n", __func__, 504 EVENT_QUEUE_MAX); 505 goto out; 506 } 507 508 if ((ch->ch_attached && (type == EVENT_INSERT)) || 509 (!ch->ch_attached && (type == EVENT_REMOVE))) { 510 DPRINTF("spurious CSC interrupt.\n"); 511 goto out; 512 } 513 514 ch->ch_attached = (type == EVENT_INSERT); 515 pe->__queued = 1; 516 pe->pe_type = type; 517 pe->pe_ch = ch; 518 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 519 wakeup(sc); 520 out: 521 splx(s); 522 } 523 524 /* 525 * interface for pcmcia driver. 526 */ 527 STATIC void * 528 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 529 struct pcmcia_function *pf, 530 int ipl, int (*ih_func)(void *), void *ih_arg) 531 { 532 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 533 int channel = ch->ch_channel; 534 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 535 int s = splhigh(); 536 uint8_t r; 537 538 ch->ch_ih_card_func = ih_func; 539 ch->ch_ih_card_arg = ih_arg; 540 541 /* enable card interrupt */ 542 r = hd64461_reg_read_1(cscier); 543 if (channel == CHANNEL_0) { 544 /* set level mode */ 545 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 546 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 547 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 548 } else { 549 /* READY-pin LOW to HIGH changes generates interrupt */ 550 r |= HD64461_PCC1CSCIER_P1RE; 551 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 552 } 553 hd64461_reg_write_1(cscier, r); 554 555 splx(s); 556 557 return (void *)ih_func; 558 } 559 560 STATIC void 561 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 562 { 563 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 564 int channel = ch->ch_channel; 565 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 566 int s = splhigh(); 567 uint8_t r; 568 569 /* disable card interrupt */ 570 r = hd64461_reg_read_1(cscier); 571 if (channel == CHANNEL_0) { 572 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 573 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 574 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 575 } else { 576 r &= ~HD64461_PCC1CSCIER_P1RE; 577 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 578 } 579 hd64461_reg_write_1(cscier, r); 580 581 ch->ch_ih_card_func = 0; 582 583 splx(s); 584 } 585 586 STATIC int 587 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 588 struct pcmcia_mem_handle *pcmhp) 589 { 590 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 591 592 pcmhp->memt = ch->ch_memt; 593 pcmhp->addr = ch->ch_membase_addr; 594 pcmhp->memh = ch->ch_memh; 595 pcmhp->size = size; 596 pcmhp->realsize = size; 597 598 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 599 600 return (0); 601 } 602 603 STATIC void 604 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 605 struct pcmcia_mem_handle *pcmhp) 606 { 607 /* nothing to do */ 608 } 609 610 STATIC int 611 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 612 bus_addr_t card_addr, 613 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 614 bus_size_t *offsetp, int *windowp) 615 { 616 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 617 struct hd64461pcmcia_window_cookie *cookie; 618 bus_addr_t ofs; 619 620 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 621 M_DEVBUF, M_NOWAIT); 622 KASSERT(cookie); 623 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 624 625 /* Address */ 626 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 627 cookie->wc_tag = ch->ch_memt; 628 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 629 size, &cookie->wc_handle) != 0) 630 goto bad; 631 632 *offsetp = card_addr; 633 cookie->wc_window = -1; 634 } else { 635 int window = card_addr / ch->ch_memsize; 636 KASSERT(window < MEMWIN_16M_MAX); 637 638 cookie->wc_tag = ch->ch_cmemt[window]; 639 ofs = card_addr - window * ch->ch_memsize; 640 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 641 &cookie->wc_handle) != 0) 642 goto bad; 643 644 /* XXX bogus. check window per common memory access. */ 645 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 646 *offsetp = ofs + 0x01000000; /* skip attribute area */ 647 cookie->wc_window = window; 648 } 649 cookie->wc_size = size; 650 *windowp = (int)cookie; 651 652 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 653 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 654 size); 655 656 return (0); 657 bad: 658 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 659 free(cookie, M_DEVBUF); 660 661 return (1); 662 } 663 664 STATIC void 665 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 666 { 667 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 668 669 if (cookie->wc_window != -1) 670 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 671 cookie->wc_size); 672 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 673 free(cookie, M_DEVBUF); 674 } 675 676 STATIC int 677 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 678 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 679 { 680 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 681 682 if (ch->ch_channel == CHANNEL_1) 683 return (1); 684 685 if (start) { 686 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 687 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 688 return (1); 689 } 690 DPRINTF("map %#lx+%#lx\n", start, size); 691 } else { 692 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 693 ch->ch_iobase + ch->ch_iosize - 1, 694 size, align, 0, 0, &pcihp->addr, 695 &pcihp->ioh)) { 696 DPRINTF("couldn't allocate %#lx\n", size); 697 return (1); 698 } 699 pcihp->flags = PCMCIA_IO_ALLOCATED; 700 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 701 } 702 703 pcihp->iot = ch->ch_iot; 704 pcihp->size = size; 705 706 return (0); 707 } 708 709 STATIC int 710 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 711 bus_addr_t offset, 712 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 713 { 714 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 715 #ifdef HD64461PCMCIA_DEBUG 716 static const char *width_names[] = { "auto", "io8", "io16" }; 717 #endif 718 if (ch->ch_channel == CHANNEL_1) 719 return (1); 720 721 hd64461_set_bus_width(CHANNEL_0, width); 722 723 /* fake. drivers init that to -1 and check if it was changed. */ 724 *windowp = 0; 725 726 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 727 width_names[width]); 728 729 return (0); 730 } 731 732 STATIC void 733 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 734 struct pcmcia_io_handle *pcihp) 735 { 736 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 737 738 if (ch->ch_channel == CHANNEL_1) 739 return; 740 741 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 742 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 743 else 744 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 745 746 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 747 } 748 749 STATIC void 750 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 751 { 752 753 /* nothing to do */ 754 } 755 756 STATIC void 757 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 758 { 759 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 760 int channel = ch->ch_channel; 761 bus_addr_t isr, gcr; 762 uint8_t r; 763 int i; 764 765 DPRINTF("enable channel %d\n", channel); 766 isr = HD64461_PCCISR(channel); 767 gcr = HD64461_PCCGCR(channel); 768 769 hd64461pcmcia_power_off(channel); 770 hd64461pcmcia_power_on(channel); 771 772 /* assert reset, set card type to memory */ 773 r = hd64461_reg_read_1(gcr); 774 r |= HD64461_PCCGCR_PCCR; 775 r &= ~HD64461_PCC0GCR_P0PCCT; 776 hd64461_reg_write_1(gcr, r); 777 778 /* 779 * hold RESET at least 10us. 780 */ 781 DELAY_MS(20); 782 783 /* clear the reset flag */ 784 r &= ~HD64461_PCCGCR_PCCR; 785 hd64461_reg_write_1(gcr, r); 786 DELAY_MS(2000); 787 788 /* wait for the chip to finish initializing */ 789 for (i = 0; i < 10000; i++) { 790 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 791 goto reset_ok; 792 DELAY_MS(500); 793 794 if ((i > 5000) && (i % 100 == 99)) 795 printf("."); 796 } 797 printf("reset failed.\n"); 798 hd64461pcmcia_power_off(channel); 799 return; 800 801 reset_ok: 802 /* set Continuous 16-MB Area Mode */ 803 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 804 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 805 806 /* 807 * set Common memory area. 808 */ 809 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 810 811 DPRINTF("OK.\n"); 812 } 813 814 STATIC void 815 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 816 { 817 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 818 int channel = ch->ch_channel; 819 bus_addr_t gcr; 820 uint8_t r; 821 822 DPRINTF("settype channel %d\n", channel); 823 gcr = HD64461_PCCGCR(channel); 824 825 /* set the card type */ 826 r = hd64461_reg_read_1(gcr); 827 if (channel == CHANNEL_0) { 828 if (type == PCMCIA_IFTYPE_IO) 829 r |= HD64461_PCC0GCR_P0PCCT; 830 else 831 r &= ~HD64461_PCC0GCR_P0PCCT; 832 } else { 833 /* reserved bit must be 0 */ 834 r &= ~HD64461_PCC1GCR_RESERVED; 835 } 836 hd64461_reg_write_1(gcr, r); 837 838 DPRINTF("OK.\n"); 839 } 840 841 STATIC void 842 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 843 { 844 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 845 int channel = ch->ch_channel; 846 847 /* dont' disable CSC interrupt */ 848 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 849 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 850 851 /* power down the socket */ 852 hd64461pcmcia_power_off(channel); 853 } 854 855 /* 856 * Card detect 857 */ 858 STATIC void 859 hd64461pcmcia_power_off(enum controller_channel channel) 860 { 861 uint8_t r; 862 uint16_t r16; 863 bus_addr_t scr, gcr; 864 865 gcr = HD64461_PCCGCR(channel); 866 scr = HD64461_PCCSCR(channel); 867 868 /* DRV (external buffer) high level */ 869 r = hd64461_reg_read_1(gcr); 870 r &= ~HD64461_PCCGCR_DRVE; 871 hd64461_reg_write_1(gcr, r); 872 873 /* stop power */ 874 r = hd64461_reg_read_1(scr); 875 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 876 hd64461_reg_write_1(scr, r); 877 r = hd64461_reg_read_1(gcr); 878 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 879 hd64461_reg_write_1(gcr, r); 880 /* 881 * wait 300ms until power fails (Tpf). Then, wait 100ms since 882 * we are changing Vcc (Toff). 883 */ 884 DELAY_MS(300 + 100); 885 886 /* stop clock */ 887 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 888 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 889 HD64461_SYSSTBCR_SPC1ST); 890 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 891 } 892 893 STATIC void 894 hd64461pcmcia_power_on(enum controller_channel channel) 895 { 896 uint8_t r; 897 uint16_t r16; 898 bus_addr_t scr, gcr, isr; 899 900 isr = HD64461_PCCISR(channel); 901 gcr = HD64461_PCCGCR(channel); 902 scr = HD64461_PCCSCR(channel); 903 904 /* 905 * XXX to access attribute memory, this is required. 906 */ 907 if (channel == CHANNEL_0) { 908 /* GPIO Port A XXX Jonanada690 specific? */ 909 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 910 r16 &= ~0xf; 911 r16 |= 0x5; 912 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 913 } 914 915 if (channel == CHANNEL_1) { 916 /* GPIO Port C, Port D -> PCC1 pin 917 * I assume SYSCR[1:0] == 0 918 */ 919 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 920 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 921 } 922 923 /* supply clock */ 924 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 925 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 926 HD64461_SYSSTBCR_SPC1ST); 927 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 928 DELAY_MS(200); 929 930 /* detect voltage and supply VCC */ 931 r = hd64461_reg_read_1(isr); 932 933 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 934 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 935 DPRINTF("5V card\n"); 936 hd64461pcmcia_power(channel, V_5, 1); 937 break; 938 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 939 /* FALLTHROUGH */ 940 case 0: /* x.x / 3.3 / 5 V */ 941 DPRINTF("3.3V card\n"); 942 hd64461pcmcia_power(channel, V_3_3, 1); 943 break; 944 case HD64461_PCCISR_VS1: /* x.x V */ 945 /* FALLTHROUGH */ 946 DPRINTF("x.x V card\n"); 947 hd64461pcmcia_power(channel, V_X_X, 1); 948 return; 949 default: 950 printf("\nunknown Voltage. don't attach.\n"); 951 return; 952 } 953 954 /* 955 * wait 100ms until power raise (Tpr) and 20ms to become 956 * stable (Tsu(Vcc)). 957 * 958 * some machines require some more time to be settled 959 * (300ms is added here). 960 */ 961 DELAY_MS(100 + 20 + 300); 962 963 /* DRV (external buffer) low level */ 964 r = hd64461_reg_read_1(gcr); 965 r |= HD64461_PCCGCR_DRVE; 966 hd64461_reg_write_1(gcr, r); 967 968 /* clear interrupt */ 969 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 970 HD64461_PCC1CSCR_REG8, 0); 971 } 972 973 STATIC enum hd64461pcmcia_event_type 974 detect_card(enum controller_channel channel) 975 { 976 uint8_t r; 977 978 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 979 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 980 981 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 982 DPRINTF("remove\n"); 983 return EVENT_REMOVE; 984 } 985 if (r == 0) { 986 DPRINTF("insert\n"); 987 return EVENT_INSERT; 988 } 989 DPRINTF("transition\n"); 990 991 return EVENT_NONE; 992 } 993 994 /* 995 * Memory window access ops. 996 */ 997 STATIC void 998 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 999 enum memory_window_mode mode) 1000 { 1001 bus_addr_t a = HD64461_PCCGCR(channel); 1002 uint8_t r = hd64461_reg_read_1(a); 1003 1004 r &= ~HD64461_PCCGCR_MMOD; 1005 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 1006 HD64461_PCCGCR_MMOD_32M; 1007 hd64461_reg_write_1(a, r); 1008 } 1009 1010 STATIC void 1011 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1012 enum memory_window_16 window) 1013 { 1014 bus_addr_t a = HD64461_PCCGCR(channel); 1015 uint8_t r; 1016 1017 r = hd64461_reg_read_1(a); 1018 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1019 1020 switch (window) { 1021 case MEMWIN_16M_COMMON_0: 1022 break; 1023 case MEMWIN_16M_COMMON_1: 1024 r |= HD64461_PCCGCR_PA24; 1025 break; 1026 case MEMWIN_16M_COMMON_2: 1027 r |= HD64461_PCCGCR_PA25; 1028 break; 1029 case MEMWIN_16M_COMMON_3: 1030 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1031 break; 1032 } 1033 1034 hd64461_reg_write_1(a, r); 1035 } 1036 1037 #if unused 1038 STATIC void 1039 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1040 { 1041 bus_addr_t a = HD64461_PCCGCR(channel); 1042 uint8_t r; 1043 1044 r = hd64461_reg_read_1(a); 1045 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1046 1047 switch (window) { 1048 case MEMWIN_32M_ATTR: 1049 break; 1050 case MEMWIN_32M_COMMON_0: 1051 r |= HD64461_PCCGCR_PREG; 1052 break; 1053 case MEMWIN_32M_COMMON_1: 1054 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1055 break; 1056 } 1057 1058 hd64461_reg_write_1(a, r); 1059 } 1060 #endif 1061 1062 STATIC void 1063 hd64461_set_bus_width(enum controller_channel channel, int width) 1064 { 1065 unsigned int area, buswidth; 1066 uint16_t bcr2; 1067 1068 if (channel == CHANNEL_0) 1069 area = BCR2_AREA6_SHIFT; 1070 else 1071 area = BCR2_AREA5_SHIFT; 1072 1073 if (width == PCMCIA_WIDTH_IO8) 1074 buswidth = BCR2_AREA_WIDTH_8; 1075 else 1076 buswidth = BCR2_AREA_WIDTH_16; 1077 1078 bcr2 = _reg_read_2(SH3_BCR2); 1079 1080 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1081 bcr2 |= buswidth << area; 1082 1083 _reg_write_2(SH3_BCR2, bcr2); 1084 } 1085 1086 STATIC void 1087 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1088 { 1089 struct hpcsh_bus_space *hbs = (void *)t; 1090 1091 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1092 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1093 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1094 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1095 } 1096 1097 #ifdef HD64461PCMCIA_DEBUG 1098 STATIC void 1099 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1100 { 1101 uint8_t r8; 1102 1103 dbg_banner_function(); 1104 /* 1105 * PCC0 1106 */ 1107 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1108 printf("PCC0 Interface Status Register\n"); 1109 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1110 1111 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1112 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1113 _(P0BVD2);_(P0BVD1); 1114 #undef _ 1115 printf("\n"); 1116 1117 printf("PCC0 General Control Register\n"); 1118 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1119 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1120 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1121 _(P0PA25);_(P0PA24);_(P0REG); 1122 #undef _ 1123 printf("\n"); 1124 1125 printf("PCC0 Card Status Change Register\n"); 1126 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1127 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1128 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1129 #undef _ 1130 printf("\n"); 1131 1132 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1133 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1134 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1135 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1136 #undef _ 1137 printf("\ninterrupt type: "); 1138 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1139 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1140 printf("none\n"); 1141 break; 1142 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1143 printf("level\n"); 1144 break; 1145 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1146 printf("falling edge\n"); 1147 break; 1148 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1149 printf("rising edge\n"); 1150 break; 1151 } 1152 1153 printf("PCC0 Software Control Register\n"); 1154 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1155 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1156 _(P0VCC1);_(P0SWP); 1157 #undef _ 1158 printf("\n"); 1159 1160 /* 1161 * PCC1 1162 */ 1163 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1164 printf("PCC1 Interface Status Register\n"); 1165 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1166 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1167 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1168 _(P1BVD2);_(P1BVD1); 1169 #undef _ 1170 printf("\n"); 1171 1172 printf("PCC1 General Contorol Register\n"); 1173 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1174 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1175 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1176 #undef _ 1177 printf("\n"); 1178 1179 printf("PCC1 Card Status Change Register\n"); 1180 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1181 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1182 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1183 #undef _ 1184 printf("\n"); 1185 1186 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1187 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1188 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1189 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1190 #undef _ 1191 printf("\n"); 1192 1193 printf("PCC1 Software Control Register\n"); 1194 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1195 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1196 _(P1VCC1);_(P1SWP); 1197 #undef _ 1198 printf("\n"); 1199 1200 /* 1201 * General Control 1202 */ 1203 printf("[General Control]\n"); 1204 printf("PCC0 Output pins Control Register\n"); 1205 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1206 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1207 _(P0DEPLUP);_(P0AEPLUP); 1208 #undef _ 1209 printf("\n"); 1210 1211 printf("PCC1 Output pins Control Register\n"); 1212 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1213 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1214 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1215 #undef _ 1216 printf("\n"); 1217 1218 printf("PC Card General Control Register\n"); 1219 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1220 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1221 _(PSSDIR);_(PSSRDWR); 1222 #undef _ 1223 printf("\n"); 1224 1225 dbg_banner_line(); 1226 } 1227 #endif /* HD64461PCMCIA_DEBUG */ 1228
Indexes created Thu Oct 02 01:09:59 GMT 2025