hd64461pcmcia.c revision 1.5
1 /* $NetBSD: hd64461pcmcia.c,v 1.5 2001/07/13 16:14:29 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #define HD64461PCMCIA_DEBUG 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 #include <sys/boot_flag.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #ifdef DEBUG 51 #include <hpcsh/hpcsh/debug.h> 52 #endif 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcvar.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64461PCMCIA_DEBUG 69 int hd64461pcmcia_debug = 1; 70 #define DPRINTF(fmt, args...) \ 71 if (hd64461pcmcia_debug) \ 72 printf("%s: " fmt, __FUNCTION__ , ##args) 73 #define DPRINTFN(n, arg) \ 74 if (hd64461pcmcia_debug > (n)) \ 75 printf("%s: " fmt, __FUNCTION__ , ##args) 76 #else 77 #define DPRINTF(arg...) ((void)0) 78 #define DPRINTFN(n, arg...) ((void)0) 79 #endif 80 81 enum controller_channel { 82 CHANNEL_0 = 0, 83 CHANNEL_1 = 1, 84 CHANNEL_MAX = 2 85 }; 86 87 enum memory_window_mode { 88 MEMWIN_16M_MODE, 89 MEMWIN_32M_MODE 90 }; 91 92 enum memory_window_16 { 93 MEMWIN_16M_COMMON_0, 94 MEMWIN_16M_COMMON_1, 95 MEMWIN_16M_COMMON_2, 96 MEMWIN_16M_COMMON_3, 97 }; 98 #define MEMWIN_16M_MAX 4 99 100 enum memory_window_32 { 101 MEMWIN_32M_ATTR, 102 MEMWIN_32M_COMMON_0, 103 MEMWIN_32M_COMMON_1, 104 }; 105 #define MEMWIN_32M_MAX 3 106 107 enum hd64461pcmcia_event_type { 108 EVENT_NONE, 109 EVENT_INSERT, 110 EVENT_REMOVE, 111 }; 112 #define EVENT_QUEUE_MAX 5 113 114 struct hd64461pcmcia_softc; /* forward declaration */ 115 116 struct hd64461pcmcia_window_cookie { 117 bus_space_tag_t wc_tag; 118 bus_space_handle_t wc_handle; 119 int wc_size; 120 int wc_window; 121 }; 122 123 struct hd64461pcmcia_channel { 124 struct hd64461pcmcia_softc *ch_parent; 125 struct device *ch_pcmcia; 126 enum controller_channel ch_channel; 127 128 /* memory space */ 129 enum memory_window_mode ch_memory_window_mode; 130 bus_space_tag_t ch_memt; 131 bus_space_handle_t ch_memh; 132 bus_addr_t ch_membase_addr; 133 bus_size_t ch_memsize; 134 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 135 136 /* I/O space */ 137 bus_space_tag_t ch_iot; 138 bus_addr_t ch_iobase; 139 bus_size_t ch_iosize; 140 141 /* card interrupt */ 142 int (*ch_ih_card_func)(void *); 143 void *ch_ih_card_arg; 144 int ch_attached; 145 }; 146 147 struct hd64461pcmcia_event { 148 int __queued; 149 enum hd64461pcmcia_event_type pe_type; 150 struct hd64461pcmcia_channel *pe_ch; 151 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 152 }; 153 154 struct hd64461pcmcia_softc { 155 struct device sc_dev; 156 enum hd64461_module_id sc_module_id; 157 int sc_shutdown; 158 159 /* CSC event */ 160 struct proc *sc_event_thread; 161 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 162 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 163 164 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 165 }; 166 167 static int _chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *); 169 static void _chip_mem_free(pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *); 171 static int _chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, 173 bus_addr_t *, int *); 174 static void _chip_mem_unmap(pcmcia_chipset_handle_t, int); 175 static int _chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 176 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 177 static void _chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 178 static int _chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 static void _chip_io_unmap(pcmcia_chipset_handle_t, int); 181 static void _chip_socket_enable(pcmcia_chipset_handle_t); 182 static void _chip_socket_disable(pcmcia_chipset_handle_t); 183 static void *_chip_intr_establish(pcmcia_chipset_handle_t, 184 struct pcmcia_function *, int, 185 int (*)(void *), void *); 186 static void _chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 187 188 static struct pcmcia_chip_functions hd64461pcmcia_functions = { 189 _chip_mem_alloc, 190 _chip_mem_free, 191 _chip_mem_map, 192 _chip_mem_unmap, 193 _chip_io_alloc, 194 _chip_io_free, 195 _chip_io_map, 196 _chip_io_unmap, 197 _chip_intr_establish, 198 _chip_intr_disestablish, 199 _chip_socket_enable, 200 _chip_socket_disable, 201 }; 202 203 static int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 204 static void hd64461pcmcia_attach(struct device *, struct device *, void *); 205 static int hd64461pcmcia_print(void *, const char *); 206 static int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 207 208 struct cfattach hd64461pcmcia_ca = { 209 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 210 hd64461pcmcia_attach 211 }; 212 213 static void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 214 enum controller_channel); 215 /* hot plug */ 216 static void hd64461pcmcia_create_event_thread(void *); 217 static void hd64461pcmcia_event_thread(void *); 218 static void queue_event(struct hd64461pcmcia_channel *, 219 enum hd64461pcmcia_event_type); 220 /* interrupt handler */ 221 static int hd64461pcmcia_channel0_intr(void *); 222 static int hd64461pcmcia_channel1_intr(void *); 223 /* card status */ 224 static enum hd64461pcmcia_event_type detect_card(enum controller_channel); 225 static void power_off(enum controller_channel) __attribute__((__unused__)); 226 static void power_on(enum controller_channel) __attribute__((__unused__)); 227 /* memory window access ops */ 228 static void memory_window_mode(enum controller_channel, 229 enum memory_window_mode)__attribute__((__unused__)); 230 static void memory_window_16(enum controller_channel, enum memory_window_16); 231 /* bus width */ 232 static void set_bus_width(enum controller_channel, int); 233 #ifdef DEBUG 234 static void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 235 #endif 236 /* fix SH3 Area[56] bug */ 237 static void fixup_sh3_pcmcia_area(bus_space_tag_t); 238 #define _BUS_SPACE_ACCESS_HOOK() \ 239 { \ 240 u_int8_t dummy __attribute__((__unused__)) = \ 241 *(volatile u_int8_t *)0xba000000; \ 242 } 243 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 244 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 245 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 246 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 247 #undef _BUS_SPACE_ACCESS_HOOK 248 249 #define DELAY_MS(x) delay((x) * 1000) 250 251 static int 252 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 253 { 254 struct hd64461_attach_args *ha = aux; 255 256 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 257 } 258 259 static void 260 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 261 { 262 struct hd64461_attach_args *ha = aux; 263 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 264 265 sc->sc_module_id = ha->ha_module_id; 266 267 printf("\n"); 268 269 #ifdef DEBUG 270 if (bootverbose) 271 hd64461pcmcia_info(sc); 272 #endif 273 /* Channel 0/1 common CSC event queue */ 274 SIMPLEQ_INIT (&sc->sc_event_head); 275 kthread_create(hd64461pcmcia_create_event_thread, sc); 276 277 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 278 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 279 } 280 281 static void 282 hd64461pcmcia_create_event_thread(void *arg) 283 { 284 struct hd64461pcmcia_softc *sc = arg; 285 int error; 286 287 error = kthread_create1(hd64461pcmcia_event_thread, sc, 288 &sc->sc_event_thread, "%s", 289 sc->sc_dev.dv_xname); 290 KASSERT(error == 0); 291 } 292 293 static void 294 hd64461pcmcia_event_thread(void *arg) 295 { 296 struct hd64461pcmcia_softc *sc = arg; 297 struct hd64461pcmcia_event *pe; 298 int s; 299 300 while (!sc->sc_shutdown) { 301 tsleep(sc, PWAIT, "CSC wait", 0); 302 s = splhigh(); 303 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 304 splx(s); 305 switch (pe->pe_type) { 306 default: 307 printf("%s: unknown event.\n", __FUNCTION__); 308 break; 309 case EVENT_INSERT: 310 DPRINTF("insert event.\n"); 311 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 312 break; 313 case EVENT_REMOVE: 314 DPRINTF("remove event.\n"); 315 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 316 DETACH_FORCE); 317 break; 318 } 319 s = splhigh(); 320 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 321 pe->__queued = 0; 322 } 323 splx(s); 324 } 325 /* NOTREACHED */ 326 } 327 328 static int 329 hd64461pcmcia_print(void *arg, const char *pnp) 330 { 331 if (pnp) 332 printf("pcmcia at %s", pnp); 333 334 return (UNCONF); 335 } 336 337 static int 338 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 339 { 340 struct pcmciabus_attach_args *paa = aux; 341 struct hd64461pcmcia_channel *ch = 342 (struct hd64461pcmcia_channel *)paa->pch; 343 344 if (ch->ch_channel == CHANNEL_0) { 345 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 346 PCMCIABUSCF_CONTROLLER_DEFAULT && 347 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 348 return 0; 349 } else { 350 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 351 PCMCIABUSCF_CONTROLLER_DEFAULT && 352 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 353 return 0; 354 } 355 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 356 357 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 358 } 359 360 static void 361 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 362 enum controller_channel channel) 363 { 364 struct device *parent = (struct device *)sc; 365 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 366 struct pcmciabus_attach_args paa; 367 bus_addr_t membase; 368 int i; 369 370 ch->ch_parent = sc; 371 ch->ch_channel = channel; 372 373 /* 374 * Continuous 16-MB Area Mode 375 */ 376 /* Attibute/Common memory extent */ 377 membase = (channel == CHANNEL_0) 378 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 379 380 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 381 membase, 0x01000000); /* 16MB */ 382 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 383 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 384 &ch->ch_memh); 385 fixup_sh3_pcmcia_area(ch->ch_memt); 386 387 /* Common memory space extent */ 388 ch->ch_memsize = 0x01000000; 389 for (i = 0; i < MEMWIN_16M_MAX; i++) { 390 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 391 membase + 0x01000000, 392 ch->ch_memsize); 393 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 394 } 395 396 /* I/O port extent and interrupt staff */ 397 _chip_socket_disable(ch); /* enable CSC interrupt only */ 398 399 if (channel == CHANNEL_0) { 400 ch->ch_iobase = 0; 401 ch->ch_iosize = HD64461_PCC0_IOSIZE; 402 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 403 HD64461_PCC0_IOBASE, 404 ch->ch_iosize); 405 fixup_sh3_pcmcia_area(ch->ch_iot); 406 407 hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 408 hd64461pcmcia_channel0_intr, ch); 409 } else { 410 set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 411 hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 412 hd64461pcmcia_channel1_intr, ch); 413 } 414 415 paa.paa_busname = "pcmcia"; 416 paa.pch = (pcmcia_chipset_handle_t)ch; 417 paa.iobase = ch->ch_iobase; 418 paa.iosize = ch->ch_iosize; 419 420 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 421 hd64461pcmcia_submatch); 422 423 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 424 ch->ch_attached = 1; 425 pcmcia_card_attach(ch->ch_pcmcia); 426 } 427 } 428 429 static int 430 hd64461pcmcia_channel0_intr(void *arg) 431 { 432 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 433 u_int8_t r; 434 int ret = 0; 435 436 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 437 /* clear interrtupt (edge source only) */ 438 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 439 440 if (r & HD64461_PCC0CSCR_P0IREQ) { 441 if (ch->ch_ih_card_func) { 442 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 443 } else 444 DPRINTF("spurious IREQ interrupt.\n"); 445 } 446 447 if (r & HD64461_PCC0CSCR_P0CDC) 448 queue_event(ch, detect_card(ch->ch_channel)); 449 450 return ret; 451 } 452 453 static int 454 hd64461pcmcia_channel1_intr(void *arg) 455 { 456 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 457 u_int8_t r; 458 int ret = 0; 459 460 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 461 /* clear interrtupt */ 462 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 463 464 if (r & HD64461_PCC1CSCR_P1RC) { 465 if (ch->ch_ih_card_func) 466 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 467 else 468 DPRINTF("spurious READY interrupt.\n"); 469 } 470 471 if (r & HD64461_PCC1CSCR_P1CDC) 472 queue_event(ch, detect_card(ch->ch_channel)); 473 474 return ret; 475 } 476 477 static void 478 queue_event(struct hd64461pcmcia_channel *ch, 479 enum hd64461pcmcia_event_type type) 480 { 481 struct hd64461pcmcia_event *pe, *pool; 482 struct hd64461pcmcia_softc *sc = ch->ch_parent; 483 int i; 484 int s = splhigh(); 485 486 if (type == EVENT_NONE) 487 goto out; 488 489 pe = 0; 490 pool = sc->sc_event_pool; 491 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 492 if (!pool[i].__queued) { 493 pe = &pool[i]; 494 break; 495 } 496 } 497 498 if (pe == 0) { 499 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 500 EVENT_QUEUE_MAX); 501 goto out; 502 } 503 504 if ((ch->ch_attached && (type == EVENT_INSERT)) || 505 (!ch->ch_attached && (type == EVENT_REMOVE))) { 506 DPRINTF("spurious CSC interrupt.\n"); 507 goto out; 508 } 509 510 ch->ch_attached = (type == EVENT_INSERT); 511 pe->__queued = 1; 512 pe->pe_type = type; 513 pe->pe_ch = ch; 514 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 515 wakeup(sc); 516 out: 517 splx(s); 518 } 519 520 /* 521 * interface for pcmcia driver. 522 */ 523 static void * 524 _chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, 525 int ipl, int (*ih_func)(void *), void *ih_arg) 526 { 527 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 528 int channel = ch->ch_channel; 529 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 530 int s = splhigh(); 531 u_int8_t r; 532 533 ch->ch_ih_card_func = ih_func; 534 ch->ch_ih_card_arg = ih_arg; 535 536 /* enable card interrupt */ 537 r = hd64461_reg_read_1(cscier); 538 if (channel == CHANNEL_0) { 539 /* set level mode */ 540 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 541 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 542 } else { 543 /* READY-pin LOW to HIGH changes generates interrupt */ 544 r |= HD64461_PCC1CSCIER_P1RE; 545 } 546 hd64461_reg_write_1(cscier, r); 547 548 splx(s); 549 550 return (void *)ih_func; 551 } 552 553 static void 554 _chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 555 { 556 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 557 int channel = ch->ch_channel; 558 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 559 int s = splhigh(); 560 u_int8_t r; 561 562 /* disable card interrupt */ 563 r = hd64461_reg_read_1(cscier); 564 if (channel == CHANNEL_0) { 565 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 566 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 567 } else { 568 r &= ~HD64461_PCC1CSCIER_P1RE; 569 } 570 hd64461_reg_write_1(cscier, r); 571 572 ch->ch_ih_card_func = 0; 573 574 splx(s); 575 } 576 577 static int 578 _chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 579 struct pcmcia_mem_handle *pcmhp) 580 { 581 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 582 583 pcmhp->memt = ch->ch_memt; 584 pcmhp->addr = ch->ch_membase_addr; 585 pcmhp->memh = ch->ch_memh; 586 pcmhp->size = size; 587 pcmhp->realsize = size; 588 589 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 590 591 return (0); 592 } 593 594 static void 595 _chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 596 { 597 /* nothing to do */ 598 } 599 600 static int 601 _chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, 602 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 603 bus_addr_t *offsetp, int *windowp) 604 { 605 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 606 struct hd64461pcmcia_window_cookie *cookie; 607 bus_addr_t ofs; 608 609 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 610 M_DEVBUF, M_NOWAIT); 611 KASSERT(cookie); 612 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 613 614 /* Address */ 615 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 616 cookie->wc_tag = ch->ch_memt; 617 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 618 size, &cookie->wc_handle) != 0) 619 goto bad; 620 621 *offsetp = card_addr; 622 cookie->wc_window = -1; 623 } else { 624 int window = card_addr / ch->ch_memsize; 625 KASSERT(window < MEMWIN_16M_MAX); 626 627 cookie->wc_tag = ch->ch_cmemt[window]; 628 ofs = card_addr - window * ch->ch_memsize; 629 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 630 &cookie->wc_handle) != 0) 631 goto bad; 632 633 /* XXX bogus. check window per common memory access. */ 634 memory_window_16(ch->ch_channel, window); 635 *offsetp = ofs + 0x01000000; /* skip attribute area */ 636 cookie->wc_window = window; 637 } 638 cookie->wc_size = size; 639 *windowp = (int)cookie; 640 641 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 642 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 643 size); 644 645 return (0); 646 bad: 647 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 648 free(cookie, M_DEVBUF); 649 650 return (1); 651 } 652 653 static void 654 _chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 655 { 656 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 657 658 if (cookie->wc_window != -1) 659 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 660 cookie->wc_size); 661 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 662 free(cookie, M_DEVBUF); 663 } 664 665 static int 666 _chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, 667 bus_size_t align, struct pcmcia_io_handle *pcihp) 668 { 669 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 670 671 if (ch->ch_channel == CHANNEL_1) 672 return (1); 673 674 if (start) { 675 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 676 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 677 return (1); 678 } 679 DPRINTF("map %#lx+%#lx\n", start, size); 680 } else { 681 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 682 ch->ch_iobase + ch->ch_iosize - 1, 683 size, align, 0, 0, &pcihp->addr, 684 &pcihp->ioh)) { 685 DPRINTF("couldn't allocate %#lx\n", size); 686 return (1); 687 } 688 pcihp->flags = PCMCIA_IO_ALLOCATED; 689 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 690 } 691 692 pcihp->iot = ch->ch_iot; 693 pcihp->size = size; 694 695 return (0); 696 } 697 698 static int 699 _chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 700 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 701 { 702 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 703 #ifdef HD64461PCMCIA_DEBUG 704 static char *width_names[] = { "auto", "io8", "io16" }; 705 #endif 706 if (ch->ch_channel == CHANNEL_1) 707 return (1); 708 709 set_bus_width(CHANNEL_0, width); 710 711 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 712 width_names[width]); 713 714 return (0); 715 } 716 717 static void 718 _chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 719 { 720 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 721 722 if (ch->ch_channel == CHANNEL_1) 723 return; 724 725 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 726 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 727 else 728 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 729 730 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 731 } 732 733 static void 734 _chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 735 { 736 /* nothing to do */ 737 } 738 739 static void 740 _chip_socket_enable(pcmcia_chipset_handle_t pch) 741 { 742 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 743 int channel = ch->ch_channel; 744 bus_addr_t isr, gcr; 745 u_int8_t r; 746 int cardtype; 747 748 DPRINTF("enable channel %d\n", channel); 749 isr = HD64461_PCCISR(channel); 750 gcr = HD64461_PCCGCR(channel); 751 752 power_off(channel); 753 power_on(channel); 754 #if notyet 755 { 756 int i; 757 /* assert reset */ 758 r = hd64461_reg_read_1(gcr); 759 r |= HD64461_PCCGCR_PCCR; 760 hd64461_reg_write_1(gcr, r); 761 762 /* 763 * hold RESET at least 10us. 764 */ 765 DELAY_MS(20); 766 767 /* clear the reset flag */ 768 r &= ~HD64461_PCCGCR_PCCR; 769 hd64461_reg_write_1(gcr, r); 770 DELAY_MS(2000); 771 772 /* wait for the chip to finish initializing */ 773 for (i = 0; i < 10000; i++) { 774 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 775 goto reset_ok; 776 DELAY_MS(500); 777 778 if ((i > 5000) && (i % 100 == 99)) 779 printf("."); 780 } 781 printf("reset failed.\n"); 782 power_off(channel); 783 return; 784 reset_ok: 785 } 786 #endif /* notyet */ 787 /* set Continuous 16-MB Area Mode */ 788 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 789 memory_window_mode(channel, ch->ch_memory_window_mode); 790 791 /* 792 * set Common memory area. 793 */ 794 memory_window_16(channel, MEMWIN_16M_COMMON_0); 795 796 /* set the card type */ 797 if (channel == CHANNEL_0) { 798 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 799 r = hd64461_reg_read_1(gcr); 800 if (cardtype == PCMCIA_IFTYPE_IO) 801 r |= HD64461_PCC0GCR_P0PCCT; 802 else 803 r &= ~HD64461_PCC0GCR_P0PCCT; 804 hd64461_reg_write_1(gcr, r); 805 } 806 807 DPRINTF("OK.\n"); 808 } 809 810 static void 811 _chip_socket_disable(pcmcia_chipset_handle_t pch) 812 { 813 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 814 int channel = ch->ch_channel; 815 816 /* dont' disable CSC interrupt */ 817 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 818 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 819 820 /* power down the socket */ 821 power_off(channel); 822 } 823 824 /* 825 * Card detect 826 */ 827 static void 828 power_off(enum controller_channel channel) 829 { 830 #if notyet 831 u_int8_t r; 832 u_int16_t r16; 833 bus_addr_t scr, gcr; 834 835 gcr = HD64461_PCCGCR(channel); 836 scr = HD64461_PCCSCR(channel); 837 838 /* DRV (external buffer) high level */ 839 r = hd64461_reg_read_1(gcr); 840 r &= ~HD64461_PCCGCR_DRVE; 841 hd64461_reg_write_1(gcr, r); 842 843 /* stop power */ 844 r = hd64461_reg_read_1(scr); 845 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 846 hd64461_reg_write_1(scr, r); 847 r = hd64461_reg_read_1(gcr); 848 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 849 hd64461_reg_write_1(gcr, r); 850 /* 851 * wait 300ms until power fails (Tpf). Then, wait 100ms since 852 * we are changing Vcc (Toff). 853 */ 854 DELAY_MS(300 + 100); 855 856 /* stop clock */ 857 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 858 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 859 HD64461_SYSSTBCR_SPC1ST); 860 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 861 862 if (channel == CHANNEL_0) { 863 /* GPIO Port A XXX Jornada690 specific? */ 864 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 865 r16 |= 0xf; 866 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 867 } 868 869 #endif /* notyet */ 870 } 871 872 static void 873 power_on(enum controller_channel channel) 874 { 875 u_int8_t r; 876 u_int16_t r16; 877 bus_addr_t scr, gcr, isr; 878 879 isr = HD64461_PCCISR(channel); 880 gcr = HD64461_PCCGCR(channel); 881 scr = HD64461_PCCSCR(channel); 882 883 /* 884 * XXX to access attribute memory, this is required. 885 */ 886 if (channel == CHANNEL_0) { 887 /* GPIO Port A XXX Jonanada690 specific? */ 888 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 889 r16 &= ~0xf; 890 r16 |= 0x5; 891 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 892 } 893 894 if (channel == CHANNEL_1) { 895 /* GPIO Port C, Port D XXX HP620LX specific? */ 896 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 897 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 898 } 899 900 /* supply clock */ 901 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 902 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 903 HD64461_SYSSTBCR_SPC1ST); 904 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 905 DELAY_MS(200); 906 907 /* detect voltage and supply VCC */ 908 r = hd64461_reg_read_1(isr); 909 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 910 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): 911 DPRINTF("5V card\n"); 912 r = hd64461_reg_read_1(gcr); 913 r &= ~HD64461_PCCGCR_VCC0; 914 hd64461_reg_write_1(gcr, r); 915 r = hd64461_reg_read_1(scr); 916 r &= ~HD64461_PCCSCR_VCC1; 917 hd64461_reg_write_1(scr, r); 918 break; 919 case HD64461_PCCISR_VS2: 920 DPRINTF("3.3V card\n"); 921 if (channel == CHANNEL_1) { 922 r = hd64461_reg_read_1(gcr); 923 r &= ~HD64461_PCCGCR_VCC0; 924 hd64461_reg_write_1(gcr, r); 925 } else { 926 r = hd64461_reg_read_1(gcr); 927 r |= HD64461_PCCGCR_VCC0; 928 hd64461_reg_write_1(gcr, r); 929 } 930 r = hd64461_reg_read_1(scr); 931 r &= ~HD64461_PCCSCR_VCC1; 932 hd64461_reg_write_1(scr, r); 933 break; 934 default: 935 printf("\nunknown Voltage. don't attach.\n"); 936 return; 937 } 938 /* 939 * wait 100ms until power raise (Tpr) and 20ms to become 940 * stable (Tsu(Vcc)). 941 * 942 * some machines require some more time to be settled 943 * (300ms is added here). 944 */ 945 DELAY_MS(100 + 20 + 300); 946 947 /* DRV (external buffer) low level */ 948 r = hd64461_reg_read_1(gcr); 949 r |= HD64461_PCCGCR_DRVE; 950 hd64461_reg_write_1(gcr, r); 951 952 /* clear interrupt */ 953 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 954 HD64461_PCC1CSCR_REG8, 0); 955 } 956 957 static enum hd64461pcmcia_event_type 958 detect_card(enum controller_channel channel) 959 { 960 u_int8_t r; 961 962 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 963 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 964 965 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 966 DPRINTF("remove\n"); 967 return EVENT_REMOVE; 968 } 969 if (r == 0) { 970 DPRINTF("insert\n"); 971 return EVENT_INSERT; 972 } 973 DPRINTF("transition\n"); 974 975 return EVENT_NONE; 976 } 977 978 /* 979 * Memory window access ops. 980 */ 981 static void 982 memory_window_mode(enum controller_channel channel, 983 enum memory_window_mode mode) 984 { 985 bus_addr_t a = HD64461_PCCGCR(channel); 986 u_int8_t r = hd64461_reg_read_1(a); 987 988 r &= ~HD64461_PCCGCR_MMOD; 989 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 990 HD64461_PCCGCR_MMOD_32M; 991 hd64461_reg_write_1(a, r); 992 } 993 994 static void 995 memory_window_16(enum controller_channel channel, enum memory_window_16 window) 996 { 997 bus_addr_t a = HD64461_PCCGCR(channel); 998 u_int8_t r; 999 1000 r = hd64461_reg_read_1(a); 1001 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1002 1003 switch (window) { 1004 case MEMWIN_16M_COMMON_0: 1005 break; 1006 case MEMWIN_16M_COMMON_1: 1007 r |= HD64461_PCCGCR_PA24; 1008 break; 1009 case MEMWIN_16M_COMMON_2: 1010 r |= HD64461_PCCGCR_PA25; 1011 break; 1012 case MEMWIN_16M_COMMON_3: 1013 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1014 break; 1015 } 1016 1017 hd64461_reg_write_1(a, r); 1018 } 1019 1020 #if unused 1021 static void 1022 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1023 { 1024 bus_addr_t a = HD64461_PCCGCR(channel); 1025 u_int8_t r; 1026 1027 r = hd64461_reg_read_1(a); 1028 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1029 1030 switch (window) { 1031 case MEMWIN_32M_ATTR: 1032 break; 1033 case MEMWIN_32M_COMMON_0: 1034 r |= HD64461_PCCGCR_PREG; 1035 break; 1036 case MEMWIN_32M_COMMON_1: 1037 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1038 break; 1039 } 1040 1041 hd64461_reg_write_1(a, r); 1042 } 1043 #endif 1044 1045 static void 1046 set_bus_width(enum controller_channel channel, int width) 1047 { 1048 u_int16_t r16; 1049 1050 r16 = SHREG_BCR2; 1051 if (channel == CHANNEL_0) { 1052 r16 &= ~((1 << 13)|(1 << 12)); 1053 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1054 } else { 1055 r16 &= ~((1 << 11)|(1 << 10)); 1056 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1057 } 1058 SHREG_BCR2 = r16; 1059 } 1060 1061 static void 1062 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1063 { 1064 struct hpcsh_bus_space *hbs = (void *)t; 1065 1066 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1067 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1068 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1069 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1070 } 1071 1072 #ifdef DEBUG 1073 static void 1074 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1075 { 1076 const char name[] = __FUNCTION__; 1077 u_int8_t r8; 1078 1079 dbg_banner_start(name, sizeof name); 1080 /* 1081 * PCC0 1082 */ 1083 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1084 printf("PCC0 Interface Status Register\n"); 1085 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1086 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 1087 DBG_BIT_PRINT(r8, P0READY); 1088 DBG_BIT_PRINT(r8, P0MWP); 1089 DBG_BIT_PRINT(r8, P0VS2); 1090 DBG_BIT_PRINT(r8, P0VS1); 1091 DBG_BIT_PRINT(r8, P0CD2); 1092 DBG_BIT_PRINT(r8, P0CD1); 1093 DBG_BIT_PRINT(r8, P0BVD2); 1094 DBG_BIT_PRINT(r8, P0BVD1); 1095 #undef DBG_BIT_PRINT 1096 printf("\n"); 1097 1098 printf("PCC0 General Control Register\n"); 1099 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1100 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 1101 DBG_BIT_PRINT(r8, P0DRVE); 1102 DBG_BIT_PRINT(r8, P0PCCR); 1103 DBG_BIT_PRINT(r8, P0PCCT); 1104 DBG_BIT_PRINT(r8, P0VCC0); 1105 DBG_BIT_PRINT(r8, P0MMOD); 1106 DBG_BIT_PRINT(r8, P0PA25); 1107 DBG_BIT_PRINT(r8, P0PA24); 1108 DBG_BIT_PRINT(r8, P0REG); 1109 #undef DBG_BIT_PRINT 1110 printf("\n"); 1111 1112 printf("PCC0 Card Status Change Register\n"); 1113 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1114 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 1115 DBG_BIT_PRINT(r8, P0SCDI); 1116 DBG_BIT_PRINT(r8, P0IREQ); 1117 DBG_BIT_PRINT(r8, P0SC); 1118 DBG_BIT_PRINT(r8, P0CDC); 1119 DBG_BIT_PRINT(r8, P0RC); 1120 DBG_BIT_PRINT(r8, P0BW); 1121 DBG_BIT_PRINT(r8, P0BD); 1122 #undef DBG_BIT_PRINT 1123 printf("\n"); 1124 1125 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1126 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1127 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 1128 DBG_BIT_PRINT(r8, P0CRE); 1129 DBG_BIT_PRINT(r8, P0SCE); 1130 DBG_BIT_PRINT(r8, P0CDE); 1131 DBG_BIT_PRINT(r8, P0RE); 1132 DBG_BIT_PRINT(r8, P0BWE); 1133 DBG_BIT_PRINT(r8, P0BDE); 1134 #undef DBG_BIT_PRINT 1135 printf("\ninterrupt type: "); 1136 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1137 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1138 printf("none\n"); 1139 break; 1140 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1141 printf("level\n"); 1142 break; 1143 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1144 printf("falling edge\n"); 1145 break; 1146 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1147 printf("rising edge\n"); 1148 break; 1149 } 1150 1151 printf("PCC0 Software Control Register\n"); 1152 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1153 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 1154 DBG_BIT_PRINT(r8, P0VCC1); 1155 DBG_BIT_PRINT(r8, P0SWP); 1156 #undef DBG_BIT_PRINT 1157 printf("\n"); 1158 1159 /* 1160 * PCC1 1161 */ 1162 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1163 printf("PCC1 Interface Status Register\n"); 1164 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1165 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 1166 DBG_BIT_PRINT(r8, P1READY); 1167 DBG_BIT_PRINT(r8, P1MWP); 1168 DBG_BIT_PRINT(r8, P1VS2); 1169 DBG_BIT_PRINT(r8, P1VS1); 1170 DBG_BIT_PRINT(r8, P1CD2); 1171 DBG_BIT_PRINT(r8, P1CD1); 1172 DBG_BIT_PRINT(r8, P1BVD2); 1173 DBG_BIT_PRINT(r8, P1BVD1); 1174 #undef DBG_BIT_PRINT 1175 printf("\n"); 1176 1177 printf("PCC1 General Contorol Register\n"); 1178 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1179 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 1180 DBG_BIT_PRINT(r8, P1DRVE); 1181 DBG_BIT_PRINT(r8, P1PCCR); 1182 DBG_BIT_PRINT(r8, P1VCC0); 1183 DBG_BIT_PRINT(r8, P1MMOD); 1184 DBG_BIT_PRINT(r8, P1PA25); 1185 DBG_BIT_PRINT(r8, P1PA24); 1186 DBG_BIT_PRINT(r8, P1REG); 1187 #undef DBG_BIT_PRINT 1188 printf("\n"); 1189 1190 printf("PCC1 Card Status Change Register\n"); 1191 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1192 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 1193 DBG_BIT_PRINT(r8, P1SCDI); 1194 DBG_BIT_PRINT(r8, P1CDC); 1195 DBG_BIT_PRINT(r8, P1RC); 1196 DBG_BIT_PRINT(r8, P1BW); 1197 DBG_BIT_PRINT(r8, P1BD); 1198 #undef DBG_BIT_PRINT 1199 printf("\n"); 1200 1201 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1202 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1203 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 1204 DBG_BIT_PRINT(r8, P1CRE); 1205 DBG_BIT_PRINT(r8, P1CDE); 1206 DBG_BIT_PRINT(r8, P1RE); 1207 DBG_BIT_PRINT(r8, P1BWE); 1208 DBG_BIT_PRINT(r8, P1BDE); 1209 #undef DBG_BIT_PRINT 1210 printf("\n"); 1211 1212 printf("PCC1 Software Control Register\n"); 1213 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1214 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 1215 DBG_BIT_PRINT(r8, P1VCC1); 1216 DBG_BIT_PRINT(r8, P1SWP); 1217 #undef DBG_BIT_PRINT 1218 printf("\n"); 1219 1220 /* 1221 * General Control 1222 */ 1223 printf("[General Control]\n"); 1224 printf("PCC0 Output pins Control Register\n"); 1225 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1226 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 1227 DBG_BIT_PRINT(r8, P0DEPLUP); 1228 DBG_BIT_PRINT(r8, P0AEPLUP); 1229 #undef DBG_BIT_PRINT 1230 printf("\n"); 1231 1232 printf("PCC1 Output pins Control Register\n"); 1233 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1234 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 1235 DBG_BIT_PRINT(r8, P1RST8MA); 1236 DBG_BIT_PRINT(r8, P1RST4MA); 1237 DBG_BIT_PRINT(r8, P1RAS8MA); 1238 DBG_BIT_PRINT(r8, P1RAS4MA); 1239 #undef DBG_BIT_PRINT 1240 printf("\n"); 1241 1242 printf("PC Card General Control Register\n"); 1243 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1244 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 1245 DBG_BIT_PRINT(r8, PSSDIR); 1246 DBG_BIT_PRINT(r8, PSSRDWR); 1247 #undef DBG_BIT_PRINT 1248 printf("\n"); 1249 1250 dbg_banner_end(); 1251 } 1252 #endif /* DEBUG */ 1253
Indexes created Thu Oct 02 01:09:59 GMT 2025