hd64461pcmcia.c revision 1.53
1 /* $NetBSD: hd64461pcmcia.c,v 1.53 2021/04/24 23:36:38 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.53 2021/04/24 23:36:38 thorpej Exp $"); 34 35 #include "opt_hd64461pcmcia.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/kmem.h> 41 #include <sys/kthread.h> 42 #include <sys/boot_flag.h> 43 #include <sys/bus.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 53 #include <hpcsh/dev/hd64461/hd64461reg.h> 54 #include <hpcsh/dev/hd64461/hd64461var.h> 55 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 56 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 58 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 59 60 #include <hpcsh/bus_util.h> /* for _BUS_SPACE_WRITE(), et cetera */ 61 62 #include "locators.h" 63 64 #ifdef HD64461PCMCIA_DEBUG 65 #define DPRINTF_ENABLE 66 #define DPRINTF_DEBUG hd64461pcmcia_debug 67 #endif 68 #include <machine/debug.h> 69 70 enum controller_channel { 71 CHANNEL_0 = 0, 72 CHANNEL_1 = 1, 73 CHANNEL_MAX = 2 74 }; 75 76 enum memory_window_mode { 77 MEMWIN_16M_MODE, 78 MEMWIN_32M_MODE 79 }; 80 81 enum memory_window_16 { 82 MEMWIN_16M_COMMON_0, 83 MEMWIN_16M_COMMON_1, 84 MEMWIN_16M_COMMON_2, 85 MEMWIN_16M_COMMON_3, 86 }; 87 #define MEMWIN_16M_MAX 4 88 89 enum memory_window_32 { 90 MEMWIN_32M_ATTR, 91 MEMWIN_32M_COMMON_0, 92 MEMWIN_32M_COMMON_1, 93 }; 94 #define MEMWIN_32M_MAX 3 95 96 enum hd64461pcmcia_event_type { 97 EVENT_NONE, 98 EVENT_INSERT, 99 EVENT_REMOVE, 100 }; 101 #define EVENT_QUEUE_MAX 5 102 103 struct hd64461pcmcia_softc; /* forward declaration */ 104 105 struct hd64461pcmcia_window_cookie { 106 bus_space_tag_t wc_tag; 107 bus_space_handle_t wc_handle; 108 int wc_size; 109 int wc_window; 110 }; 111 112 struct hd64461pcmcia_channel { 113 struct hd64461pcmcia_softc *ch_parent; 114 device_t ch_pcmcia; 115 enum controller_channel ch_channel; 116 117 /* memory space */ 118 enum memory_window_mode ch_memory_window_mode; 119 bus_space_tag_t ch_memt; 120 bus_space_handle_t ch_memh; 121 bus_addr_t ch_membase_addr; 122 bus_size_t ch_memsize; 123 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 124 125 /* I/O space */ 126 bus_space_tag_t ch_iot; 127 bus_addr_t ch_iobase; 128 bus_size_t ch_iosize; 129 130 /* card interrupt */ 131 int (*ch_ih_card_func)(void *); 132 void *ch_ih_card_arg; 133 int ch_attached; 134 }; 135 136 struct hd64461pcmcia_event { 137 int __queued; 138 enum hd64461pcmcia_event_type pe_type; 139 struct hd64461pcmcia_channel *pe_ch; 140 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 141 }; 142 143 struct hd64461pcmcia_softc { 144 device_t sc_dev; 145 146 enum hd64461_module_id sc_module_id; 147 int sc_shutdown; 148 149 /* CSC event */ 150 lwp_t *sc_event_thread; 151 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 152 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 153 154 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 155 }; 156 157 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 158 struct pcmcia_mem_handle *); 159 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 160 struct pcmcia_mem_handle *); 161 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 162 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 163 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 164 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 165 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 166 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 167 struct pcmcia_io_handle *); 168 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_io_handle *, int *); 170 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 171 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 172 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 hd64461pcmcia_chip_socket_settype, 193 }; 194 195 STATIC int hd64461pcmcia_match(device_t, cfdata_t, void *); 196 STATIC void hd64461pcmcia_attach(device_t, device_t, void *); 197 STATIC int hd64461pcmcia_print(void *, const char *); 198 STATIC int hd64461pcmcia_submatch(device_t, cfdata_t, const int *, void *); 199 200 CFATTACH_DECL_NEW(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 201 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 202 203 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 204 enum controller_channel); 205 /* hot plug */ 206 STATIC void hd64461pcmcia_event_thread(void *); 207 STATIC void queue_event(struct hd64461pcmcia_channel *, 208 enum hd64461pcmcia_event_type); 209 /* interrupt handler */ 210 STATIC int hd64461pcmcia_channel0_intr(void *); 211 STATIC int hd64461pcmcia_channel1_intr(void *); 212 /* card status */ 213 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 214 STATIC void hd64461pcmcia_power_off(enum controller_channel); 215 STATIC void hd64461pcmcia_power_on(enum controller_channel); 216 /* memory window access ops */ 217 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 218 enum memory_window_mode)__attribute__((__unused__)); 219 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 220 enum memory_window_16); 221 /* bus width */ 222 STATIC void hd64461_set_bus_width(enum controller_channel, int); 223 #ifdef HD64461PCMCIA_DEBUG 224 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 225 #endif 226 /* fix SH3 Area[56] bug */ 227 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 228 #define _BUS_SPACE_ACCESS_HOOK() \ 229 do { \ 230 uint8_t dummy __attribute__((__unused__)) = \ 231 *(volatile uint8_t *)0xba000000; \ 232 } while (/*CONSTCOND*/0) 233 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 234 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 235 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 236 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 237 #undef _BUS_SPACE_ACCESS_HOOK 238 239 #define DELAY_MS(x) delay((x) * 1000) 240 241 STATIC int 242 hd64461pcmcia_match(device_t parent, cfdata_t cf, void *aux) 243 { 244 struct hd64461_attach_args *ha = aux; 245 246 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 247 } 248 249 STATIC void 250 hd64461pcmcia_attach(device_t parent, device_t self, void *aux) 251 { 252 struct hd64461_attach_args *ha = aux; 253 struct hd64461pcmcia_softc *sc; 254 int error __diagused; 255 256 sc = device_private(self); 257 sc->sc_dev = self; 258 259 sc->sc_module_id = ha->ha_module_id; 260 261 aprint_naive("\n"); 262 aprint_normal("\n"); 263 264 #ifdef HD64461PCMCIA_DEBUG 265 hd64461pcmcia_info(sc); 266 #endif 267 /* Channel 0/1 common CSC event queue */ 268 SIMPLEQ_INIT (&sc->sc_event_head); 269 270 error = kthread_create(PRI_NONE, 0, NULL, 271 hd64461pcmcia_event_thread, sc, 272 &sc->sc_event_thread, 273 "%s", device_xname(self)); 274 KASSERT(error == 0); 275 276 config_pending_incr(self); 277 278 /* XXX: TODO */ 279 if (!pmf_device_register(self, NULL, NULL)) 280 aprint_error_dev(self, "unable to establish power handler\n"); 281 } 282 283 STATIC void 284 hd64461pcmcia_event_thread(void *arg) 285 { 286 struct hd64461pcmcia_softc *sc = arg; 287 struct hd64461pcmcia_event *pe; 288 int s; 289 290 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 291 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 292 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 293 #else 294 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 295 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 296 #endif 297 config_pending_decr(sc->sc_dev); 298 299 while (!sc->sc_shutdown) { 300 tsleep(sc, PWAIT, "CSC wait", 0); 301 s = splhigh(); 302 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 303 splx(s); 304 switch (pe->pe_type) { 305 default: 306 printf("%s: unknown event.\n", __func__); 307 break; 308 case EVENT_INSERT: 309 DPRINTF("insert event.\n"); 310 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 311 break; 312 case EVENT_REMOVE: 313 DPRINTF("remove event.\n"); 314 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 315 DETACH_FORCE); 316 break; 317 } 318 s = splhigh(); 319 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 320 pe->__queued = 0; 321 } 322 splx(s); 323 } 324 325 sc->sc_event_thread = NULL; 326 kthread_exit(0); 327 /* NOTREACHED */ 328 } 329 330 STATIC int 331 hd64461pcmcia_print(void *arg, const char *pnp) 332 { 333 334 if (pnp) 335 aprint_normal("pcmcia at %s", pnp); 336 337 return (UNCONF); 338 } 339 340 STATIC int 341 hd64461pcmcia_submatch(device_t parent, cfdata_t cf, 342 const int *ldesc, void *aux) 343 { 344 struct pcmciabus_attach_args *paa = aux; 345 struct hd64461pcmcia_channel *ch = 346 (struct hd64461pcmcia_channel *)paa->pch; 347 348 if (ch->ch_channel == CHANNEL_0) { 349 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 350 PCMCIABUSCF_CONTROLLER_DEFAULT && 351 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 352 return 0; 353 } else { 354 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 355 PCMCIABUSCF_CONTROLLER_DEFAULT && 356 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 357 return 0; 358 } 359 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 360 361 return (config_match(parent, cf, aux)); 362 } 363 364 STATIC void 365 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 366 enum controller_channel channel) 367 { 368 device_t parent = sc->sc_dev; 369 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 370 struct pcmciabus_attach_args paa; 371 bus_addr_t membase; 372 int i; 373 374 ch->ch_parent = sc; 375 ch->ch_channel = channel; 376 377 /* 378 * Continuous 16-MB Area Mode 379 */ 380 /* Attibute/Common memory extent */ 381 membase = (channel == CHANNEL_0) 382 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 383 384 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 385 membase, 0x01000000); /* 16MB */ 386 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 387 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 388 &ch->ch_memh); 389 fixup_sh3_pcmcia_area(ch->ch_memt); 390 391 /* Common memory space extent */ 392 ch->ch_memsize = 0x01000000; 393 for (i = 0; i < MEMWIN_16M_MAX; i++) { 394 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 395 membase + 0x01000000, 396 ch->ch_memsize); 397 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 398 } 399 400 /* I/O port extent and interrupt staff */ 401 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 402 403 if (channel == CHANNEL_0) { 404 ch->ch_iobase = 0; 405 ch->ch_iosize = HD64461_PCC0_IOSIZE; 406 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 407 HD64461_PCC0_IOBASE, 408 ch->ch_iosize); 409 fixup_sh3_pcmcia_area(ch->ch_iot); 410 411 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 412 hd64461pcmcia_channel0_intr, ch); 413 } else { 414 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 415 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 416 hd64461pcmcia_channel1_intr, ch); 417 } 418 419 paa.paa_busname = "pcmcia"; 420 paa.pch = (pcmcia_chipset_handle_t)ch; 421 422 ch->ch_pcmcia = config_found(parent, &paa, hd64461pcmcia_print, 423 CFARG_SUBMATCH, hd64461pcmcia_submatch, 424 CFARG_EOL); 425 426 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 427 ch->ch_attached = 1; 428 pcmcia_card_attach(ch->ch_pcmcia); 429 } 430 } 431 432 STATIC int 433 hd64461pcmcia_channel0_intr(void *arg) 434 { 435 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 436 uint8_t r; 437 int ret = 0; 438 439 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 440 /* clear interrtupt (edge source only) */ 441 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 442 443 if (r & HD64461_PCC0CSCR_P0IREQ) { 444 if (ch->ch_ih_card_func) { 445 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 446 } else 447 DPRINTF("spurious IREQ interrupt.\n"); 448 } 449 450 if (r & HD64461_PCC0CSCR_P0CDC) 451 queue_event(ch, detect_card(ch->ch_channel)); 452 453 return ret; 454 } 455 456 STATIC int 457 hd64461pcmcia_channel1_intr(void *arg) 458 { 459 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 460 uint8_t r; 461 int ret = 0; 462 463 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 464 /* clear interrtupt */ 465 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 466 467 if (r & HD64461_PCC1CSCR_P1RC) { 468 if (ch->ch_ih_card_func) 469 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 470 else 471 DPRINTF("spurious READY interrupt.\n"); 472 } 473 474 if (r & HD64461_PCC1CSCR_P1CDC) 475 queue_event(ch, detect_card(ch->ch_channel)); 476 477 return ret; 478 } 479 480 STATIC void 481 queue_event(struct hd64461pcmcia_channel *ch, 482 enum hd64461pcmcia_event_type type) 483 { 484 struct hd64461pcmcia_event *pe, *pool; 485 struct hd64461pcmcia_softc *sc = ch->ch_parent; 486 int i; 487 int s = splhigh(); 488 489 if (type == EVENT_NONE) 490 goto out; 491 492 pe = 0; 493 pool = sc->sc_event_pool; 494 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 495 if (!pool[i].__queued) { 496 pe = &pool[i]; 497 break; 498 } 499 } 500 501 if (pe == 0) { 502 printf("%s: event FIFO overflow (max %d).\n", __func__, 503 EVENT_QUEUE_MAX); 504 goto out; 505 } 506 507 if ((ch->ch_attached && (type == EVENT_INSERT)) || 508 (!ch->ch_attached && (type == EVENT_REMOVE))) { 509 DPRINTF("spurious CSC interrupt.\n"); 510 goto out; 511 } 512 513 ch->ch_attached = (type == EVENT_INSERT); 514 pe->__queued = 1; 515 pe->pe_type = type; 516 pe->pe_ch = ch; 517 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 518 wakeup(sc); 519 out: 520 splx(s); 521 } 522 523 /* 524 * interface for pcmcia driver. 525 */ 526 STATIC void * 527 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 528 struct pcmcia_function *pf, 529 int ipl, int (*ih_func)(void *), void *ih_arg) 530 { 531 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 532 int channel = ch->ch_channel; 533 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 534 int s = splhigh(); 535 uint8_t r; 536 537 ch->ch_ih_card_func = ih_func; 538 ch->ch_ih_card_arg = ih_arg; 539 540 /* enable card interrupt */ 541 r = hd64461_reg_read_1(cscier); 542 if (channel == CHANNEL_0) { 543 /* set level mode */ 544 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 545 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 546 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 547 } else { 548 /* READY-pin LOW to HIGH changes generates interrupt */ 549 r |= HD64461_PCC1CSCIER_P1RE; 550 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 551 } 552 hd64461_reg_write_1(cscier, r); 553 554 splx(s); 555 556 return (void *)ih_func; 557 } 558 559 STATIC void 560 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 561 { 562 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 563 int channel = ch->ch_channel; 564 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 565 int s = splhigh(); 566 uint8_t r; 567 568 /* disable card interrupt */ 569 r = hd64461_reg_read_1(cscier); 570 if (channel == CHANNEL_0) { 571 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 572 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 573 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 574 } else { 575 r &= ~HD64461_PCC1CSCIER_P1RE; 576 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 577 } 578 hd64461_reg_write_1(cscier, r); 579 580 ch->ch_ih_card_func = 0; 581 582 splx(s); 583 } 584 585 STATIC int 586 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 587 struct pcmcia_mem_handle *pcmhp) 588 { 589 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 590 591 pcmhp->memt = ch->ch_memt; 592 pcmhp->addr = ch->ch_membase_addr; 593 pcmhp->memh = ch->ch_memh; 594 pcmhp->size = size; 595 pcmhp->realsize = size; 596 597 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 598 599 return (0); 600 } 601 602 STATIC void 603 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 604 struct pcmcia_mem_handle *pcmhp) 605 { 606 /* nothing to do */ 607 } 608 609 STATIC int 610 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 611 bus_addr_t card_addr, 612 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 613 bus_size_t *offsetp, int *windowp) 614 { 615 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 616 struct hd64461pcmcia_window_cookie *cookie; 617 bus_addr_t ofs; 618 619 cookie = kmem_zalloc(sizeof(struct hd64461pcmcia_window_cookie), 620 KM_SLEEP); 621 KASSERT(cookie != NULL); 622 623 /* Address */ 624 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 625 cookie->wc_tag = ch->ch_memt; 626 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 627 size, &cookie->wc_handle) != 0) 628 goto bad; 629 630 *offsetp = card_addr; 631 cookie->wc_window = -1; 632 } else { 633 int window = card_addr / ch->ch_memsize; 634 KASSERT(window < MEMWIN_16M_MAX); 635 636 cookie->wc_tag = ch->ch_cmemt[window]; 637 ofs = card_addr - window * ch->ch_memsize; 638 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 639 &cookie->wc_handle) != 0) 640 goto bad; 641 642 /* XXX bogus. check window per common memory access. */ 643 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 644 *offsetp = ofs + 0x01000000; /* skip attribute area */ 645 cookie->wc_window = window; 646 } 647 cookie->wc_size = size; 648 *windowp = (int)cookie; 649 650 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 651 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 652 size); 653 654 return (0); 655 bad: 656 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 657 kmem_free(cookie, sizeof(*cookie)); 658 659 return (1); 660 } 661 662 STATIC void 663 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 664 { 665 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 666 667 if (cookie->wc_window != -1) 668 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 669 cookie->wc_size); 670 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 671 kmem_free(cookie, sizeof(*cookie)); 672 } 673 674 STATIC int 675 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 676 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 677 { 678 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 679 680 if (ch->ch_channel == CHANNEL_1) 681 return (1); 682 683 if (start) { 684 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 685 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 686 return (1); 687 } 688 DPRINTF("map %#lx+%#lx\n", start, size); 689 } else { 690 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 691 ch->ch_iobase + ch->ch_iosize - 1, 692 size, align, 0, 0, &pcihp->addr, 693 &pcihp->ioh)) { 694 DPRINTF("couldn't allocate %#lx\n", size); 695 return (1); 696 } 697 pcihp->flags = PCMCIA_IO_ALLOCATED; 698 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 699 } 700 701 pcihp->iot = ch->ch_iot; 702 pcihp->size = size; 703 704 return (0); 705 } 706 707 STATIC int 708 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 709 bus_addr_t offset, 710 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 711 { 712 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 713 #ifdef HD64461PCMCIA_DEBUG 714 static const char *width_names[] = { "auto", "io8", "io16" }; 715 #endif 716 if (ch->ch_channel == CHANNEL_1) 717 return (1); 718 719 hd64461_set_bus_width(CHANNEL_0, width); 720 721 /* fake. drivers init that to -1 and check if it was changed. */ 722 *windowp = 0; 723 724 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 725 width_names[width]); 726 727 return (0); 728 } 729 730 STATIC void 731 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 732 struct pcmcia_io_handle *pcihp) 733 { 734 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 735 736 if (ch->ch_channel == CHANNEL_1) 737 return; 738 739 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 740 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 741 else 742 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 743 744 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 745 } 746 747 STATIC void 748 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 749 { 750 751 /* nothing to do */ 752 } 753 754 STATIC void 755 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 756 { 757 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 758 int channel = ch->ch_channel; 759 bus_addr_t isr, gcr; 760 uint8_t r; 761 int i; 762 763 DPRINTF("enable channel %d\n", channel); 764 isr = HD64461_PCCISR(channel); 765 gcr = HD64461_PCCGCR(channel); 766 767 hd64461pcmcia_power_off(channel); 768 hd64461pcmcia_power_on(channel); 769 770 /* assert reset, set card type to memory */ 771 r = hd64461_reg_read_1(gcr); 772 r |= HD64461_PCCGCR_PCCR; 773 r &= ~HD64461_PCC0GCR_P0PCCT; 774 hd64461_reg_write_1(gcr, r); 775 776 /* 777 * hold RESET at least 10us. 778 */ 779 DELAY_MS(20); 780 781 /* clear the reset flag */ 782 r &= ~HD64461_PCCGCR_PCCR; 783 hd64461_reg_write_1(gcr, r); 784 DELAY_MS(2000); 785 786 /* wait for the chip to finish initializing */ 787 for (i = 0; i < 10000; i++) { 788 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 789 goto reset_ok; 790 DELAY_MS(500); 791 792 if ((i > 5000) && (i % 100 == 99)) 793 printf("."); 794 } 795 printf("reset failed.\n"); 796 hd64461pcmcia_power_off(channel); 797 return; 798 799 reset_ok: 800 /* set Continuous 16-MB Area Mode */ 801 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 802 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 803 804 /* 805 * set Common memory area. 806 */ 807 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 808 809 DPRINTF("OK.\n"); 810 } 811 812 STATIC void 813 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 814 { 815 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 816 int channel = ch->ch_channel; 817 bus_addr_t gcr; 818 uint8_t r; 819 820 DPRINTF("settype channel %d\n", channel); 821 gcr = HD64461_PCCGCR(channel); 822 823 /* set the card type */ 824 r = hd64461_reg_read_1(gcr); 825 if (channel == CHANNEL_0) { 826 if (type == PCMCIA_IFTYPE_IO) 827 r |= HD64461_PCC0GCR_P0PCCT; 828 else 829 r &= ~HD64461_PCC0GCR_P0PCCT; 830 } else { 831 /* reserved bit must be 0 */ 832 r &= ~HD64461_PCC1GCR_RESERVED; 833 } 834 hd64461_reg_write_1(gcr, r); 835 836 DPRINTF("OK.\n"); 837 } 838 839 STATIC void 840 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 841 { 842 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 843 int channel = ch->ch_channel; 844 845 /* dont' disable CSC interrupt */ 846 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 847 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 848 849 /* power down the socket */ 850 hd64461pcmcia_power_off(channel); 851 } 852 853 /* 854 * Card detect 855 */ 856 STATIC void 857 hd64461pcmcia_power_off(enum controller_channel channel) 858 { 859 uint8_t r; 860 uint16_t r16; 861 bus_addr_t scr, gcr; 862 863 gcr = HD64461_PCCGCR(channel); 864 scr = HD64461_PCCSCR(channel); 865 866 /* DRV (external buffer) high level */ 867 r = hd64461_reg_read_1(gcr); 868 r &= ~HD64461_PCCGCR_DRVE; 869 hd64461_reg_write_1(gcr, r); 870 871 /* stop power */ 872 r = hd64461_reg_read_1(scr); 873 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 874 hd64461_reg_write_1(scr, r); 875 r = hd64461_reg_read_1(gcr); 876 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 877 hd64461_reg_write_1(gcr, r); 878 /* 879 * wait 300ms until power fails (Tpf). Then, wait 100ms since 880 * we are changing Vcc (Toff). 881 */ 882 DELAY_MS(300 + 100); 883 884 /* stop clock */ 885 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 886 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 887 HD64461_SYSSTBCR_SPC1ST); 888 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 889 } 890 891 STATIC void 892 hd64461pcmcia_power_on(enum controller_channel channel) 893 { 894 uint8_t r; 895 uint16_t r16; 896 bus_addr_t gcr, isr; 897 898 isr = HD64461_PCCISR(channel); 899 gcr = HD64461_PCCGCR(channel); 900 (void)HD64461_PCCSCR(channel); 901 902 /* 903 * XXX to access attribute memory, this is required. 904 */ 905 if (channel == CHANNEL_0) { 906 /* GPIO Port A XXX Jonanada690 specific? */ 907 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 908 r16 &= ~0xf; 909 r16 |= 0x5; 910 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 911 } 912 913 if (channel == CHANNEL_1) { 914 /* GPIO Port C, Port D -> PCC1 pin 915 * I assume SYSCR[1:0] == 0 916 */ 917 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 918 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 919 } 920 921 /* supply clock */ 922 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 923 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 924 HD64461_SYSSTBCR_SPC1ST); 925 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 926 DELAY_MS(200); 927 928 /* detect voltage and supply VCC */ 929 r = hd64461_reg_read_1(isr); 930 931 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 932 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 933 DPRINTF("5V card\n"); 934 hd64461pcmcia_power(channel, V_5, 1); 935 break; 936 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 937 /* FALLTHROUGH */ 938 case 0: /* x.x / 3.3 / 5 V */ 939 DPRINTF("3.3V card\n"); 940 hd64461pcmcia_power(channel, V_3_3, 1); 941 break; 942 case HD64461_PCCISR_VS1: /* x.x V */ 943 /* FALLTHROUGH */ 944 DPRINTF("x.x V card\n"); 945 hd64461pcmcia_power(channel, V_X_X, 1); 946 return; 947 default: 948 printf("\nunknown Voltage. don't attach.\n"); 949 return; 950 } 951 952 /* 953 * wait 100ms until power raise (Tpr) and 20ms to become 954 * stable (Tsu(Vcc)). 955 * 956 * some machines require some more time to be settled 957 * (300ms is added here). 958 */ 959 DELAY_MS(100 + 20 + 300); 960 961 /* DRV (external buffer) low level */ 962 r = hd64461_reg_read_1(gcr); 963 r |= HD64461_PCCGCR_DRVE; 964 hd64461_reg_write_1(gcr, r); 965 966 /* clear interrupt */ 967 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 968 HD64461_PCC1CSCR_REG8, 0); 969 } 970 971 STATIC enum hd64461pcmcia_event_type 972 detect_card(enum controller_channel channel) 973 { 974 uint8_t r; 975 976 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 977 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 978 979 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 980 DPRINTF("remove\n"); 981 return EVENT_REMOVE; 982 } 983 if (r == 0) { 984 DPRINTF("insert\n"); 985 return EVENT_INSERT; 986 } 987 DPRINTF("transition\n"); 988 989 return EVENT_NONE; 990 } 991 992 /* 993 * Memory window access ops. 994 */ 995 STATIC void 996 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 997 enum memory_window_mode mode) 998 { 999 bus_addr_t a = HD64461_PCCGCR(channel); 1000 uint8_t r = hd64461_reg_read_1(a); 1001 1002 r &= ~HD64461_PCCGCR_MMOD; 1003 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 1004 HD64461_PCCGCR_MMOD_32M; 1005 hd64461_reg_write_1(a, r); 1006 } 1007 1008 STATIC void 1009 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1010 enum memory_window_16 window) 1011 { 1012 bus_addr_t a = HD64461_PCCGCR(channel); 1013 uint8_t r; 1014 1015 r = hd64461_reg_read_1(a); 1016 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1017 1018 switch (window) { 1019 case MEMWIN_16M_COMMON_0: 1020 break; 1021 case MEMWIN_16M_COMMON_1: 1022 r |= HD64461_PCCGCR_PA24; 1023 break; 1024 case MEMWIN_16M_COMMON_2: 1025 r |= HD64461_PCCGCR_PA25; 1026 break; 1027 case MEMWIN_16M_COMMON_3: 1028 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1029 break; 1030 } 1031 1032 hd64461_reg_write_1(a, r); 1033 } 1034 1035 #if unused 1036 STATIC void 1037 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1038 { 1039 bus_addr_t a = HD64461_PCCGCR(channel); 1040 uint8_t r; 1041 1042 r = hd64461_reg_read_1(a); 1043 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1044 1045 switch (window) { 1046 case MEMWIN_32M_ATTR: 1047 break; 1048 case MEMWIN_32M_COMMON_0: 1049 r |= HD64461_PCCGCR_PREG; 1050 break; 1051 case MEMWIN_32M_COMMON_1: 1052 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1053 break; 1054 } 1055 1056 hd64461_reg_write_1(a, r); 1057 } 1058 #endif 1059 1060 STATIC void 1061 hd64461_set_bus_width(enum controller_channel channel, int width) 1062 { 1063 unsigned int area, buswidth; 1064 uint16_t bcr2; 1065 1066 if (channel == CHANNEL_0) 1067 area = BCR2_AREA6_SHIFT; 1068 else 1069 area = BCR2_AREA5_SHIFT; 1070 1071 if (width == PCMCIA_WIDTH_IO8) 1072 buswidth = BCR2_AREA_WIDTH_8; 1073 else 1074 buswidth = BCR2_AREA_WIDTH_16; 1075 1076 bcr2 = _reg_read_2(SH3_BCR2); 1077 1078 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1079 bcr2 |= buswidth << area; 1080 1081 _reg_write_2(SH3_BCR2, bcr2); 1082 } 1083 1084 STATIC void 1085 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1086 { 1087 struct hpcsh_bus_space *hbs = (void *)t; 1088 1089 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1090 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1091 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1092 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1093 } 1094 1095 #ifdef HD64461PCMCIA_DEBUG 1096 STATIC void 1097 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1098 { 1099 uint8_t r8; 1100 1101 dbg_banner_function(); 1102 /* 1103 * PCC0 1104 */ 1105 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1106 printf("PCC0 Interface Status Register\n"); 1107 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1108 1109 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1110 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1111 _(P0BVD2);_(P0BVD1); 1112 #undef _ 1113 printf("\n"); 1114 1115 printf("PCC0 General Control Register\n"); 1116 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1117 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1118 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1119 _(P0PA25);_(P0PA24);_(P0REG); 1120 #undef _ 1121 printf("\n"); 1122 1123 printf("PCC0 Card Status Change Register\n"); 1124 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1125 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1126 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1127 #undef _ 1128 printf("\n"); 1129 1130 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1131 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1132 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1133 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1134 #undef _ 1135 printf("\ninterrupt type: "); 1136 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1137 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1138 printf("none\n"); 1139 break; 1140 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1141 printf("level\n"); 1142 break; 1143 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1144 printf("falling edge\n"); 1145 break; 1146 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1147 printf("rising edge\n"); 1148 break; 1149 } 1150 1151 printf("PCC0 Software Control Register\n"); 1152 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1153 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1154 _(P0VCC1);_(P0SWP); 1155 #undef _ 1156 printf("\n"); 1157 1158 /* 1159 * PCC1 1160 */ 1161 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1162 printf("PCC1 Interface Status Register\n"); 1163 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1164 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1165 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1166 _(P1BVD2);_(P1BVD1); 1167 #undef _ 1168 printf("\n"); 1169 1170 printf("PCC1 General Contorol Register\n"); 1171 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1172 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1173 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1174 #undef _ 1175 printf("\n"); 1176 1177 printf("PCC1 Card Status Change Register\n"); 1178 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1179 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1180 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1181 #undef _ 1182 printf("\n"); 1183 1184 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1185 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1186 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1187 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1188 #undef _ 1189 printf("\n"); 1190 1191 printf("PCC1 Software Control Register\n"); 1192 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1193 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1194 _(P1VCC1);_(P1SWP); 1195 #undef _ 1196 printf("\n"); 1197 1198 /* 1199 * General Control 1200 */ 1201 printf("[General Control]\n"); 1202 printf("PCC0 Output pins Control Register\n"); 1203 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1204 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1205 _(P0DEPLUP);_(P0AEPLUP); 1206 #undef _ 1207 printf("\n"); 1208 1209 printf("PCC1 Output pins Control Register\n"); 1210 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1211 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1212 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1213 #undef _ 1214 printf("\n"); 1215 1216 printf("PC Card General Control Register\n"); 1217 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1218 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1219 _(PSSDIR);_(PSSRDWR); 1220 #undef _ 1221 printf("\n"); 1222 1223 dbg_banner_line(); 1224 } 1225 #endif /* HD64461PCMCIA_DEBUG */ 1226
Indexes created Thu Oct 02 01:09:59 GMT 2025