hd64461pcmcia.c revision 1.54
1 /* $NetBSD: hd64461pcmcia.c,v 1.54 2021/08/07 16:18:54 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64461pcmcia.c,v 1.54 2021/08/07 16:18:54 thorpej Exp $"); 34 35 #include "opt_hd64461pcmcia.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/kmem.h> 41 #include <sys/kthread.h> 42 #include <sys/boot_flag.h> 43 #include <sys/bus.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 53 #include <hpcsh/dev/hd64461/hd64461reg.h> 54 #include <hpcsh/dev/hd64461/hd64461var.h> 55 #include <hpcsh/dev/hd64461/hd64461intcreg.h> 56 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciavar.h> 58 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 59 60 #include <hpcsh/bus_util.h> /* for _BUS_SPACE_WRITE(), et cetera */ 61 62 #include "locators.h" 63 64 #ifdef HD64461PCMCIA_DEBUG 65 #define DPRINTF_ENABLE 66 #define DPRINTF_DEBUG hd64461pcmcia_debug 67 #endif 68 #include <machine/debug.h> 69 70 enum controller_channel { 71 CHANNEL_0 = 0, 72 CHANNEL_1 = 1, 73 CHANNEL_MAX = 2 74 }; 75 76 enum memory_window_mode { 77 MEMWIN_16M_MODE, 78 MEMWIN_32M_MODE 79 }; 80 81 enum memory_window_16 { 82 MEMWIN_16M_COMMON_0, 83 MEMWIN_16M_COMMON_1, 84 MEMWIN_16M_COMMON_2, 85 MEMWIN_16M_COMMON_3, 86 }; 87 #define MEMWIN_16M_MAX 4 88 89 enum memory_window_32 { 90 MEMWIN_32M_ATTR, 91 MEMWIN_32M_COMMON_0, 92 MEMWIN_32M_COMMON_1, 93 }; 94 #define MEMWIN_32M_MAX 3 95 96 enum hd64461pcmcia_event_type { 97 EVENT_NONE, 98 EVENT_INSERT, 99 EVENT_REMOVE, 100 }; 101 #define EVENT_QUEUE_MAX 5 102 103 struct hd64461pcmcia_softc; /* forward declaration */ 104 105 struct hd64461pcmcia_window_cookie { 106 bus_space_tag_t wc_tag; 107 bus_space_handle_t wc_handle; 108 int wc_size; 109 int wc_window; 110 }; 111 112 struct hd64461pcmcia_channel { 113 struct hd64461pcmcia_softc *ch_parent; 114 device_t ch_pcmcia; 115 enum controller_channel ch_channel; 116 117 /* memory space */ 118 enum memory_window_mode ch_memory_window_mode; 119 bus_space_tag_t ch_memt; 120 bus_space_handle_t ch_memh; 121 bus_addr_t ch_membase_addr; 122 bus_size_t ch_memsize; 123 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 124 125 /* I/O space */ 126 bus_space_tag_t ch_iot; 127 bus_addr_t ch_iobase; 128 bus_size_t ch_iosize; 129 130 /* card interrupt */ 131 int (*ch_ih_card_func)(void *); 132 void *ch_ih_card_arg; 133 int ch_attached; 134 }; 135 136 struct hd64461pcmcia_event { 137 int __queued; 138 enum hd64461pcmcia_event_type pe_type; 139 struct hd64461pcmcia_channel *pe_ch; 140 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 141 }; 142 143 struct hd64461pcmcia_softc { 144 device_t sc_dev; 145 146 enum hd64461_module_id sc_module_id; 147 int sc_shutdown; 148 149 /* CSC event */ 150 lwp_t *sc_event_thread; 151 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 152 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 153 154 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 155 }; 156 157 STATIC int hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 158 struct pcmcia_mem_handle *); 159 STATIC void hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 160 struct pcmcia_mem_handle *); 161 STATIC int hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 162 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 163 STATIC void hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 164 STATIC int hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 165 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 166 STATIC void hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t, 167 struct pcmcia_io_handle *); 168 STATIC int hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 169 bus_size_t, struct pcmcia_io_handle *, int *); 170 STATIC void hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 171 STATIC void hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 172 STATIC void hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 173 STATIC void hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 174 STATIC void *hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 175 struct pcmcia_function *, int, int (*)(void *), void *); 176 STATIC void hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 177 void *); 178 179 STATIC struct pcmcia_chip_functions hd64461pcmcia_functions = { 180 hd64461pcmcia_chip_mem_alloc, 181 hd64461pcmcia_chip_mem_free, 182 hd64461pcmcia_chip_mem_map, 183 hd64461pcmcia_chip_mem_unmap, 184 hd64461pcmcia_chip_io_alloc, 185 hd64461pcmcia_chip_io_free, 186 hd64461pcmcia_chip_io_map, 187 hd64461pcmcia_chip_io_unmap, 188 hd64461pcmcia_chip_intr_establish, 189 hd64461pcmcia_chip_intr_disestablish, 190 hd64461pcmcia_chip_socket_enable, 191 hd64461pcmcia_chip_socket_disable, 192 hd64461pcmcia_chip_socket_settype, 193 }; 194 195 STATIC int hd64461pcmcia_match(device_t, cfdata_t, void *); 196 STATIC void hd64461pcmcia_attach(device_t, device_t, void *); 197 STATIC int hd64461pcmcia_print(void *, const char *); 198 STATIC int hd64461pcmcia_submatch(device_t, cfdata_t, const int *, void *); 199 200 CFATTACH_DECL_NEW(hd64461pcmcia, sizeof(struct hd64461pcmcia_softc), 201 hd64461pcmcia_match, hd64461pcmcia_attach, NULL, NULL); 202 203 STATIC void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 204 enum controller_channel); 205 /* hot plug */ 206 STATIC void hd64461pcmcia_event_thread(void *); 207 STATIC void queue_event(struct hd64461pcmcia_channel *, 208 enum hd64461pcmcia_event_type); 209 /* interrupt handler */ 210 STATIC int hd64461pcmcia_channel0_intr(void *); 211 STATIC int hd64461pcmcia_channel1_intr(void *); 212 /* card status */ 213 STATIC enum hd64461pcmcia_event_type detect_card(enum controller_channel); 214 STATIC void hd64461pcmcia_power_off(enum controller_channel); 215 STATIC void hd64461pcmcia_power_on(enum controller_channel); 216 /* memory window access ops */ 217 STATIC void hd64461pcmcia_memory_window_mode(enum controller_channel, 218 enum memory_window_mode)__attribute__((__unused__)); 219 STATIC void hd64461pcmcia_memory_window_16(enum controller_channel, 220 enum memory_window_16); 221 /* bus width */ 222 STATIC void hd64461_set_bus_width(enum controller_channel, int); 223 #ifdef HD64461PCMCIA_DEBUG 224 STATIC void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 225 #endif 226 /* fix SH3 Area[56] bug */ 227 STATIC void fixup_sh3_pcmcia_area(bus_space_tag_t); 228 #define _BUS_SPACE_ACCESS_HOOK() \ 229 do { \ 230 uint8_t dummy __attribute__((__unused__)) = \ 231 *(volatile uint8_t *)0xba000000; \ 232 } while (/*CONSTCOND*/0) 233 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 234 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 235 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 236 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 237 #undef _BUS_SPACE_ACCESS_HOOK 238 239 #define DELAY_MS(x) delay((x) * 1000) 240 241 STATIC int 242 hd64461pcmcia_match(device_t parent, cfdata_t cf, void *aux) 243 { 244 struct hd64461_attach_args *ha = aux; 245 246 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 247 } 248 249 STATIC void 250 hd64461pcmcia_attach(device_t parent, device_t self, void *aux) 251 { 252 struct hd64461_attach_args *ha = aux; 253 struct hd64461pcmcia_softc *sc; 254 int error __diagused; 255 256 sc = device_private(self); 257 sc->sc_dev = self; 258 259 sc->sc_module_id = ha->ha_module_id; 260 261 aprint_naive("\n"); 262 aprint_normal("\n"); 263 264 #ifdef HD64461PCMCIA_DEBUG 265 hd64461pcmcia_info(sc); 266 #endif 267 /* Channel 0/1 common CSC event queue */ 268 SIMPLEQ_INIT (&sc->sc_event_head); 269 270 error = kthread_create(PRI_NONE, 0, NULL, 271 hd64461pcmcia_event_thread, sc, 272 &sc->sc_event_thread, 273 "%s", device_xname(self)); 274 KASSERT(error == 0); 275 276 config_pending_incr(self); 277 278 /* XXX: TODO */ 279 if (!pmf_device_register(self, NULL, NULL)) 280 aprint_error_dev(self, "unable to establish power handler\n"); 281 } 282 283 STATIC void 284 hd64461pcmcia_event_thread(void *arg) 285 { 286 struct hd64461pcmcia_softc *sc = arg; 287 struct hd64461pcmcia_event *pe; 288 int s; 289 290 #if !defined(HD64461PCMCIA_REORDER_ATTACH) 291 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 292 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 293 #else 294 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 295 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 296 #endif 297 config_pending_decr(sc->sc_dev); 298 299 while (!sc->sc_shutdown) { 300 tsleep(sc, PWAIT, "CSC wait", 0); 301 s = splhigh(); 302 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 303 splx(s); 304 switch (pe->pe_type) { 305 default: 306 printf("%s: unknown event.\n", __func__); 307 break; 308 case EVENT_INSERT: 309 DPRINTF("insert event.\n"); 310 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 311 break; 312 case EVENT_REMOVE: 313 DPRINTF("remove event.\n"); 314 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 315 DETACH_FORCE); 316 break; 317 } 318 s = splhigh(); 319 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 320 pe->__queued = 0; 321 } 322 splx(s); 323 } 324 325 sc->sc_event_thread = NULL; 326 kthread_exit(0); 327 /* NOTREACHED */ 328 } 329 330 STATIC int 331 hd64461pcmcia_print(void *arg, const char *pnp) 332 { 333 334 if (pnp) 335 aprint_normal("pcmcia at %s", pnp); 336 337 return (UNCONF); 338 } 339 340 STATIC int 341 hd64461pcmcia_submatch(device_t parent, cfdata_t cf, 342 const int *ldesc, void *aux) 343 { 344 struct pcmciabus_attach_args *paa = aux; 345 struct hd64461pcmcia_channel *ch = 346 (struct hd64461pcmcia_channel *)paa->pch; 347 348 if (ch->ch_channel == CHANNEL_0) { 349 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 350 PCMCIABUSCF_CONTROLLER_DEFAULT && 351 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 352 return 0; 353 } else { 354 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 355 PCMCIABUSCF_CONTROLLER_DEFAULT && 356 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 357 return 0; 358 } 359 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 360 361 return (config_match(parent, cf, aux)); 362 } 363 364 STATIC void 365 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 366 enum controller_channel channel) 367 { 368 device_t parent = sc->sc_dev; 369 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 370 struct pcmciabus_attach_args paa; 371 bus_addr_t membase; 372 int i; 373 374 ch->ch_parent = sc; 375 ch->ch_channel = channel; 376 377 /* 378 * Continuous 16-MB Area Mode 379 */ 380 /* Attibute/Common memory extent */ 381 membase = (channel == CHANNEL_0) 382 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 383 384 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 385 membase, 0x01000000); /* 16MB */ 386 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 387 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 388 &ch->ch_memh); 389 fixup_sh3_pcmcia_area(ch->ch_memt); 390 391 /* Common memory space extent */ 392 ch->ch_memsize = 0x01000000; 393 for (i = 0; i < MEMWIN_16M_MAX; i++) { 394 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 395 membase + 0x01000000, 396 ch->ch_memsize); 397 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 398 } 399 400 /* I/O port extent and interrupt staff */ 401 hd64461pcmcia_chip_socket_disable(ch); /* enable CSC interrupt only */ 402 403 if (channel == CHANNEL_0) { 404 ch->ch_iobase = 0; 405 ch->ch_iosize = HD64461_PCC0_IOSIZE; 406 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 407 HD64461_PCC0_IOBASE, 408 ch->ch_iosize); 409 fixup_sh3_pcmcia_area(ch->ch_iot); 410 411 hd6446x_intr_establish(HD64461_INTC_PCC0, IST_LEVEL, IPL_TTY, 412 hd64461pcmcia_channel0_intr, ch); 413 } else { 414 hd64461_set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 415 hd6446x_intr_establish(HD64461_INTC_PCC1, IST_EDGE, IPL_TTY, 416 hd64461pcmcia_channel1_intr, ch); 417 } 418 419 paa.paa_busname = "pcmcia"; 420 paa.pch = (pcmcia_chipset_handle_t)ch; 421 422 ch->ch_pcmcia = config_found(parent, &paa, hd64461pcmcia_print, 423 CFARGS(.submatch = hd64461pcmcia_submatch)); 424 425 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 426 ch->ch_attached = 1; 427 pcmcia_card_attach(ch->ch_pcmcia); 428 } 429 } 430 431 STATIC int 432 hd64461pcmcia_channel0_intr(void *arg) 433 { 434 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 435 uint8_t r; 436 int ret = 0; 437 438 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 439 /* clear interrtupt (edge source only) */ 440 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 441 442 if (r & HD64461_PCC0CSCR_P0IREQ) { 443 if (ch->ch_ih_card_func) { 444 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 445 } else 446 DPRINTF("spurious IREQ interrupt.\n"); 447 } 448 449 if (r & HD64461_PCC0CSCR_P0CDC) 450 queue_event(ch, detect_card(ch->ch_channel)); 451 452 return ret; 453 } 454 455 STATIC int 456 hd64461pcmcia_channel1_intr(void *arg) 457 { 458 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 459 uint8_t r; 460 int ret = 0; 461 462 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 463 /* clear interrtupt */ 464 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 465 466 if (r & HD64461_PCC1CSCR_P1RC) { 467 if (ch->ch_ih_card_func) 468 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 469 else 470 DPRINTF("spurious READY interrupt.\n"); 471 } 472 473 if (r & HD64461_PCC1CSCR_P1CDC) 474 queue_event(ch, detect_card(ch->ch_channel)); 475 476 return ret; 477 } 478 479 STATIC void 480 queue_event(struct hd64461pcmcia_channel *ch, 481 enum hd64461pcmcia_event_type type) 482 { 483 struct hd64461pcmcia_event *pe, *pool; 484 struct hd64461pcmcia_softc *sc = ch->ch_parent; 485 int i; 486 int s = splhigh(); 487 488 if (type == EVENT_NONE) 489 goto out; 490 491 pe = 0; 492 pool = sc->sc_event_pool; 493 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 494 if (!pool[i].__queued) { 495 pe = &pool[i]; 496 break; 497 } 498 } 499 500 if (pe == 0) { 501 printf("%s: event FIFO overflow (max %d).\n", __func__, 502 EVENT_QUEUE_MAX); 503 goto out; 504 } 505 506 if ((ch->ch_attached && (type == EVENT_INSERT)) || 507 (!ch->ch_attached && (type == EVENT_REMOVE))) { 508 DPRINTF("spurious CSC interrupt.\n"); 509 goto out; 510 } 511 512 ch->ch_attached = (type == EVENT_INSERT); 513 pe->__queued = 1; 514 pe->pe_type = type; 515 pe->pe_ch = ch; 516 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 517 wakeup(sc); 518 out: 519 splx(s); 520 } 521 522 /* 523 * interface for pcmcia driver. 524 */ 525 STATIC void * 526 hd64461pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 527 struct pcmcia_function *pf, 528 int ipl, int (*ih_func)(void *), void *ih_arg) 529 { 530 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 531 int channel = ch->ch_channel; 532 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 533 int s = splhigh(); 534 uint8_t r; 535 536 ch->ch_ih_card_func = ih_func; 537 ch->ch_ih_card_arg = ih_arg; 538 539 /* enable card interrupt */ 540 r = hd64461_reg_read_1(cscier); 541 if (channel == CHANNEL_0) { 542 /* set level mode */ 543 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 544 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 545 hd6446x_intr_priority(HD64461_INTC_PCC0, ipl); 546 } else { 547 /* READY-pin LOW to HIGH changes generates interrupt */ 548 r |= HD64461_PCC1CSCIER_P1RE; 549 hd6446x_intr_priority(HD64461_INTC_PCC1, ipl); 550 } 551 hd64461_reg_write_1(cscier, r); 552 553 splx(s); 554 555 return (void *)ih_func; 556 } 557 558 STATIC void 559 hd64461pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 560 { 561 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 562 int channel = ch->ch_channel; 563 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 564 int s = splhigh(); 565 uint8_t r; 566 567 /* disable card interrupt */ 568 r = hd64461_reg_read_1(cscier); 569 if (channel == CHANNEL_0) { 570 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 571 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 572 hd6446x_intr_priority(HD64461_INTC_PCC0, IPL_TTY); 573 } else { 574 r &= ~HD64461_PCC1CSCIER_P1RE; 575 hd6446x_intr_priority(HD64461_INTC_PCC1, IPL_TTY); 576 } 577 hd64461_reg_write_1(cscier, r); 578 579 ch->ch_ih_card_func = 0; 580 581 splx(s); 582 } 583 584 STATIC int 585 hd64461pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 586 struct pcmcia_mem_handle *pcmhp) 587 { 588 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 589 590 pcmhp->memt = ch->ch_memt; 591 pcmhp->addr = ch->ch_membase_addr; 592 pcmhp->memh = ch->ch_memh; 593 pcmhp->size = size; 594 pcmhp->realsize = size; 595 596 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 597 598 return (0); 599 } 600 601 STATIC void 602 hd64461pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 603 struct pcmcia_mem_handle *pcmhp) 604 { 605 /* nothing to do */ 606 } 607 608 STATIC int 609 hd64461pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 610 bus_addr_t card_addr, 611 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 612 bus_size_t *offsetp, int *windowp) 613 { 614 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 615 struct hd64461pcmcia_window_cookie *cookie; 616 bus_addr_t ofs; 617 618 cookie = kmem_zalloc(sizeof(struct hd64461pcmcia_window_cookie), 619 KM_SLEEP); 620 KASSERT(cookie != NULL); 621 622 /* Address */ 623 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 624 cookie->wc_tag = ch->ch_memt; 625 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 626 size, &cookie->wc_handle) != 0) 627 goto bad; 628 629 *offsetp = card_addr; 630 cookie->wc_window = -1; 631 } else { 632 int window = card_addr / ch->ch_memsize; 633 KASSERT(window < MEMWIN_16M_MAX); 634 635 cookie->wc_tag = ch->ch_cmemt[window]; 636 ofs = card_addr - window * ch->ch_memsize; 637 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 638 &cookie->wc_handle) != 0) 639 goto bad; 640 641 /* XXX bogus. check window per common memory access. */ 642 hd64461pcmcia_memory_window_16(ch->ch_channel, window); 643 *offsetp = ofs + 0x01000000; /* skip attribute area */ 644 cookie->wc_window = window; 645 } 646 cookie->wc_size = size; 647 *windowp = (int)cookie; 648 649 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 650 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 651 size); 652 653 return (0); 654 bad: 655 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 656 kmem_free(cookie, sizeof(*cookie)); 657 658 return (1); 659 } 660 661 STATIC void 662 hd64461pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 663 { 664 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 665 666 if (cookie->wc_window != -1) 667 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 668 cookie->wc_size); 669 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 670 kmem_free(cookie, sizeof(*cookie)); 671 } 672 673 STATIC int 674 hd64461pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 675 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 676 { 677 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 678 679 if (ch->ch_channel == CHANNEL_1) 680 return (1); 681 682 if (start) { 683 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 684 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 685 return (1); 686 } 687 DPRINTF("map %#lx+%#lx\n", start, size); 688 } else { 689 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 690 ch->ch_iobase + ch->ch_iosize - 1, 691 size, align, 0, 0, &pcihp->addr, 692 &pcihp->ioh)) { 693 DPRINTF("couldn't allocate %#lx\n", size); 694 return (1); 695 } 696 pcihp->flags = PCMCIA_IO_ALLOCATED; 697 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 698 } 699 700 pcihp->iot = ch->ch_iot; 701 pcihp->size = size; 702 703 return (0); 704 } 705 706 STATIC int 707 hd64461pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 708 bus_addr_t offset, 709 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 710 { 711 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 712 #ifdef HD64461PCMCIA_DEBUG 713 static const char *width_names[] = { "auto", "io8", "io16" }; 714 #endif 715 if (ch->ch_channel == CHANNEL_1) 716 return (1); 717 718 hd64461_set_bus_width(CHANNEL_0, width); 719 720 /* fake. drivers init that to -1 and check if it was changed. */ 721 *windowp = 0; 722 723 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 724 width_names[width]); 725 726 return (0); 727 } 728 729 STATIC void 730 hd64461pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 731 struct pcmcia_io_handle *pcihp) 732 { 733 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 734 735 if (ch->ch_channel == CHANNEL_1) 736 return; 737 738 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 739 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 740 else 741 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 742 743 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 744 } 745 746 STATIC void 747 hd64461pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 748 { 749 750 /* nothing to do */ 751 } 752 753 STATIC void 754 hd64461pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 755 { 756 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 757 int channel = ch->ch_channel; 758 bus_addr_t isr, gcr; 759 uint8_t r; 760 int i; 761 762 DPRINTF("enable channel %d\n", channel); 763 isr = HD64461_PCCISR(channel); 764 gcr = HD64461_PCCGCR(channel); 765 766 hd64461pcmcia_power_off(channel); 767 hd64461pcmcia_power_on(channel); 768 769 /* assert reset, set card type to memory */ 770 r = hd64461_reg_read_1(gcr); 771 r |= HD64461_PCCGCR_PCCR; 772 r &= ~HD64461_PCC0GCR_P0PCCT; 773 hd64461_reg_write_1(gcr, r); 774 775 /* 776 * hold RESET at least 10us. 777 */ 778 DELAY_MS(20); 779 780 /* clear the reset flag */ 781 r &= ~HD64461_PCCGCR_PCCR; 782 hd64461_reg_write_1(gcr, r); 783 DELAY_MS(2000); 784 785 /* wait for the chip to finish initializing */ 786 for (i = 0; i < 10000; i++) { 787 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 788 goto reset_ok; 789 DELAY_MS(500); 790 791 if ((i > 5000) && (i % 100 == 99)) 792 printf("."); 793 } 794 printf("reset failed.\n"); 795 hd64461pcmcia_power_off(channel); 796 return; 797 798 reset_ok: 799 /* set Continuous 16-MB Area Mode */ 800 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 801 hd64461pcmcia_memory_window_mode(channel, ch->ch_memory_window_mode); 802 803 /* 804 * set Common memory area. 805 */ 806 hd64461pcmcia_memory_window_16(channel, MEMWIN_16M_COMMON_0); 807 808 DPRINTF("OK.\n"); 809 } 810 811 STATIC void 812 hd64461pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 813 { 814 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 815 int channel = ch->ch_channel; 816 bus_addr_t gcr; 817 uint8_t r; 818 819 DPRINTF("settype channel %d\n", channel); 820 gcr = HD64461_PCCGCR(channel); 821 822 /* set the card type */ 823 r = hd64461_reg_read_1(gcr); 824 if (channel == CHANNEL_0) { 825 if (type == PCMCIA_IFTYPE_IO) 826 r |= HD64461_PCC0GCR_P0PCCT; 827 else 828 r &= ~HD64461_PCC0GCR_P0PCCT; 829 } else { 830 /* reserved bit must be 0 */ 831 r &= ~HD64461_PCC1GCR_RESERVED; 832 } 833 hd64461_reg_write_1(gcr, r); 834 835 DPRINTF("OK.\n"); 836 } 837 838 STATIC void 839 hd64461pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 840 { 841 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 842 int channel = ch->ch_channel; 843 844 /* dont' disable CSC interrupt */ 845 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 846 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 847 848 /* power down the socket */ 849 hd64461pcmcia_power_off(channel); 850 } 851 852 /* 853 * Card detect 854 */ 855 STATIC void 856 hd64461pcmcia_power_off(enum controller_channel channel) 857 { 858 uint8_t r; 859 uint16_t r16; 860 bus_addr_t scr, gcr; 861 862 gcr = HD64461_PCCGCR(channel); 863 scr = HD64461_PCCSCR(channel); 864 865 /* DRV (external buffer) high level */ 866 r = hd64461_reg_read_1(gcr); 867 r &= ~HD64461_PCCGCR_DRVE; 868 hd64461_reg_write_1(gcr, r); 869 870 /* stop power */ 871 r = hd64461_reg_read_1(scr); 872 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 873 hd64461_reg_write_1(scr, r); 874 r = hd64461_reg_read_1(gcr); 875 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 876 hd64461_reg_write_1(gcr, r); 877 /* 878 * wait 300ms until power fails (Tpf). Then, wait 100ms since 879 * we are changing Vcc (Toff). 880 */ 881 DELAY_MS(300 + 100); 882 883 /* stop clock */ 884 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 885 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 886 HD64461_SYSSTBCR_SPC1ST); 887 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 888 } 889 890 STATIC void 891 hd64461pcmcia_power_on(enum controller_channel channel) 892 { 893 uint8_t r; 894 uint16_t r16; 895 bus_addr_t gcr, isr; 896 897 isr = HD64461_PCCISR(channel); 898 gcr = HD64461_PCCGCR(channel); 899 (void)HD64461_PCCSCR(channel); 900 901 /* 902 * XXX to access attribute memory, this is required. 903 */ 904 if (channel == CHANNEL_0) { 905 /* GPIO Port A XXX Jonanada690 specific? */ 906 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 907 r16 &= ~0xf; 908 r16 |= 0x5; 909 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 910 } 911 912 if (channel == CHANNEL_1) { 913 /* GPIO Port C, Port D -> PCC1 pin 914 * I assume SYSCR[1:0] == 0 915 */ 916 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 917 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 918 } 919 920 /* supply clock */ 921 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 922 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 923 HD64461_SYSSTBCR_SPC1ST); 924 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 925 DELAY_MS(200); 926 927 /* detect voltage and supply VCC */ 928 r = hd64461_reg_read_1(isr); 929 930 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 931 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 932 DPRINTF("5V card\n"); 933 hd64461pcmcia_power(channel, V_5, 1); 934 break; 935 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 936 /* FALLTHROUGH */ 937 case 0: /* x.x / 3.3 / 5 V */ 938 DPRINTF("3.3V card\n"); 939 hd64461pcmcia_power(channel, V_3_3, 1); 940 break; 941 case HD64461_PCCISR_VS1: /* x.x V */ 942 /* FALLTHROUGH */ 943 DPRINTF("x.x V card\n"); 944 hd64461pcmcia_power(channel, V_X_X, 1); 945 return; 946 default: 947 printf("\nunknown Voltage. don't attach.\n"); 948 return; 949 } 950 951 /* 952 * wait 100ms until power raise (Tpr) and 20ms to become 953 * stable (Tsu(Vcc)). 954 * 955 * some machines require some more time to be settled 956 * (300ms is added here). 957 */ 958 DELAY_MS(100 + 20 + 300); 959 960 /* DRV (external buffer) low level */ 961 r = hd64461_reg_read_1(gcr); 962 r |= HD64461_PCCGCR_DRVE; 963 hd64461_reg_write_1(gcr, r); 964 965 /* clear interrupt */ 966 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 967 HD64461_PCC1CSCR_REG8, 0); 968 } 969 970 STATIC enum hd64461pcmcia_event_type 971 detect_card(enum controller_channel channel) 972 { 973 uint8_t r; 974 975 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 976 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 977 978 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 979 DPRINTF("remove\n"); 980 return EVENT_REMOVE; 981 } 982 if (r == 0) { 983 DPRINTF("insert\n"); 984 return EVENT_INSERT; 985 } 986 DPRINTF("transition\n"); 987 988 return EVENT_NONE; 989 } 990 991 /* 992 * Memory window access ops. 993 */ 994 STATIC void 995 hd64461pcmcia_memory_window_mode(enum controller_channel channel, 996 enum memory_window_mode mode) 997 { 998 bus_addr_t a = HD64461_PCCGCR(channel); 999 uint8_t r = hd64461_reg_read_1(a); 1000 1001 r &= ~HD64461_PCCGCR_MMOD; 1002 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 1003 HD64461_PCCGCR_MMOD_32M; 1004 hd64461_reg_write_1(a, r); 1005 } 1006 1007 STATIC void 1008 hd64461pcmcia_memory_window_16(enum controller_channel channel, 1009 enum memory_window_16 window) 1010 { 1011 bus_addr_t a = HD64461_PCCGCR(channel); 1012 uint8_t r; 1013 1014 r = hd64461_reg_read_1(a); 1015 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1016 1017 switch (window) { 1018 case MEMWIN_16M_COMMON_0: 1019 break; 1020 case MEMWIN_16M_COMMON_1: 1021 r |= HD64461_PCCGCR_PA24; 1022 break; 1023 case MEMWIN_16M_COMMON_2: 1024 r |= HD64461_PCCGCR_PA25; 1025 break; 1026 case MEMWIN_16M_COMMON_3: 1027 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1028 break; 1029 } 1030 1031 hd64461_reg_write_1(a, r); 1032 } 1033 1034 #if unused 1035 STATIC void 1036 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1037 { 1038 bus_addr_t a = HD64461_PCCGCR(channel); 1039 uint8_t r; 1040 1041 r = hd64461_reg_read_1(a); 1042 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1043 1044 switch (window) { 1045 case MEMWIN_32M_ATTR: 1046 break; 1047 case MEMWIN_32M_COMMON_0: 1048 r |= HD64461_PCCGCR_PREG; 1049 break; 1050 case MEMWIN_32M_COMMON_1: 1051 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1052 break; 1053 } 1054 1055 hd64461_reg_write_1(a, r); 1056 } 1057 #endif 1058 1059 STATIC void 1060 hd64461_set_bus_width(enum controller_channel channel, int width) 1061 { 1062 unsigned int area, buswidth; 1063 uint16_t bcr2; 1064 1065 if (channel == CHANNEL_0) 1066 area = BCR2_AREA6_SHIFT; 1067 else 1068 area = BCR2_AREA5_SHIFT; 1069 1070 if (width == PCMCIA_WIDTH_IO8) 1071 buswidth = BCR2_AREA_WIDTH_8; 1072 else 1073 buswidth = BCR2_AREA_WIDTH_16; 1074 1075 bcr2 = _reg_read_2(SH3_BCR2); 1076 1077 bcr2 &= ~(BCR2_AREA_WIDTH_MASK << area); 1078 bcr2 |= buswidth << area; 1079 1080 _reg_write_2(SH3_BCR2, bcr2); 1081 } 1082 1083 STATIC void 1084 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1085 { 1086 struct hpcsh_bus_space *hbs = (void *)t; 1087 1088 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1089 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1090 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1091 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1092 } 1093 1094 #ifdef HD64461PCMCIA_DEBUG 1095 STATIC void 1096 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1097 { 1098 uint8_t r8; 1099 1100 dbg_banner_function(); 1101 /* 1102 * PCC0 1103 */ 1104 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1105 printf("PCC0 Interface Status Register\n"); 1106 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1107 1108 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0ISR_##m, #m) 1109 _(P0READY);_(P0MWP);_(P0VS2);_(P0VS1);_(P0CD2);_(P0CD1); 1110 _(P0BVD2);_(P0BVD1); 1111 #undef _ 1112 printf("\n"); 1113 1114 printf("PCC0 General Control Register\n"); 1115 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1116 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0GCR_##m, #m) 1117 _(P0DRVE);_(P0PCCR);_(P0PCCT);_(P0VCC0);_(P0MMOD); 1118 _(P0PA25);_(P0PA24);_(P0REG); 1119 #undef _ 1120 printf("\n"); 1121 1122 printf("PCC0 Card Status Change Register\n"); 1123 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1124 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCR_##m, #m) 1125 _(P0SCDI);_(P0IREQ);_(P0SC);_(P0CDC);_(P0RC);_(P0BW);_(P0BD); 1126 #undef _ 1127 printf("\n"); 1128 1129 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1130 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1131 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0CSCIER_##m, #m) 1132 _(P0CRE);_(P0SCE);_(P0CDE);_(P0RE);_(P0BWE);_(P0BDE); 1133 #undef _ 1134 printf("\ninterrupt type: "); 1135 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1136 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1137 printf("none\n"); 1138 break; 1139 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1140 printf("level\n"); 1141 break; 1142 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1143 printf("falling edge\n"); 1144 break; 1145 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1146 printf("rising edge\n"); 1147 break; 1148 } 1149 1150 printf("PCC0 Software Control Register\n"); 1151 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1152 #define _(m) dbg_bitmask_print(r8, HD64461_PCC0SCR_##m, #m) 1153 _(P0VCC1);_(P0SWP); 1154 #undef _ 1155 printf("\n"); 1156 1157 /* 1158 * PCC1 1159 */ 1160 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1161 printf("PCC1 Interface Status Register\n"); 1162 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1163 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1ISR_##m, #m) 1164 _(P1READY);_(P1MWP);_(P1VS2);_(P1VS1);_(P1CD2);_(P1CD1); 1165 _(P1BVD2);_(P1BVD1); 1166 #undef _ 1167 printf("\n"); 1168 1169 printf("PCC1 General Contorol Register\n"); 1170 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1171 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1GCR_##m, #m) 1172 _(P1DRVE);_(P1PCCR);_(P1VCC0);_(P1MMOD);_(P1PA25);_(P1PA24);_(P1REG); 1173 #undef _ 1174 printf("\n"); 1175 1176 printf("PCC1 Card Status Change Register\n"); 1177 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1178 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCR_##m, #m) 1179 _(P1SCDI);_(P1CDC);_(P1RC);_(P1BW);_(P1BD); 1180 #undef _ 1181 printf("\n"); 1182 1183 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1184 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1185 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1CSCIER_##m, #m) 1186 _(P1CRE);_(P1CDE);_(P1RE);_(P1BWE);_(P1BDE); 1187 #undef _ 1188 printf("\n"); 1189 1190 printf("PCC1 Software Control Register\n"); 1191 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1192 #define _(m) dbg_bitmask_print(r8, HD64461_PCC1SCR_##m, #m) 1193 _(P1VCC1);_(P1SWP); 1194 #undef _ 1195 printf("\n"); 1196 1197 /* 1198 * General Control 1199 */ 1200 printf("[General Control]\n"); 1201 printf("PCC0 Output pins Control Register\n"); 1202 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1203 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP0OCR_##m, #m) 1204 _(P0DEPLUP);_(P0AEPLUP); 1205 #undef _ 1206 printf("\n"); 1207 1208 printf("PCC1 Output pins Control Register\n"); 1209 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1210 #define _(m) dbg_bitmask_print(r8, HD64461_PCCP1OCR_##m, #m) 1211 _(P1RST8MA);_(P1RST4MA);_(P1RAS8MA);_(P1RAS4MA); 1212 #undef _ 1213 printf("\n"); 1214 1215 printf("PC Card General Control Register\n"); 1216 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1217 #define _(m) dbg_bitmask_print(r8, HD64461_PCCPGCR_##m, #m) 1218 _(PSSDIR);_(PSSRDWR); 1219 #undef _ 1220 printf("\n"); 1221 1222 dbg_banner_line(); 1223 } 1224 #endif /* HD64461PCMCIA_DEBUG */ 1225
Indexes created Thu Oct 02 01:09:59 GMT 2025