hd64461pcmcia.c revision 1.8
1 /* $NetBSD: hd64461pcmcia.c,v 1.8 2001/12/15 13:23:21 soren Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #define HD64461PCMCIA_DEBUG 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 #include <sys/boot_flag.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #ifdef DEBUG 51 #include <hpcsh/hpcsh/debug.h> 52 #endif 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 60 #include <hpcsh/dev/hd64461/hd64461reg.h> 61 #include <hpcsh/dev/hd64461/hd64461var.h> 62 #include <hpcsh/dev/hd64461/hd64461intcvar.h> 63 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64461PCMCIA_DEBUG 69 int hd64461pcmcia_debug = 1; 70 #define DPRINTF(fmt, args...) \ 71 if (hd64461pcmcia_debug) \ 72 printf("%s: " fmt, __FUNCTION__ , ##args) 73 #define DPRINTFN(n, arg) \ 74 if (hd64461pcmcia_debug > (n)) \ 75 printf("%s: " fmt, __FUNCTION__ , ##args) 76 #else 77 #define DPRINTF(arg...) ((void)0) 78 #define DPRINTFN(n, arg...) ((void)0) 79 #endif 80 81 enum controller_channel { 82 CHANNEL_0 = 0, 83 CHANNEL_1 = 1, 84 CHANNEL_MAX = 2 85 }; 86 87 enum memory_window_mode { 88 MEMWIN_16M_MODE, 89 MEMWIN_32M_MODE 90 }; 91 92 enum memory_window_16 { 93 MEMWIN_16M_COMMON_0, 94 MEMWIN_16M_COMMON_1, 95 MEMWIN_16M_COMMON_2, 96 MEMWIN_16M_COMMON_3, 97 }; 98 #define MEMWIN_16M_MAX 4 99 100 enum memory_window_32 { 101 MEMWIN_32M_ATTR, 102 MEMWIN_32M_COMMON_0, 103 MEMWIN_32M_COMMON_1, 104 }; 105 #define MEMWIN_32M_MAX 3 106 107 enum hd64461pcmcia_event_type { 108 EVENT_NONE, 109 EVENT_INSERT, 110 EVENT_REMOVE, 111 }; 112 #define EVENT_QUEUE_MAX 5 113 114 struct hd64461pcmcia_softc; /* forward declaration */ 115 116 struct hd64461pcmcia_window_cookie { 117 bus_space_tag_t wc_tag; 118 bus_space_handle_t wc_handle; 119 int wc_size; 120 int wc_window; 121 }; 122 123 struct hd64461pcmcia_channel { 124 struct hd64461pcmcia_softc *ch_parent; 125 struct device *ch_pcmcia; 126 enum controller_channel ch_channel; 127 128 /* memory space */ 129 enum memory_window_mode ch_memory_window_mode; 130 bus_space_tag_t ch_memt; 131 bus_space_handle_t ch_memh; 132 bus_addr_t ch_membase_addr; 133 bus_size_t ch_memsize; 134 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 135 136 /* I/O space */ 137 bus_space_tag_t ch_iot; 138 bus_addr_t ch_iobase; 139 bus_size_t ch_iosize; 140 141 /* card interrupt */ 142 int (*ch_ih_card_func)(void *); 143 void *ch_ih_card_arg; 144 int ch_attached; 145 }; 146 147 struct hd64461pcmcia_event { 148 int __queued; 149 enum hd64461pcmcia_event_type pe_type; 150 struct hd64461pcmcia_channel *pe_ch; 151 SIMPLEQ_ENTRY(hd64461pcmcia_event) pe_link; 152 }; 153 154 struct hd64461pcmcia_softc { 155 struct device sc_dev; 156 enum hd64461_module_id sc_module_id; 157 int sc_shutdown; 158 159 /* CSC event */ 160 struct proc *sc_event_thread; 161 struct hd64461pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 162 SIMPLEQ_HEAD (, hd64461pcmcia_event) sc_event_head; 163 164 struct hd64461pcmcia_channel sc_ch[CHANNEL_MAX]; 165 }; 166 167 static int _chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *); 169 static void _chip_mem_free(pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *); 171 static int _chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 173 static void _chip_mem_unmap(pcmcia_chipset_handle_t, int); 174 static int _chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 176 static void _chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 177 static int _chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 178 bus_size_t, struct pcmcia_io_handle *, int *); 179 static void _chip_io_unmap(pcmcia_chipset_handle_t, int); 180 static void _chip_socket_enable(pcmcia_chipset_handle_t); 181 static void _chip_socket_disable(pcmcia_chipset_handle_t); 182 static void *_chip_intr_establish(pcmcia_chipset_handle_t, 183 struct pcmcia_function *, int, int (*)(void *), void *); 184 static void _chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 185 186 static struct pcmcia_chip_functions hd64461pcmcia_functions = { 187 _chip_mem_alloc, 188 _chip_mem_free, 189 _chip_mem_map, 190 _chip_mem_unmap, 191 _chip_io_alloc, 192 _chip_io_free, 193 _chip_io_map, 194 _chip_io_unmap, 195 _chip_intr_establish, 196 _chip_intr_disestablish, 197 _chip_socket_enable, 198 _chip_socket_disable, 199 }; 200 201 static int hd64461pcmcia_match(struct device *, struct cfdata *, void *); 202 static void hd64461pcmcia_attach(struct device *, struct device *, void *); 203 static int hd64461pcmcia_print(void *, const char *); 204 static int hd64461pcmcia_submatch(struct device *, struct cfdata *, void *); 205 206 struct cfattach hd64461pcmcia_ca = { 207 sizeof(struct hd64461pcmcia_softc), hd64461pcmcia_match, 208 hd64461pcmcia_attach 209 }; 210 211 static void hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *, 212 enum controller_channel); 213 /* hot plug */ 214 static void hd64461pcmcia_create_event_thread(void *); 215 static void hd64461pcmcia_event_thread(void *); 216 static void queue_event(struct hd64461pcmcia_channel *, 217 enum hd64461pcmcia_event_type); 218 /* interrupt handler */ 219 static int hd64461pcmcia_channel0_intr(void *); 220 static int hd64461pcmcia_channel1_intr(void *); 221 /* card status */ 222 static enum hd64461pcmcia_event_type detect_card(enum controller_channel); 223 static void power_off(enum controller_channel) __attribute__((__unused__)); 224 static void power_on(enum controller_channel) __attribute__((__unused__)); 225 /* memory window access ops */ 226 static void memory_window_mode(enum controller_channel, 227 enum memory_window_mode)__attribute__((__unused__)); 228 static void memory_window_16(enum controller_channel, enum memory_window_16); 229 /* bus width */ 230 static void set_bus_width(enum controller_channel, int); 231 #ifdef DEBUG 232 static void hd64461pcmcia_info(struct hd64461pcmcia_softc *); 233 #endif 234 /* fix SH3 Area[56] bug */ 235 static void fixup_sh3_pcmcia_area(bus_space_tag_t); 236 #define _BUS_SPACE_ACCESS_HOOK() \ 237 { \ 238 u_int8_t dummy __attribute__((__unused__)) = \ 239 *(volatile u_int8_t *)0xba000000; \ 240 } 241 _BUS_SPACE_WRITE(_sh3_pcmcia_bug, 1, 8) 242 _BUS_SPACE_WRITE_MULTI(_sh3_pcmcia_bug, 1, 8) 243 _BUS_SPACE_WRITE_REGION(_sh3_pcmcia_bug, 1, 8) 244 _BUS_SPACE_SET_MULTI(_sh3_pcmcia_bug, 1, 8) 245 #undef _BUS_SPACE_ACCESS_HOOK 246 247 #define DELAY_MS(x) delay((x) * 1000) 248 249 static int 250 hd64461pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 251 { 252 struct hd64461_attach_args *ha = aux; 253 254 return (ha->ha_module_id == HD64461_MODULE_PCMCIA); 255 } 256 257 static void 258 hd64461pcmcia_attach(struct device *parent, struct device *self, void *aux) 259 { 260 struct hd64461_attach_args *ha = aux; 261 struct hd64461pcmcia_softc *sc = (struct hd64461pcmcia_softc *)self; 262 263 sc->sc_module_id = ha->ha_module_id; 264 265 printf("\n"); 266 267 #ifdef DEBUG 268 if (bootverbose) 269 hd64461pcmcia_info(sc); 270 #endif 271 /* Channel 0/1 common CSC event queue */ 272 SIMPLEQ_INIT (&sc->sc_event_head); 273 kthread_create(hd64461pcmcia_create_event_thread, sc); 274 275 hd64461pcmcia_attach_channel(sc, CHANNEL_0); 276 hd64461pcmcia_attach_channel(sc, CHANNEL_1); 277 } 278 279 static void 280 hd64461pcmcia_create_event_thread(void *arg) 281 { 282 struct hd64461pcmcia_softc *sc = arg; 283 int error; 284 285 error = kthread_create1(hd64461pcmcia_event_thread, sc, 286 &sc->sc_event_thread, "%s", 287 sc->sc_dev.dv_xname); 288 KASSERT(error == 0); 289 } 290 291 static void 292 hd64461pcmcia_event_thread(void *arg) 293 { 294 struct hd64461pcmcia_softc *sc = arg; 295 struct hd64461pcmcia_event *pe; 296 int s; 297 298 while (!sc->sc_shutdown) { 299 tsleep(sc, PWAIT, "CSC wait", 0); 300 s = splhigh(); 301 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 302 splx(s); 303 switch (pe->pe_type) { 304 default: 305 printf("%s: unknown event.\n", __FUNCTION__); 306 break; 307 case EVENT_INSERT: 308 DPRINTF("insert event.\n"); 309 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 310 break; 311 case EVENT_REMOVE: 312 DPRINTF("remove event.\n"); 313 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 314 DETACH_FORCE); 315 break; 316 } 317 s = splhigh(); 318 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 319 pe->__queued = 0; 320 } 321 splx(s); 322 } 323 /* NOTREACHED */ 324 } 325 326 static int 327 hd64461pcmcia_print(void *arg, const char *pnp) 328 { 329 330 if (pnp) 331 printf("pcmcia at %s", pnp); 332 333 return (UNCONF); 334 } 335 336 static int 337 hd64461pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 338 { 339 struct pcmciabus_attach_args *paa = aux; 340 struct hd64461pcmcia_channel *ch = 341 (struct hd64461pcmcia_channel *)paa->pch; 342 343 if (ch->ch_channel == CHANNEL_0) { 344 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 345 PCMCIABUSCF_CONTROLLER_DEFAULT && 346 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 347 return 0; 348 } else { 349 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 350 PCMCIABUSCF_CONTROLLER_DEFAULT && 351 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 352 return 0; 353 } 354 paa->pct = (pcmcia_chipset_tag_t)&hd64461pcmcia_functions; 355 356 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 357 } 358 359 static void 360 hd64461pcmcia_attach_channel(struct hd64461pcmcia_softc *sc, 361 enum controller_channel channel) 362 { 363 struct device *parent = (struct device *)sc; 364 struct hd64461pcmcia_channel *ch = &sc->sc_ch[channel]; 365 struct pcmciabus_attach_args paa; 366 bus_addr_t membase; 367 int i; 368 369 ch->ch_parent = sc; 370 ch->ch_channel = channel; 371 372 /* 373 * Continuous 16-MB Area Mode 374 */ 375 /* Attibute/Common memory extent */ 376 membase = (channel == CHANNEL_0) 377 ? HD64461_PCC0_MEMBASE : HD64461_PCC1_MEMBASE; 378 379 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 380 membase, 0x01000000); /* 16MB */ 381 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x01000000, 382 0x01000000, 0x01000000, 0, &ch->ch_membase_addr, 383 &ch->ch_memh); 384 fixup_sh3_pcmcia_area(ch->ch_memt); 385 386 /* Common memory space extent */ 387 ch->ch_memsize = 0x01000000; 388 for (i = 0; i < MEMWIN_16M_MAX; i++) { 389 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 390 membase + 0x01000000, 391 ch->ch_memsize); 392 fixup_sh3_pcmcia_area(ch->ch_cmemt[i]); 393 } 394 395 /* I/O port extent and interrupt staff */ 396 _chip_socket_disable(ch); /* enable CSC interrupt only */ 397 398 if (channel == CHANNEL_0) { 399 ch->ch_iobase = 0; 400 ch->ch_iosize = HD64461_PCC0_IOSIZE; 401 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 402 HD64461_PCC0_IOBASE, 403 ch->ch_iosize); 404 fixup_sh3_pcmcia_area(ch->ch_iot); 405 406 hd64461_intr_establish(HD64461_IRQ_PCC0, IST_LEVEL, IPL_TTY, 407 hd64461pcmcia_channel0_intr, ch); 408 } else { 409 set_bus_width(CHANNEL_1, PCMCIA_WIDTH_IO16); 410 hd64461_intr_establish(HD64461_IRQ_PCC1, IST_EDGE, IPL_TTY, 411 hd64461pcmcia_channel1_intr, ch); 412 } 413 414 paa.paa_busname = "pcmcia"; 415 paa.pch = (pcmcia_chipset_handle_t)ch; 416 paa.iobase = ch->ch_iobase; 417 paa.iosize = ch->ch_iosize; 418 419 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64461pcmcia_print, 420 hd64461pcmcia_submatch); 421 422 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 423 ch->ch_attached = 1; 424 pcmcia_card_attach(ch->ch_pcmcia); 425 } 426 } 427 428 static int 429 hd64461pcmcia_channel0_intr(void *arg) 430 { 431 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 432 u_int8_t r; 433 int ret = 0; 434 435 r = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 436 /* clear interrtupt (edge source only) */ 437 hd64461_reg_write_1(HD64461_PCC0CSCR_REG8, 0); 438 439 if (r & HD64461_PCC0CSCR_P0IREQ) { 440 if (ch->ch_ih_card_func) { 441 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 442 } else 443 DPRINTF("spurious IREQ interrupt.\n"); 444 } 445 446 if (r & HD64461_PCC0CSCR_P0CDC) 447 queue_event(ch, detect_card(ch->ch_channel)); 448 449 return ret; 450 } 451 452 static int 453 hd64461pcmcia_channel1_intr(void *arg) 454 { 455 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)arg; 456 u_int8_t r; 457 int ret = 0; 458 459 r = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 460 /* clear interrtupt */ 461 hd64461_reg_write_1(HD64461_PCC1CSCR_REG8, 0); 462 463 if (r & HD64461_PCC1CSCR_P1RC) { 464 if (ch->ch_ih_card_func) 465 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 466 else 467 DPRINTF("spurious READY interrupt.\n"); 468 } 469 470 if (r & HD64461_PCC1CSCR_P1CDC) 471 queue_event(ch, detect_card(ch->ch_channel)); 472 473 return ret; 474 } 475 476 static void 477 queue_event(struct hd64461pcmcia_channel *ch, 478 enum hd64461pcmcia_event_type type) 479 { 480 struct hd64461pcmcia_event *pe, *pool; 481 struct hd64461pcmcia_softc *sc = ch->ch_parent; 482 int i; 483 int s = splhigh(); 484 485 if (type == EVENT_NONE) 486 goto out; 487 488 pe = 0; 489 pool = sc->sc_event_pool; 490 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 491 if (!pool[i].__queued) { 492 pe = &pool[i]; 493 break; 494 } 495 } 496 497 if (pe == 0) { 498 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 499 EVENT_QUEUE_MAX); 500 goto out; 501 } 502 503 if ((ch->ch_attached && (type == EVENT_INSERT)) || 504 (!ch->ch_attached && (type == EVENT_REMOVE))) { 505 DPRINTF("spurious CSC interrupt.\n"); 506 goto out; 507 } 508 509 ch->ch_attached = (type == EVENT_INSERT); 510 pe->__queued = 1; 511 pe->pe_type = type; 512 pe->pe_ch = ch; 513 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 514 wakeup(sc); 515 out: 516 splx(s); 517 } 518 519 /* 520 * interface for pcmcia driver. 521 */ 522 static void * 523 _chip_intr_establish(pcmcia_chipset_handle_t pch, struct pcmcia_function *pf, 524 int ipl, int (*ih_func)(void *), void *ih_arg) 525 { 526 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 527 int channel = ch->ch_channel; 528 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 529 int s = splhigh(); 530 u_int8_t r; 531 532 ch->ch_ih_card_func = ih_func; 533 ch->ch_ih_card_arg = ih_arg; 534 535 /* enable card interrupt */ 536 r = hd64461_reg_read_1(cscier); 537 if (channel == CHANNEL_0) { 538 /* set level mode */ 539 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 540 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 541 } else { 542 /* READY-pin LOW to HIGH changes generates interrupt */ 543 r |= HD64461_PCC1CSCIER_P1RE; 544 } 545 hd64461_reg_write_1(cscier, r); 546 547 splx(s); 548 549 return (void *)ih_func; 550 } 551 552 static void 553 _chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 554 { 555 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 556 int channel = ch->ch_channel; 557 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 558 int s = splhigh(); 559 u_int8_t r; 560 561 /* disable card interrupt */ 562 r = hd64461_reg_read_1(cscier); 563 if (channel == CHANNEL_0) { 564 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 565 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 566 } else { 567 r &= ~HD64461_PCC1CSCIER_P1RE; 568 } 569 hd64461_reg_write_1(cscier, r); 570 571 ch->ch_ih_card_func = 0; 572 573 splx(s); 574 } 575 576 static int 577 _chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 578 struct pcmcia_mem_handle *pcmhp) 579 { 580 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 581 582 pcmhp->memt = ch->ch_memt; 583 pcmhp->addr = ch->ch_membase_addr; 584 pcmhp->memh = ch->ch_memh; 585 pcmhp->size = size; 586 pcmhp->realsize = size; 587 588 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 589 590 return (0); 591 } 592 593 static void 594 _chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 595 { 596 /* nothing to do */ 597 } 598 599 static int 600 _chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, 601 bus_size_t size, struct pcmcia_mem_handle *pcmhp, 602 bus_size_t *offsetp, int *windowp) 603 { 604 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 605 struct hd64461pcmcia_window_cookie *cookie; 606 bus_addr_t ofs; 607 608 cookie = malloc(sizeof(struct hd64461pcmcia_window_cookie), 609 M_DEVBUF, M_NOWAIT); 610 KASSERT(cookie); 611 memset(cookie, 0, sizeof(struct hd64461pcmcia_window_cookie)); 612 613 /* Address */ 614 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 615 cookie->wc_tag = ch->ch_memt; 616 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 617 size, &cookie->wc_handle) != 0) 618 goto bad; 619 620 *offsetp = card_addr; 621 cookie->wc_window = -1; 622 } else { 623 int window = card_addr / ch->ch_memsize; 624 KASSERT(window < MEMWIN_16M_MAX); 625 626 cookie->wc_tag = ch->ch_cmemt[window]; 627 ofs = card_addr - window * ch->ch_memsize; 628 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 629 &cookie->wc_handle) != 0) 630 goto bad; 631 632 /* XXX bogus. check window per common memory access. */ 633 memory_window_16(ch->ch_channel, window); 634 *offsetp = ofs + 0x01000000; /* skip attribute area */ 635 cookie->wc_window = window; 636 } 637 cookie->wc_size = size; 638 *windowp = (int)cookie; 639 640 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 641 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, 642 size); 643 644 return (0); 645 bad: 646 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 647 free(cookie, M_DEVBUF); 648 649 return (1); 650 } 651 652 static void 653 _chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 654 { 655 struct hd64461pcmcia_window_cookie *cookie = (void *)window; 656 657 if (cookie->wc_window != -1) 658 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 659 cookie->wc_size); 660 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 661 free(cookie, M_DEVBUF); 662 } 663 664 static int 665 _chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, 666 bus_size_t align, struct pcmcia_io_handle *pcihp) 667 { 668 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 669 670 if (ch->ch_channel == CHANNEL_1) 671 return (1); 672 673 if (start) { 674 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 675 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 676 return (1); 677 } 678 DPRINTF("map %#lx+%#lx\n", start, size); 679 } else { 680 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 681 ch->ch_iobase + ch->ch_iosize - 1, 682 size, align, 0, 0, &pcihp->addr, 683 &pcihp->ioh)) { 684 DPRINTF("couldn't allocate %#lx\n", size); 685 return (1); 686 } 687 pcihp->flags = PCMCIA_IO_ALLOCATED; 688 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 689 } 690 691 pcihp->iot = ch->ch_iot; 692 pcihp->size = size; 693 694 return (0); 695 } 696 697 static int 698 _chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 699 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 700 { 701 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 702 #ifdef HD64461PCMCIA_DEBUG 703 static char *width_names[] = { "auto", "io8", "io16" }; 704 #endif 705 if (ch->ch_channel == CHANNEL_1) 706 return (1); 707 708 set_bus_width(CHANNEL_0, width); 709 710 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 711 width_names[width]); 712 713 return (0); 714 } 715 716 static void 717 _chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp) 718 { 719 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 720 721 if (ch->ch_channel == CHANNEL_1) 722 return; 723 724 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 725 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 726 else 727 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 728 729 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 730 } 731 732 static void 733 _chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 734 { 735 /* nothing to do */ 736 } 737 738 static void 739 _chip_socket_enable(pcmcia_chipset_handle_t pch) 740 { 741 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 742 int channel = ch->ch_channel; 743 bus_addr_t isr, gcr; 744 u_int8_t r; 745 int cardtype; 746 747 DPRINTF("enable channel %d\n", channel); 748 isr = HD64461_PCCISR(channel); 749 gcr = HD64461_PCCGCR(channel); 750 751 power_off(channel); 752 power_on(channel); 753 #if notyet 754 { 755 int i; 756 /* assert reset */ 757 r = hd64461_reg_read_1(gcr); 758 r |= HD64461_PCCGCR_PCCR; 759 hd64461_reg_write_1(gcr, r); 760 761 /* 762 * hold RESET at least 10us. 763 */ 764 DELAY_MS(20); 765 766 /* clear the reset flag */ 767 r &= ~HD64461_PCCGCR_PCCR; 768 hd64461_reg_write_1(gcr, r); 769 DELAY_MS(2000); 770 771 /* wait for the chip to finish initializing */ 772 for (i = 0; i < 10000; i++) { 773 if ((hd64461_reg_read_1(isr) & HD64461_PCCISR_READY)) 774 goto reset_ok; 775 DELAY_MS(500); 776 777 if ((i > 5000) && (i % 100 == 99)) 778 printf("."); 779 } 780 printf("reset failed.\n"); 781 power_off(channel); 782 return; 783 reset_ok: 784 } 785 #endif /* notyet */ 786 /* set Continuous 16-MB Area Mode */ 787 ch->ch_memory_window_mode = MEMWIN_16M_MODE; 788 memory_window_mode(channel, ch->ch_memory_window_mode); 789 790 /* 791 * set Common memory area. 792 */ 793 memory_window_16(channel, MEMWIN_16M_COMMON_0); 794 795 /* set the card type */ 796 r = hd64461_reg_read_1(gcr); 797 if (channel == CHANNEL_0) { 798 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 799 if (cardtype == PCMCIA_IFTYPE_IO) 800 r |= HD64461_PCC0GCR_P0PCCT; 801 else 802 r &= ~HD64461_PCC0GCR_P0PCCT; 803 } else { 804 /* reserved bit must be 0 */ 805 r &= ~HD64461_PCC1GCR_RESERVED; 806 } 807 hd64461_reg_write_1(gcr, r); 808 809 DPRINTF("OK.\n"); 810 } 811 812 static void 813 _chip_socket_disable(pcmcia_chipset_handle_t pch) 814 { 815 struct hd64461pcmcia_channel *ch = (struct hd64461pcmcia_channel *)pch; 816 int channel = ch->ch_channel; 817 818 /* dont' disable CSC interrupt */ 819 hd64461_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 820 hd64461_reg_write_1(HD64461_PCCCSCR(channel), 0); 821 822 /* power down the socket */ 823 power_off(channel); 824 } 825 826 /* 827 * Card detect 828 */ 829 static void 830 power_off(enum controller_channel channel) 831 { 832 #if notyet 833 u_int8_t r; 834 u_int16_t r16; 835 bus_addr_t scr, gcr; 836 837 gcr = HD64461_PCCGCR(channel); 838 scr = HD64461_PCCSCR(channel); 839 840 /* DRV (external buffer) high level */ 841 r = hd64461_reg_read_1(gcr); 842 r &= ~HD64461_PCCGCR_DRVE; 843 hd64461_reg_write_1(gcr, r); 844 845 /* stop power */ 846 r = hd64461_reg_read_1(scr); 847 r |= HD64461_PCCSCR_VCC1; /* VCC1 high */ 848 hd64461_reg_write_1(scr, r); 849 r = hd64461_reg_read_1(gcr); 850 r |= HD64461_PCCGCR_VCC0; /* VCC0 high */ 851 hd64461_reg_write_1(gcr, r); 852 /* 853 * wait 300ms until power fails (Tpf). Then, wait 100ms since 854 * we are changing Vcc (Toff). 855 */ 856 DELAY_MS(300 + 100); 857 858 /* stop clock */ 859 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 860 r16 |= (channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 861 HD64461_SYSSTBCR_SPC1ST); 862 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 863 864 if (channel == CHANNEL_0) { 865 /* GPIO Port A XXX Jornada690 specific? */ 866 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 867 r16 |= 0xf; 868 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 869 } 870 871 #endif /* notyet */ 872 } 873 874 static void 875 power_on(enum controller_channel channel) 876 { 877 u_int8_t r; 878 u_int16_t r16; 879 bus_addr_t scr, gcr, isr; 880 881 isr = HD64461_PCCISR(channel); 882 gcr = HD64461_PCCGCR(channel); 883 scr = HD64461_PCCSCR(channel); 884 885 /* 886 * XXX to access attribute memory, this is required. 887 */ 888 if (channel == CHANNEL_0) { 889 /* GPIO Port A XXX Jonanada690 specific? */ 890 r16 = hd64461_reg_read_2(HD64461_GPADR_REG16); 891 r16 &= ~0xf; 892 r16 |= 0x5; 893 hd64461_reg_write_2(HD64461_GPADR_REG16, r16); 894 } 895 896 if (channel == CHANNEL_1) { 897 /* GPIO Port C, Port D XXX HP620LX specific? */ 898 hd64461_reg_write_2(HD64461_GPCCR_REG16, 0xa800); 899 hd64461_reg_write_2(HD64461_GPDCR_REG16, 0xaa0a); 900 } 901 902 /* supply clock */ 903 r16 = hd64461_reg_read_2(HD64461_SYSSTBCR_REG16); 904 r16 &= ~(channel == CHANNEL_0 ? HD64461_SYSSTBCR_SPC0ST : 905 HD64461_SYSSTBCR_SPC1ST); 906 hd64461_reg_write_2(HD64461_SYSSTBCR_REG16, r16); 907 DELAY_MS(200); 908 909 /* detect voltage and supply VCC */ 910 r = hd64461_reg_read_1(isr); 911 switch (r & (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2)) { 912 case (HD64461_PCCISR_VS1 | HD64461_PCCISR_VS2): /* 5 V */ 913 DPRINTF("5V card\n"); 914 r = hd64461_reg_read_1(gcr); 915 r &= ~HD64461_PCCGCR_VCC0; 916 hd64461_reg_write_1(gcr, r); 917 r = hd64461_reg_read_1(scr); 918 r &= ~HD64461_PCCSCR_VCC1; 919 hd64461_reg_write_1(scr, r); 920 break; 921 case HD64461_PCCISR_VS2: /* 3.3 / 5 V */ 922 /* FALLTHROUGH */ 923 case 0: /* x.x / 3.3 / 5 V */ 924 DPRINTF("3.3V card\n"); 925 if (channel == CHANNEL_1) { 926 r = hd64461_reg_read_1(gcr); 927 r &= ~HD64461_PCCGCR_VCC0; 928 hd64461_reg_write_1(gcr, r); 929 } else { 930 r = hd64461_reg_read_1(gcr); 931 r |= HD64461_PCCGCR_VCC0; 932 hd64461_reg_write_1(gcr, r); 933 } 934 r = hd64461_reg_read_1(scr); 935 r &= ~HD64461_PCCSCR_VCC1; 936 hd64461_reg_write_1(scr, r); 937 break; 938 case HD64461_PCCISR_VS1: /* x.x V */ 939 /* FALLTHROUGH */ 940 printf("x.x V not supported.\n"); 941 return; 942 default: 943 printf("\nunknown Voltage. don't attach.\n"); 944 return; 945 } 946 /* 947 * wait 100ms until power raise (Tpr) and 20ms to become 948 * stable (Tsu(Vcc)). 949 * 950 * some machines require some more time to be settled 951 * (300ms is added here). 952 */ 953 DELAY_MS(100 + 20 + 300); 954 955 /* DRV (external buffer) low level */ 956 r = hd64461_reg_read_1(gcr); 957 r |= HD64461_PCCGCR_DRVE; 958 hd64461_reg_write_1(gcr, r); 959 960 /* clear interrupt */ 961 hd64461_reg_write_1(channel == CHANNEL_0 ? HD64461_PCC0CSCR_REG8 : 962 HD64461_PCC1CSCR_REG8, 0); 963 } 964 965 static enum hd64461pcmcia_event_type 966 detect_card(enum controller_channel channel) 967 { 968 u_int8_t r; 969 970 r = hd64461_reg_read_1(HD64461_PCCISR(channel)) & 971 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 972 973 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 974 DPRINTF("remove\n"); 975 return EVENT_REMOVE; 976 } 977 if (r == 0) { 978 DPRINTF("insert\n"); 979 return EVENT_INSERT; 980 } 981 DPRINTF("transition\n"); 982 983 return EVENT_NONE; 984 } 985 986 /* 987 * Memory window access ops. 988 */ 989 static void 990 memory_window_mode(enum controller_channel channel, 991 enum memory_window_mode mode) 992 { 993 bus_addr_t a = HD64461_PCCGCR(channel); 994 u_int8_t r = hd64461_reg_read_1(a); 995 996 r &= ~HD64461_PCCGCR_MMOD; 997 r |= (mode == MEMWIN_16M_MODE) ? HD64461_PCCGCR_MMOD_16M : 998 HD64461_PCCGCR_MMOD_32M; 999 hd64461_reg_write_1(a, r); 1000 } 1001 1002 static void 1003 memory_window_16(enum controller_channel channel, enum memory_window_16 window) 1004 { 1005 bus_addr_t a = HD64461_PCCGCR(channel); 1006 u_int8_t r; 1007 1008 r = hd64461_reg_read_1(a); 1009 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1010 1011 switch (window) { 1012 case MEMWIN_16M_COMMON_0: 1013 break; 1014 case MEMWIN_16M_COMMON_1: 1015 r |= HD64461_PCCGCR_PA24; 1016 break; 1017 case MEMWIN_16M_COMMON_2: 1018 r |= HD64461_PCCGCR_PA25; 1019 break; 1020 case MEMWIN_16M_COMMON_3: 1021 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 1022 break; 1023 } 1024 1025 hd64461_reg_write_1(a, r); 1026 } 1027 1028 #if unused 1029 static void 1030 memory_window_32(enum controller_channel channel, enum memory_window_32 window) 1031 { 1032 bus_addr_t a = HD64461_PCCGCR(channel); 1033 u_int8_t r; 1034 1035 r = hd64461_reg_read_1(a); 1036 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1037 1038 switch (window) { 1039 case MEMWIN_32M_ATTR: 1040 break; 1041 case MEMWIN_32M_COMMON_0: 1042 r |= HD64461_PCCGCR_PREG; 1043 break; 1044 case MEMWIN_32M_COMMON_1: 1045 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PREG); 1046 break; 1047 } 1048 1049 hd64461_reg_write_1(a, r); 1050 } 1051 #endif 1052 1053 static void 1054 set_bus_width(enum controller_channel channel, int width) 1055 { 1056 u_int16_t r16; 1057 1058 r16 = SHREG_BCR2; 1059 if (channel == CHANNEL_0) { 1060 r16 &= ~((1 << 13)|(1 << 12)); 1061 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 1062 } else { 1063 r16 &= ~((1 << 11)|(1 << 10)); 1064 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 1065 } 1066 SHREG_BCR2 = r16; 1067 } 1068 1069 static void 1070 fixup_sh3_pcmcia_area(bus_space_tag_t t) 1071 { 1072 struct hpcsh_bus_space *hbs = (void *)t; 1073 1074 hbs->hbs_w_1 = _sh3_pcmcia_bug_write_1; 1075 hbs->hbs_wm_1 = _sh3_pcmcia_bug_write_multi_1; 1076 hbs->hbs_wr_1 = _sh3_pcmcia_bug_write_region_1; 1077 hbs->hbs_sm_1 = _sh3_pcmcia_bug_set_multi_1; 1078 } 1079 1080 #ifdef DEBUG 1081 static void 1082 hd64461pcmcia_info(struct hd64461pcmcia_softc *sc) 1083 { 1084 const char name[] = __FUNCTION__; 1085 u_int8_t r8; 1086 1087 dbg_banner_start(name, sizeof name); 1088 /* 1089 * PCC0 1090 */ 1091 printf("[PCC0 memory and I/O card (SH3 Area 6)]\n"); 1092 printf("PCC0 Interface Status Register\n"); 1093 r8 = hd64461_reg_read_1(HD64461_PCC0ISR_REG8); 1094 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 1095 DBG_BIT_PRINT(r8, P0READY); 1096 DBG_BIT_PRINT(r8, P0MWP); 1097 DBG_BIT_PRINT(r8, P0VS2); 1098 DBG_BIT_PRINT(r8, P0VS1); 1099 DBG_BIT_PRINT(r8, P0CD2); 1100 DBG_BIT_PRINT(r8, P0CD1); 1101 DBG_BIT_PRINT(r8, P0BVD2); 1102 DBG_BIT_PRINT(r8, P0BVD1); 1103 #undef DBG_BIT_PRINT 1104 printf("\n"); 1105 1106 printf("PCC0 General Control Register\n"); 1107 r8 = hd64461_reg_read_1(HD64461_PCC0GCR_REG8); 1108 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 1109 DBG_BIT_PRINT(r8, P0DRVE); 1110 DBG_BIT_PRINT(r8, P0PCCR); 1111 DBG_BIT_PRINT(r8, P0PCCT); 1112 DBG_BIT_PRINT(r8, P0VCC0); 1113 DBG_BIT_PRINT(r8, P0MMOD); 1114 DBG_BIT_PRINT(r8, P0PA25); 1115 DBG_BIT_PRINT(r8, P0PA24); 1116 DBG_BIT_PRINT(r8, P0REG); 1117 #undef DBG_BIT_PRINT 1118 printf("\n"); 1119 1120 printf("PCC0 Card Status Change Register\n"); 1121 r8 = hd64461_reg_read_1(HD64461_PCC0CSCR_REG8); 1122 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 1123 DBG_BIT_PRINT(r8, P0SCDI); 1124 DBG_BIT_PRINT(r8, P0IREQ); 1125 DBG_BIT_PRINT(r8, P0SC); 1126 DBG_BIT_PRINT(r8, P0CDC); 1127 DBG_BIT_PRINT(r8, P0RC); 1128 DBG_BIT_PRINT(r8, P0BW); 1129 DBG_BIT_PRINT(r8, P0BD); 1130 #undef DBG_BIT_PRINT 1131 printf("\n"); 1132 1133 printf("PCC0 Card Status Change Interrupt Enable Register\n"); 1134 r8 = hd64461_reg_read_1(HD64461_PCC0CSCIER_REG8); 1135 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 1136 DBG_BIT_PRINT(r8, P0CRE); 1137 DBG_BIT_PRINT(r8, P0SCE); 1138 DBG_BIT_PRINT(r8, P0CDE); 1139 DBG_BIT_PRINT(r8, P0RE); 1140 DBG_BIT_PRINT(r8, P0BWE); 1141 DBG_BIT_PRINT(r8, P0BDE); 1142 #undef DBG_BIT_PRINT 1143 printf("\ninterrupt type: "); 1144 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 1145 case HD64461_PCC0CSCIER_P0IREQE_NONE: 1146 printf("none\n"); 1147 break; 1148 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 1149 printf("level\n"); 1150 break; 1151 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 1152 printf("falling edge\n"); 1153 break; 1154 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 1155 printf("rising edge\n"); 1156 break; 1157 } 1158 1159 printf("PCC0 Software Control Register\n"); 1160 r8 = hd64461_reg_read_1(HD64461_PCC0SCR_REG8); 1161 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 1162 DBG_BIT_PRINT(r8, P0VCC1); 1163 DBG_BIT_PRINT(r8, P0SWP); 1164 #undef DBG_BIT_PRINT 1165 printf("\n"); 1166 1167 /* 1168 * PCC1 1169 */ 1170 printf("[PCC1 memory card only (SH3 Area 5)]\n"); 1171 printf("PCC1 Interface Status Register\n"); 1172 r8 = hd64461_reg_read_1(HD64461_PCC1ISR_REG8); 1173 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 1174 DBG_BIT_PRINT(r8, P1READY); 1175 DBG_BIT_PRINT(r8, P1MWP); 1176 DBG_BIT_PRINT(r8, P1VS2); 1177 DBG_BIT_PRINT(r8, P1VS1); 1178 DBG_BIT_PRINT(r8, P1CD2); 1179 DBG_BIT_PRINT(r8, P1CD1); 1180 DBG_BIT_PRINT(r8, P1BVD2); 1181 DBG_BIT_PRINT(r8, P1BVD1); 1182 #undef DBG_BIT_PRINT 1183 printf("\n"); 1184 1185 printf("PCC1 General Contorol Register\n"); 1186 r8 = hd64461_reg_read_1(HD64461_PCC1GCR_REG8); 1187 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 1188 DBG_BIT_PRINT(r8, P1DRVE); 1189 DBG_BIT_PRINT(r8, P1PCCR); 1190 DBG_BIT_PRINT(r8, P1VCC0); 1191 DBG_BIT_PRINT(r8, P1MMOD); 1192 DBG_BIT_PRINT(r8, P1PA25); 1193 DBG_BIT_PRINT(r8, P1PA24); 1194 DBG_BIT_PRINT(r8, P1REG); 1195 #undef DBG_BIT_PRINT 1196 printf("\n"); 1197 1198 printf("PCC1 Card Status Change Register\n"); 1199 r8 = hd64461_reg_read_1(HD64461_PCC1CSCR_REG8); 1200 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 1201 DBG_BIT_PRINT(r8, P1SCDI); 1202 DBG_BIT_PRINT(r8, P1CDC); 1203 DBG_BIT_PRINT(r8, P1RC); 1204 DBG_BIT_PRINT(r8, P1BW); 1205 DBG_BIT_PRINT(r8, P1BD); 1206 #undef DBG_BIT_PRINT 1207 printf("\n"); 1208 1209 printf("PCC1 Card Status Change Interrupt Enable Register\n"); 1210 r8 = hd64461_reg_read_1(HD64461_PCC1CSCIER_REG8); 1211 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 1212 DBG_BIT_PRINT(r8, P1CRE); 1213 DBG_BIT_PRINT(r8, P1CDE); 1214 DBG_BIT_PRINT(r8, P1RE); 1215 DBG_BIT_PRINT(r8, P1BWE); 1216 DBG_BIT_PRINT(r8, P1BDE); 1217 #undef DBG_BIT_PRINT 1218 printf("\n"); 1219 1220 printf("PCC1 Software Control Register\n"); 1221 r8 = hd64461_reg_read_1(HD64461_PCC1SCR_REG8); 1222 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 1223 DBG_BIT_PRINT(r8, P1VCC1); 1224 DBG_BIT_PRINT(r8, P1SWP); 1225 #undef DBG_BIT_PRINT 1226 printf("\n"); 1227 1228 /* 1229 * General Control 1230 */ 1231 printf("[General Control]\n"); 1232 printf("PCC0 Output pins Control Register\n"); 1233 r8 = hd64461_reg_read_1(HD64461_PCCP0OCR_REG8); 1234 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 1235 DBG_BIT_PRINT(r8, P0DEPLUP); 1236 DBG_BIT_PRINT(r8, P0AEPLUP); 1237 #undef DBG_BIT_PRINT 1238 printf("\n"); 1239 1240 printf("PCC1 Output pins Control Register\n"); 1241 r8 = hd64461_reg_read_1(HD64461_PCCP1OCR_REG8); 1242 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 1243 DBG_BIT_PRINT(r8, P1RST8MA); 1244 DBG_BIT_PRINT(r8, P1RST4MA); 1245 DBG_BIT_PRINT(r8, P1RAS8MA); 1246 DBG_BIT_PRINT(r8, P1RAS4MA); 1247 #undef DBG_BIT_PRINT 1248 printf("\n"); 1249 1250 printf("PC Card General Control Register\n"); 1251 r8 = hd64461_reg_read_1(HD64461_PCCPGCR_REG8); 1252 #define DBG_BIT_PRINT(r, m) dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 1253 DBG_BIT_PRINT(r8, PSSDIR); 1254 DBG_BIT_PRINT(r8, PSSRDWR); 1255 #undef DBG_BIT_PRINT 1256 printf("\n"); 1257 1258 dbg_banner_end(); 1259 } 1260 #endif /* DEBUG */ 1261
Indexes created Thu Oct 02 01:09:59 GMT 2025