hd64461pcmciareg.h revision 1.3.78.1
1 1.3.78.1 yamt /* $NetBSD: hd64461pcmciareg.h,v 1.3.78.1 2008/05/16 02:22:30 yamt Exp $ */ 2 1.1 uch 3 1.1 uch /*- 4 1.1 uch * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.1 uch * by UCHIYAMA Yasushi. 9 1.1 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 uch * notice, this list of conditions and the following disclaimer in the 17 1.1 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.3 uwe #ifndef _HPCSH_DEV_HD64461PCMCIAREG_H_ 33 1.3 uwe #define _HPCSH_DEV_HD64461PCMCIAREG_H_ 34 1.3 uwe 35 1.1 uch /* 36 1.1 uch * PCC0 SH7709 Area 6 (memory and I/O card) 37 1.1 uch */ 38 1.3 uwe 39 1.1 uch /* PCC0 Interface Status Register (R) */ 40 1.1 uch #define HD64461_PCC0ISR_REG8 0xb0002000 41 1.1 uch #define HD64461_PCC0ISR_P0READY HD64461_PCCISR_READY 42 1.1 uch #define HD64461_PCC0ISR_IREQ HD64461_PCCISR_READY 43 1.1 uch #define HD64461_PCC0ISR_P0MWP HD64461_PCCISR_MWP 44 1.1 uch #define HD64461_PCC0ISR_P0VS2 HD64461_PCCISR_VS2 45 1.1 uch #define HD64461_PCC0ISR_P0VS1 HD64461_PCCISR_VS1 46 1.1 uch #define HD64461_PCC0ISR_P0CD2 HD64461_PCCISR_CD2 47 1.1 uch #define HD64461_PCC0ISR_P0CD1 HD64461_PCCISR_CD1 48 1.1 uch #define HD64461_PCC0ISR_P0BVD2 HD64461_PCCISR_BVD2 49 1.1 uch #define HD64461_PCC0ISR_SPKR0 HD64461_PCCISR_BVD2 50 1.1 uch #define HD64461_PCC0ISR_P0BVD1 HD64461_PCCISR_BVD1 51 1.1 uch #define HD64461_PCC0ISR_STSCHG0 HD64461_PCCISR_BVD1 52 1.1 uch 53 1.1 uch /* PCC0 General Contorol Register (R/W) */ 54 1.1 uch #define HD64461_PCC0GCR_REG8 0xb0002002 55 1.1 uch #define HD64461_PCC0GCR_P0DRVE HD64461_PCCGCR_DRVE 56 1.1 uch #define HD64461_PCC0GCR_P0PCCR HD64461_PCCGCR_PCCR 57 1.2 uch #define HD64461_PCC0GCR_P0PCCT HD64461_PCCGCR_PCCT 58 1.1 uch #define HD64461_PCC0GCR_P0VCC0 HD64461_PCCGCR_VCC0 59 1.1 uch #define HD64461_PCC0GCR_P0MMOD HD64461_PCCGCR_MMOD 60 1.1 uch #define HD64461_PCC0GCR_P0MMOD_16M HD64461_PCCGCR_MMOD_16M 61 1.1 uch #define HD64461_PCC0GCR_P0MMOD_32M HD64461_PCCGCR_MMOD_32M 62 1.1 uch /* these bits meaning different for P0MMOD mode */ 63 1.1 uch #define HD64461_PCC0GCR_P0PA25 HD64461_PCCGCR_PA25 64 1.1 uch #define HD64461_PCC0GCR_P0PA24 HD64461_PCCGCR_PA24 65 1.1 uch #define HD64461_PCC0GCR_P0REG HD64461_PCCGCR_PREG 66 1.1 uch 67 1.1 uch /* PCC0 Card Status Change Register (R/W) */ 68 1.1 uch #define HD64461_PCC0CSCR_REG8 0xb0002004 69 1.1 uch #define HD64461_PCC0CSCR_P0SCDI HD64461_PCCCSCR_SCDI 70 1.1 uch #define HD64461_PCC0CSCR_P0IREQ 0x20 71 1.1 uch #define HD64461_PCC0CSCR_P0SC 0x10 72 1.1 uch #define HD64461_PCC0CSCR_P0CDC HD64461_PCCCSCR_CDC 73 1.1 uch #define HD64461_PCC0CSCR_P0RC HD64461_PCCCSCR_RC 74 1.1 uch #define HD64461_PCC0CSCR_P0BW HD64461_PCCCSCR_BW 75 1.1 uch #define HD64461_PCC0CSCR_P0BD HD64461_PCCCSCR_BD 76 1.1 uch 77 1.1 uch /* PCC0 Card Status Change Interrupt Enable Register (R/W) */ 78 1.1 uch #define HD64461_PCC0CSCIER_REG8 0xb0002006 79 1.1 uch #define HD64461_PCC0CSCIER_P0CRE HD64461_PCCCSCIER_CRE 80 1.1 uch 81 1.1 uch #define HD64461_PCC0CSCIER_P0IREQE_MASK 0x60 82 1.1 uch #define HD64461_PCC0CSCIER_P0IREQE_NONE 0x00 83 1.1 uch #define HD64461_PCC0CSCIER_P0IREQE_LEVEL 0x20 84 1.1 uch #define HD64461_PCC0CSCIER_P0IREQE_FEDGE 0x40 85 1.1 uch #define HD64461_PCC0CSCIER_P0IREQE_REDGE 0x60 86 1.1 uch 87 1.1 uch #define HD64461_PCC0CSCIER_P0SCE 0x10 88 1.1 uch #define HD64461_PCC0CSCIER_P0CDE HD64461_PCCCSCIER_CDE 89 1.1 uch #define HD64461_PCC0CSCIER_P0RE HD64461_PCCCSCIER_RE 90 1.1 uch #define HD64461_PCC0CSCIER_P0BWE HD64461_PCCCSCIER_BWE 91 1.1 uch #define HD64461_PCC0CSCIER_P0BDE HD64461_PCCCSCIER_BDE 92 1.1 uch 93 1.1 uch /* PCC0 Software Control Register (R/W) */ 94 1.1 uch #define HD64461_PCC0SCR_REG8 0xb0002008 95 1.1 uch #define HD64461_PCC0SCR_P0VCC1 HD64461_PCCSCR_VCC1 96 1.1 uch #define HD64461_PCC0SCR_P0SWP HD64461_PCCSCR_SWP 97 1.1 uch 98 1.1 uch /* 99 1.1 uch * PCC1 SH7709 Area 5 (memory card only) 100 1.1 uch */ 101 1.1 uch /* PCC1 Interface Status Register (R) */ 102 1.1 uch #define HD64461_PCC1ISR_REG8 0xb0002010 103 1.1 uch #define HD64461_PCC1ISR_P1READY HD64461_PCCISR_READY 104 1.1 uch #define HD64461_PCC1ISR_P1MWP HD64461_PCCISR_MWP 105 1.1 uch #define HD64461_PCC1ISR_P1VS2 HD64461_PCCISR_VS2 106 1.1 uch #define HD64461_PCC1ISR_P1VS1 HD64461_PCCISR_VS1 107 1.1 uch #define HD64461_PCC1ISR_P1CD2 HD64461_PCCISR_CD2 108 1.1 uch #define HD64461_PCC1ISR_P1CD1 HD64461_PCCISR_CD1 109 1.1 uch #define HD64461_PCC1ISR_P1BVD2 HD64461_PCCISR_BVD2 110 1.1 uch #define HD64461_PCC1ISR_P1BVD1 HD64461_PCCISR_BVD1 111 1.1 uch 112 1.1 uch /* PCC1 General Contorol Register (R/W) */ 113 1.1 uch #define HD64461_PCC1GCR_REG8 0xb0002012 114 1.1 uch #define HD64461_PCC1GCR_P1DRVE HD64461_PCCGCR_DRVE 115 1.1 uch #define HD64461_PCC1GCR_P1PCCR HD64461_PCCGCR_PCCR 116 1.2 uch #define HD64461_PCC1GCR_RESERVED HD64461_PCCGCR_PCCT 117 1.1 uch #define HD64461_PCC1GCR_P1VCC0 HD64461_PCCGCR_VCC0 118 1.1 uch #define HD64461_PCC1GCR_P1MMOD HD64461_PCCGCR_MMOD 119 1.1 uch #define HD64461_PCC1GCR_P1MMOD_16M HD64461_PCCGCR_MMOD_16M 120 1.1 uch #define HD64461_PCC1GCR_P1MMOD_32M HD64461_PCCGCR_MMOD_32M 121 1.1 uch #define HD64461_PCC1GCR_P1PA25 HD64461_PCCGCR_PA25 122 1.1 uch #define HD64461_PCC1GCR_P1PA24 HD64461_PCCGCR_PA24 123 1.1 uch #define HD64461_PCC1GCR_P1REG HD64461_PCCGCR_PREG 124 1.1 uch 125 1.1 uch /* PCC1 Card Status Change Register (R/W) */ 126 1.1 uch #define HD64461_PCC1CSCR_REG8 0xb0002014 127 1.1 uch #define HD64461_PCC1CSCR_P1SCDI HD64461_PCCCSCR_SCDI 128 1.1 uch #define HD64461_PCC1CSCR_P1CDC HD64461_PCCCSCR_CDC 129 1.1 uch #define HD64461_PCC1CSCR_P1RC HD64461_PCCCSCR_RC 130 1.1 uch #define HD64461_PCC1CSCR_P1BW HD64461_PCCCSCR_BW 131 1.1 uch #define HD64461_PCC1CSCR_P1BD HD64461_PCCCSCR_BD 132 1.1 uch 133 1.1 uch /* PCC1 Card Status Change Interrupt Enable Register (R/W) */ 134 1.1 uch #define HD64461_PCC1CSCIER_REG8 0xb0002016 135 1.1 uch #define HD64461_PCC1CSCIER_P1CRE HD64461_PCCCSCIER_CRE 136 1.1 uch #define HD64461_PCC1CSCIER_P1CDE HD64461_PCCCSCIER_CDE 137 1.1 uch #define HD64461_PCC1CSCIER_P1RE HD64461_PCCCSCIER_RE 138 1.1 uch #define HD64461_PCC1CSCIER_P1BWE HD64461_PCCCSCIER_BWE 139 1.1 uch #define HD64461_PCC1CSCIER_P1BDE HD64461_PCCCSCIER_BDE 140 1.1 uch 141 1.1 uch /* PCC1 Software Control Register (R/W) */ 142 1.1 uch #define HD64461_PCC1SCR_REG8 0xb0002018 143 1.1 uch #define HD64461_PCC1SCR_P1VCC1 HD64461_PCCSCR_VCC1 144 1.1 uch #define HD64461_PCC1SCR_P1SWP HD64461_PCCSCR_SWP 145 1.1 uch 146 1.1 uch /* 147 1.1 uch * General Control 148 1.1 uch */ 149 1.1 uch /* PCC0 Output pins Control Register (R/W) */ 150 1.1 uch #define HD64461_PCCP0OCR_REG8 0xb000202a 151 1.1 uch #define HD64461_PCCP0OCR_P0DEPLUP 0x80 152 1.1 uch #define HD64461_PCCP0OCR_P0AEPLUP 0x10 153 1.1 uch 154 1.1 uch /* PCC1 Output pins Control Register (R/W) */ 155 1.1 uch #define HD64461_PCCP1OCR_REG8 0xb000202c 156 1.1 uch #define HD64461_PCCP1OCR_P1RST8MA 0x08 157 1.1 uch #define HD64461_PCCP1OCR_P1RST4MA 0x04 158 1.1 uch #define HD64461_PCCP1OCR_P1RAS8MA 0x02 159 1.1 uch #define HD64461_PCCP1OCR_P1RAS4MA 0x01 160 1.1 uch 161 1.1 uch /* PC Card General Control Register (R/W) */ 162 1.1 uch #define HD64461_PCCPGCR_REG8 0xb000202e 163 1.1 uch #define HD64461_PCCPGCR_PSSDIR 0x02 164 1.1 uch #define HD64461_PCCPGCR_PSSRDWR 0x01 165 1.1 uch 166 1.1 uch /* 167 1.1 uch * common defines. 168 1.1 uch */ 169 1.1 uch #define HD64461_PCC0_REGBASE HD64461_PCC0ISR_REG8 170 1.1 uch #define HD64461_PCC1_REGBASE HD64461_PCC1ISR_REG8 171 1.1 uch #define HD64461_PCC_ISR_OFS 0x0 172 1.1 uch #define HD64461_PCC_GCR_OFS 0x2 173 1.1 uch #define HD64461_PCC_CSCR_OFS 0x4 174 1.1 uch #define HD64461_PCC_CSCIER_OFS 0x6 175 1.1 uch #define HD64461_PCC_SCR_OFS 0x8 176 1.1 uch 177 1.1 uch #define HD64461_PCCISR(x) \ 178 1.1 uch (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 179 1.1 uch HD64461_PCC_ISR_OFS) 180 1.1 uch #define HD64461_PCCGCR(x) \ 181 1.1 uch (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 182 1.1 uch HD64461_PCC_GCR_OFS) 183 1.1 uch #define HD64461_PCCCSCR(x) \ 184 1.1 uch (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 185 1.1 uch HD64461_PCC_CSCR_OFS) 186 1.1 uch #define HD64461_PCCCSCIER(x) \ 187 1.1 uch (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 188 1.1 uch HD64461_PCC_CSCIER_OFS) 189 1.1 uch #define HD64461_PCCSCR(x) \ 190 1.1 uch (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 191 1.1 uch HD64461_PCC_SCR_OFS) 192 1.1 uch 193 1.1 uch #define HD64461_PCCISR_READY 0x80 194 1.1 uch #define HD64461_PCCISR_MWP 0x40 195 1.1 uch #define HD64461_PCCISR_VS2 0x20 196 1.1 uch #define HD64461_PCCISR_VS1 0x10 197 1.1 uch #define HD64461_PCCISR_CD2 0x08 198 1.1 uch #define HD64461_PCCISR_CD1 0x04 199 1.1 uch #define HD64461_PCCISR_BVD2 0x02 200 1.1 uch #define HD64461_PCCISR_BVD1 0x01 201 1.1 uch 202 1.1 uch #define HD64461_PCCGCR_DRVE 0x80 203 1.1 uch #define HD64461_PCCGCR_PCCR 0x40 204 1.2 uch #define HD64461_PCCGCR_PCCT 0x20 205 1.1 uch #define HD64461_PCCGCR_VCC0 0x10 206 1.1 uch #define HD64461_PCCGCR_MMOD 0x08 207 1.1 uch #define HD64461_PCCGCR_MMOD_16M 0x08 208 1.1 uch #define HD64461_PCCGCR_MMOD_32M 0x00 209 1.1 uch #define HD64461_PCCGCR_PA25 0x04 210 1.1 uch #define HD64461_PCCGCR_PA24 0x02 211 1.1 uch #define HD64461_PCCGCR_PREG 0x01 212 1.1 uch 213 1.1 uch #define HD64461_PCCCSCR_SCDI 0x80 214 1.1 uch #define HD64461_PCCCSCR_CDC 0x08 215 1.1 uch #define HD64461_PCCCSCR_RC 0x04 216 1.1 uch #define HD64461_PCCCSCR_BW 0x02 217 1.1 uch #define HD64461_PCCCSCR_BD 0x01 218 1.1 uch 219 1.1 uch #define HD64461_PCCCSCIER_CRE 0x80 220 1.1 uch #define HD64461_PCCCSCIER_CDE 0x08 221 1.1 uch #define HD64461_PCCCSCIER_RE 0x04 222 1.1 uch #define HD64461_PCCCSCIER_BWE 0x02 223 1.1 uch #define HD64461_PCCCSCIER_BDE 0x01 224 1.1 uch 225 1.1 uch #define HD64461_PCCSCR_VCC1 0x02 226 1.1 uch #define HD64461_PCCSCR_SWP 0x01 227 1.3 uwe 228 1.3 uwe #endif /* !_HPCSH_DEV_HD64461PCMCIAREG_H_ */ 229
Indexes created Tue Oct 28 12:10:06 GMT 2025