hd64461pcmciareg.h revision 1.2
1 /* $NetBSD: hd64461pcmciareg.h,v 1.2 2001/10/08 15:34:24 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * PCC0 SH7709 Area 6 (memory and I/O card) 41 */ 42 /* PCC0 Interface Status Register (R) */ 43 #define HD64461_PCC0ISR_REG8 0xb0002000 44 #define HD64461_PCC0ISR_P0READY HD64461_PCCISR_READY 45 #define HD64461_PCC0ISR_IREQ HD64461_PCCISR_READY 46 #define HD64461_PCC0ISR_P0MWP HD64461_PCCISR_MWP 47 #define HD64461_PCC0ISR_P0VS2 HD64461_PCCISR_VS2 48 #define HD64461_PCC0ISR_P0VS1 HD64461_PCCISR_VS1 49 #define HD64461_PCC0ISR_P0CD2 HD64461_PCCISR_CD2 50 #define HD64461_PCC0ISR_P0CD1 HD64461_PCCISR_CD1 51 #define HD64461_PCC0ISR_P0BVD2 HD64461_PCCISR_BVD2 52 #define HD64461_PCC0ISR_SPKR0 HD64461_PCCISR_BVD2 53 #define HD64461_PCC0ISR_P0BVD1 HD64461_PCCISR_BVD1 54 #define HD64461_PCC0ISR_STSCHG0 HD64461_PCCISR_BVD1 55 56 /* PCC0 General Contorol Register (R/W) */ 57 #define HD64461_PCC0GCR_REG8 0xb0002002 58 #define HD64461_PCC0GCR_P0DRVE HD64461_PCCGCR_DRVE 59 #define HD64461_PCC0GCR_P0PCCR HD64461_PCCGCR_PCCR 60 #define HD64461_PCC0GCR_P0PCCT HD64461_PCCGCR_PCCT 61 #define HD64461_PCC0GCR_P0VCC0 HD64461_PCCGCR_VCC0 62 #define HD64461_PCC0GCR_P0MMOD HD64461_PCCGCR_MMOD 63 #define HD64461_PCC0GCR_P0MMOD_16M HD64461_PCCGCR_MMOD_16M 64 #define HD64461_PCC0GCR_P0MMOD_32M HD64461_PCCGCR_MMOD_32M 65 /* these bits meaning different for P0MMOD mode */ 66 #define HD64461_PCC0GCR_P0PA25 HD64461_PCCGCR_PA25 67 #define HD64461_PCC0GCR_P0PA24 HD64461_PCCGCR_PA24 68 #define HD64461_PCC0GCR_P0REG HD64461_PCCGCR_PREG 69 70 /* PCC0 Card Status Change Register (R/W) */ 71 #define HD64461_PCC0CSCR_REG8 0xb0002004 72 #define HD64461_PCC0CSCR_P0SCDI HD64461_PCCCSCR_SCDI 73 #define HD64461_PCC0CSCR_P0IREQ 0x20 74 #define HD64461_PCC0CSCR_P0SC 0x10 75 #define HD64461_PCC0CSCR_P0CDC HD64461_PCCCSCR_CDC 76 #define HD64461_PCC0CSCR_P0RC HD64461_PCCCSCR_RC 77 #define HD64461_PCC0CSCR_P0BW HD64461_PCCCSCR_BW 78 #define HD64461_PCC0CSCR_P0BD HD64461_PCCCSCR_BD 79 80 /* PCC0 Card Status Change Interrupt Enable Register (R/W) */ 81 #define HD64461_PCC0CSCIER_REG8 0xb0002006 82 #define HD64461_PCC0CSCIER_P0CRE HD64461_PCCCSCIER_CRE 83 84 #define HD64461_PCC0CSCIER_P0IREQE_MASK 0x60 85 #define HD64461_PCC0CSCIER_P0IREQE_NONE 0x00 86 #define HD64461_PCC0CSCIER_P0IREQE_LEVEL 0x20 87 #define HD64461_PCC0CSCIER_P0IREQE_FEDGE 0x40 88 #define HD64461_PCC0CSCIER_P0IREQE_REDGE 0x60 89 90 #define HD64461_PCC0CSCIER_P0SCE 0x10 91 #define HD64461_PCC0CSCIER_P0CDE HD64461_PCCCSCIER_CDE 92 #define HD64461_PCC0CSCIER_P0RE HD64461_PCCCSCIER_RE 93 #define HD64461_PCC0CSCIER_P0BWE HD64461_PCCCSCIER_BWE 94 #define HD64461_PCC0CSCIER_P0BDE HD64461_PCCCSCIER_BDE 95 96 /* PCC0 Software Control Register (R/W) */ 97 #define HD64461_PCC0SCR_REG8 0xb0002008 98 #define HD64461_PCC0SCR_P0VCC1 HD64461_PCCSCR_VCC1 99 #define HD64461_PCC0SCR_P0SWP HD64461_PCCSCR_SWP 100 101 /* 102 * PCC1 SH7709 Area 5 (memory card only) 103 */ 104 /* PCC1 Interface Status Register (R) */ 105 #define HD64461_PCC1ISR_REG8 0xb0002010 106 #define HD64461_PCC1ISR_P1READY HD64461_PCCISR_READY 107 #define HD64461_PCC1ISR_P1MWP HD64461_PCCISR_MWP 108 #define HD64461_PCC1ISR_P1VS2 HD64461_PCCISR_VS2 109 #define HD64461_PCC1ISR_P1VS1 HD64461_PCCISR_VS1 110 #define HD64461_PCC1ISR_P1CD2 HD64461_PCCISR_CD2 111 #define HD64461_PCC1ISR_P1CD1 HD64461_PCCISR_CD1 112 #define HD64461_PCC1ISR_P1BVD2 HD64461_PCCISR_BVD2 113 #define HD64461_PCC1ISR_P1BVD1 HD64461_PCCISR_BVD1 114 115 /* PCC1 General Contorol Register (R/W) */ 116 #define HD64461_PCC1GCR_REG8 0xb0002012 117 #define HD64461_PCC1GCR_P1DRVE HD64461_PCCGCR_DRVE 118 #define HD64461_PCC1GCR_P1PCCR HD64461_PCCGCR_PCCR 119 #define HD64461_PCC1GCR_RESERVED HD64461_PCCGCR_PCCT 120 #define HD64461_PCC1GCR_P1VCC0 HD64461_PCCGCR_VCC0 121 #define HD64461_PCC1GCR_P1MMOD HD64461_PCCGCR_MMOD 122 #define HD64461_PCC1GCR_P1MMOD_16M HD64461_PCCGCR_MMOD_16M 123 #define HD64461_PCC1GCR_P1MMOD_32M HD64461_PCCGCR_MMOD_32M 124 #define HD64461_PCC1GCR_P1PA25 HD64461_PCCGCR_PA25 125 #define HD64461_PCC1GCR_P1PA24 HD64461_PCCGCR_PA24 126 #define HD64461_PCC1GCR_P1REG HD64461_PCCGCR_PREG 127 128 /* PCC1 Card Status Change Register (R/W) */ 129 #define HD64461_PCC1CSCR_REG8 0xb0002014 130 #define HD64461_PCC1CSCR_P1SCDI HD64461_PCCCSCR_SCDI 131 #define HD64461_PCC1CSCR_P1CDC HD64461_PCCCSCR_CDC 132 #define HD64461_PCC1CSCR_P1RC HD64461_PCCCSCR_RC 133 #define HD64461_PCC1CSCR_P1BW HD64461_PCCCSCR_BW 134 #define HD64461_PCC1CSCR_P1BD HD64461_PCCCSCR_BD 135 136 /* PCC1 Card Status Change Interrupt Enable Register (R/W) */ 137 #define HD64461_PCC1CSCIER_REG8 0xb0002016 138 #define HD64461_PCC1CSCIER_P1CRE HD64461_PCCCSCIER_CRE 139 #define HD64461_PCC1CSCIER_P1CDE HD64461_PCCCSCIER_CDE 140 #define HD64461_PCC1CSCIER_P1RE HD64461_PCCCSCIER_RE 141 #define HD64461_PCC1CSCIER_P1BWE HD64461_PCCCSCIER_BWE 142 #define HD64461_PCC1CSCIER_P1BDE HD64461_PCCCSCIER_BDE 143 144 /* PCC1 Software Control Register (R/W) */ 145 #define HD64461_PCC1SCR_REG8 0xb0002018 146 #define HD64461_PCC1SCR_P1VCC1 HD64461_PCCSCR_VCC1 147 #define HD64461_PCC1SCR_P1SWP HD64461_PCCSCR_SWP 148 149 /* 150 * General Control 151 */ 152 /* PCC0 Output pins Control Register (R/W) */ 153 #define HD64461_PCCP0OCR_REG8 0xb000202a 154 #define HD64461_PCCP0OCR_P0DEPLUP 0x80 155 #define HD64461_PCCP0OCR_P0AEPLUP 0x10 156 157 /* PCC1 Output pins Control Register (R/W) */ 158 #define HD64461_PCCP1OCR_REG8 0xb000202c 159 #define HD64461_PCCP1OCR_P1RST8MA 0x08 160 #define HD64461_PCCP1OCR_P1RST4MA 0x04 161 #define HD64461_PCCP1OCR_P1RAS8MA 0x02 162 #define HD64461_PCCP1OCR_P1RAS4MA 0x01 163 164 /* PC Card General Control Register (R/W) */ 165 #define HD64461_PCCPGCR_REG8 0xb000202e 166 #define HD64461_PCCPGCR_PSSDIR 0x02 167 #define HD64461_PCCPGCR_PSSRDWR 0x01 168 169 /* 170 * common defines. 171 */ 172 #define HD64461_PCC0_REGBASE HD64461_PCC0ISR_REG8 173 #define HD64461_PCC1_REGBASE HD64461_PCC1ISR_REG8 174 #define HD64461_PCC_ISR_OFS 0x0 175 #define HD64461_PCC_GCR_OFS 0x2 176 #define HD64461_PCC_CSCR_OFS 0x4 177 #define HD64461_PCC_CSCIER_OFS 0x6 178 #define HD64461_PCC_SCR_OFS 0x8 179 180 #define HD64461_PCCISR(x) \ 181 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 182 HD64461_PCC_ISR_OFS) 183 #define HD64461_PCCGCR(x) \ 184 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 185 HD64461_PCC_GCR_OFS) 186 #define HD64461_PCCCSCR(x) \ 187 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 188 HD64461_PCC_CSCR_OFS) 189 #define HD64461_PCCCSCIER(x) \ 190 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 191 HD64461_PCC_CSCIER_OFS) 192 #define HD64461_PCCSCR(x) \ 193 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 194 HD64461_PCC_SCR_OFS) 195 196 #define HD64461_PCCISR_READY 0x80 197 #define HD64461_PCCISR_MWP 0x40 198 #define HD64461_PCCISR_VS2 0x20 199 #define HD64461_PCCISR_VS1 0x10 200 #define HD64461_PCCISR_CD2 0x08 201 #define HD64461_PCCISR_CD1 0x04 202 #define HD64461_PCCISR_BVD2 0x02 203 #define HD64461_PCCISR_BVD1 0x01 204 205 #define HD64461_PCCGCR_DRVE 0x80 206 #define HD64461_PCCGCR_PCCR 0x40 207 #define HD64461_PCCGCR_PCCT 0x20 208 #define HD64461_PCCGCR_VCC0 0x10 209 #define HD64461_PCCGCR_MMOD 0x08 210 #define HD64461_PCCGCR_MMOD_16M 0x08 211 #define HD64461_PCCGCR_MMOD_32M 0x00 212 #define HD64461_PCCGCR_PA25 0x04 213 #define HD64461_PCCGCR_PA24 0x02 214 #define HD64461_PCCGCR_PREG 0x01 215 216 #define HD64461_PCCCSCR_SCDI 0x80 217 #define HD64461_PCCCSCR_CDC 0x08 218 #define HD64461_PCCCSCR_RC 0x04 219 #define HD64461_PCCCSCR_BW 0x02 220 #define HD64461_PCCCSCR_BD 0x01 221 222 #define HD64461_PCCCSCIER_CRE 0x80 223 #define HD64461_PCCCSCIER_CDE 0x08 224 #define HD64461_PCCCSCIER_RE 0x04 225 #define HD64461_PCCCSCIER_BWE 0x02 226 #define HD64461_PCCCSCIER_BDE 0x01 227 228 #define HD64461_PCCSCR_VCC1 0x02 229 #define HD64461_PCCSCR_SWP 0x01 230
Indexes created Wed Oct 01 07:09:59 GMT 2025