hd64461videoreg.h revision 1.1
1 /* $NetBSD: hd64461videoreg.h,v 1.1 2001/06/04 17:08:36 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * LCD Controller Control Register 41 */ 42 /* Base Address Register */ 43 #define HD64461_LCDCBAR_REG16 0xb0001000 44 #define HD64461_LCDCBAR_MASK 0x3fff 45 #define HD64461_LCDCBAR_SHIFT 12 46 #define HD64461_LCDCBAR_BASEADDR(x) \ 47 (((x) & HD64461_LCDCBAR_MASK) << HD64461_LCDCBAR_SHIFT) 48 49 /* Line Address Offset Register */ 50 #define HD64461_LCDCLOR_REG16 0xb0001002 51 #define HD64461_LCDCLOR_MASK 0x07ff 52 #define HD64461_LCDCLOR(x) ((x) & HD64461_LCDCLOR_MASK) 53 54 /* LCDC Control Register */ 55 #define HD64461_LCDCCR_REG16 0xb0001004 56 #define HD64461_LCDCCR_STBAK 0x0400 57 #define HD64461_LCDCCR_STREQ 0x0100 58 #define HD64461_LCDCCR_MOFF 0x0080 59 #define HD64461_LCDCCR_REFSEL 0x0040 60 #define HD64461_LCDCCR_EPON 0x0020 61 #define HD64461_LCDCCR_SPON 0x0010 62 #define HD64461_LCDCCR_DSPSEL_MASK 0x7 63 #define HD64461_LCDCCR_DSPSEL(x) ((x) & HD64461_LCDCCR_DSPSEL_MASK) 64 #define HD64461_LCDCCR_DSPSEL_LCD_CRT 0x4 65 #define HD64461_LCDCCR_DSPSEL_CRT 0x2 66 #define HD64461_LCDCCR_DSPSEL_LCD 0x1 67 68 /* LCD Display Register */ 69 /* 1 */ 70 #define HD64461_LCDLDR1_REG16 0xb0001010 71 #define HD64461_LCDLDR1_DINV 0x0100 72 #define HD64461_LCDLDR1_DON 0x0001 73 /* 2 */ 74 #define HD64461_LCDLDR2_REG16 0xb0001012 75 #define HD64461_LCDLDR2_CC1 0x0080 76 #define HD64461_LCDLDR2_CC2 0x0040 77 #define HD64461_LCDLDR2_LM_MASK 0x7 78 #define HD64461_LCDLDR2_LM(x) ((x) & HD64461_LCDLDR2_LM_MASK) 79 #define HD64461_LCDLDR2_LM_COLOR 0x4 80 #define HD64461_LCDLDR2_LM_GRAY8 0x1 81 #define HD64461_LCDLDR2_LM_GRAY4 0x0 82 /* 3 */ 83 #define HD64461_LCDLDR3_REG16 0xb000101e 84 #define HD64461_LCDLDR3_CS_SHIFT 5 85 #define HD64461_LCDLDR3_CS_MASK 0x1f 86 #define HD64461_LCDLDR3_CS(cr) \ 87 (((cr) >> HD64461_LCDLDR3_CS_SHIFT) & \ 88 HD64461_LCDLDR3_CS_MASK) 89 #define HD64461_LCDLDR3_CS_SET(cr, val) \ 90 ((cr) | (((val) << HD64461_LCDLDR3_CS_SHIFT) & \ 91 (HD64461_LCDLDR3_CS_MASK << HD64461_LCDLDR3_CS_SHIFT))) 92 #define HD64461_LCDLDR3_CG_MASK 0xf 93 #define HD64461_LCDLDR3_CG(cr) \ 94 ((cr) & HD64461_LCDLDR3_CG_MASK) 95 #define HD64461_LCDLDR3_CG_CLR(cr) \ 96 ((cr) & ~HD64461_LCDLDR3_CG_MASK) 97 #define HD64461_LCDLDR3_CG_SET(cr, val) \ 98 ((cr) | ((val) & HD64461_LCDLDR3_CG_MASK)) 99 100 /* 101 * select CL2 frequency 102 * 0x0 15 MHz (color) 15/2 (monochrome) 103 * 0x1 2.5 MHz 104 * 0x2 3.75 Mhz 105 * 0x4 5 Mhz 106 * 0x8 7.5 Mhz 107 * 0x10 10 Mhz 108 */ 109 #define HD64461_LCDLDR3_CG_COLOR16 0x8 110 #define HD64461_LCDLDR3_CG_COLOR8 0x4 111 #define HD64461_LCDLDR3_CG_GRAY6 0x3 112 #define HD64461_LCDLDR3_CG_GRAY4 0x2 113 #define HD64461_LCDLDR3_CG_GRAY2 0x1 114 #define HD64461_LCDLDR3_CG_GRAY1 0x0 115 116 /* LCD Number of Characters in Horizontal Register */ 117 #define HD64461_LCDLDHNCR_REG16 0xb0001014 118 #define HD64461_LCDLDHNCR_NHD_SHIFT 8 119 #define HD64461_LCDLDHNCR_NHD_MASK 0xff 120 #define HD64461_LCDLDHNCR_NHD(cr) \ 121 (((cr) >> HD64461_LCDLDHNCR_NHD_SHIFT) & \ 122 HD64461_LCDLDHNCR_NHD_MASK) 123 #define HD64461_LCDLDHNCR_NHD_SET(cr, val) \ 124 ((cr) | (((val) << HD64461_LCDLDHNCR_NHD_SHIFT) & \ 125 (HD64461_LCDLDHNCR_NHD_MASK << HD64461_LCDLDHNCR_NHD_SHIFT))) 126 #define HD64461_LCDLDHNCR_NHT_SHIFT 0 127 #define HD64461_LCDLDHNCR_NHT_MASK 0xff 128 #define HD64461_LCDLDHNCR_NHT(cr) \ 129 (((cr) >> HD64461_LCDLDHNCR_NHT_SHIFT) & \ 130 HD64461_LCDLDHNCR_NHT_MASK) 131 #define HD64461_LCDLDHNCR_NHT_SET(cr, val) \ 132 ((cr) | (((val) << HD64461_LCDLDHNCR_NHT_SHIFT) & \ 133 (HD64461_LCDLDHNCR_NHT_MASK << HD64461_LCDLDHNCR_NHT_SHIFT))) 134 135 /* Start Position of Horizontal Register */ 136 #define HD64461_LCDLDHNSR_REG16 0xb0001016 137 #define HD64461_LCDLDHNSR_HSW_SHIFT 8 138 #define HD64461_LCDLDHNSR_HSW_MASK 0xf 139 #define HD64461_LCDLDHNSR_HSW(cr) \ 140 (((cr) >> HD64461_LCDLDHNSR_HSW_SHIFT) & \ 141 HD64461_LCDLDHNSR_HSW_MASK) 142 #define HD64461_LCDLDHNSR_HSW_SET(cr, val) \ 143 ((cr) | (((val) << HD64461_LCDLDHNSR_HSW_SHIFT) & \ 144 (HD64461_LCDLDHNSR_HSW_MASK << HD64461_LCDLDHNSR_HSW_SHIFT))) 145 #define HD64461_LCDLDHNSR_HSP_SHIFT 0 146 #define HD64461_LCDLDHNSR_HSP_MASK 0xff 147 #define HD64461_LCDLDHNSR_HSP(cr) \ 148 (((cr) >> HD64461_LCDLDHNSR_HSP_SHIFT) & \ 149 HD64461_LCDLDHNSR_HSP_MASK) 150 #define HD64461_LCDLDHNSR_HSP_SET(cr, val) \ 151 ((cr) | (((val) << HD64461_LCDLDHNSR_HSP_SHIFT) & \ 152 (HD64461_LCDLDHNSR_HSP_MASK << HD64461_LCDLDHNSR_HSP_SHIFT))) 153 154 /* Total Vertical Lines Register */ 155 #define HD64461_LCDLDVNTR_REG16 0xb0001018 156 #define HD64461_LCDLDVNTR_VTL_SHIFT 0 157 #define HD64461_LCDLDVNTR_VTL_MASK 0x3ff 158 #define HD64461_LCDLDVNTR_VTL(cr) \ 159 (((cr) >> HD64461_LCDLDVNTR_VTL_SHIFT) & \ 160 HD64461_LCDLDVNTR_VTL_MASK) 161 #define HD64461_LCDLDVNTR_VTL_SET(cr, val) \ 162 ((cr) | (((val) << HD64461_LCDLDVNTR_VTL_SHIFT) & \ 163 (HD64461_LCDLDVNTR_VTL_MASK << HD64461_LCDLDVNTR_VTL_SHIFT))) 164 165 /* Display Vertical Lines Register */ 166 #define HD64461_LCDLDVNDR_REG16 0xb000101a 167 #define HD64461_LCDLDVNDR_VDL_SHIFT 0 168 #define HD64461_LCDLDVNDR_VDL_MASK 0x3ff 169 #define HD64461_LCDLDVNDR_VDL(cr) \ 170 (((cr) >> HD64461_LCDLDVNDR_VDL_SHIFT) & \ 171 HD64461_LCDLDVNDR_VDL_MASK) 172 #define HD64461_LCDLDVNDR_VDL_SET(cr, val) \ 173 ((cr) | (((val) << HD64461_LCDLDVNDR_VDL_SHIFT) & \ 174 (HD64461_LCDLDVNDR_VDL_MASK << HD64461_LCDLDVNDR_VDL_SHIFT))) 175 176 /* Vertical Synchronization Position Register */ 177 #define HD64461_LCDLDVSPR_REG16 0xb000101c 178 #define HD64461_LCDLDVSPR_VSP_SHIFT 0 179 #define HD64461_LCDLDVSPR_VSP_MASK 0x3ff 180 #define HD64461_LCDLDVSPR_VSP(cr) \ 181 ((cr) & HD64461_LCDLDVSPR_VSP_MASK) 182 #define HD64461_LCDLDVSPR_VSP_SET(cr, val) \ 183 ((cr) | ((val) & HD64461_LCDLDVSPR_VSP_MASK)) 184 185 /* 186 * CRT Control Register 187 */ 188 /* CRTC Total Vertical Lines Register */ 189 #define HD64461_LCDCRTVTR_REG16 0xb0001020 190 #define HD64461_LCDCRTVTR_SHIFT 0 191 #define HD64461_LCDCRTVTR_MASK 0x3ff 192 #define HD64461_LCDCRTVTR(cr) \ 193 (((cr) >> HD64461_LCDCRTVTR_SHIFT) & \ 194 HD64461_LCDCRTVTR_MASK) 195 #define HD64461_LCDCRTVTR_SET(cr, val) \ 196 ((cr) | (((val) << HD64461_LCDCRTVTR_SHIFT) & \ 197 (HD64461_LCDCRTVTR_MASK << HD64461_LCDCRTVTR_SHIFT))) 198 199 /* CRTC Vertical Retrace Start Register */ 200 #define HD64461_LCDCRTVRSR_REG16 0xb0001022 201 #define HD64461_LCDCRTVRSR_SHIFT 0 202 #define HD64461_LCDCRTVRSR_MASK 0x3ff 203 #define HD64461_LCDCRTVRSR(cr) \ 204 (((cr) >> HD64461_LCDCRTVRSR_SHIFT) & \ 205 HD64461_LCDCRTVRSR_MASK) 206 #define HD64461_LCDCRTVRSR_SET(cr, val) \ 207 ((cr) | (((val) << HD64461_LCDCRTVRSR_SHIFT) & \ 208 (HD64461_LCDCRTVRSR_MASK << HD64461_LCDCRTVRSR_SHIFT))) 209 210 /* CRTC Vertical Retrace End Register */ 211 #define HD64461_LCDCRTVRER_REG16 0xb0001024 212 #define HD64461_LCDCRTVRER_SHIFT 0 213 #define HD64461_LCDCRTVRER_MASK 0xf 214 #define HD64461_LCDCRTVRER(cr) \ 215 (((cr) >> HD64461_LCDCRTVRER_SHIFT) & HD64461_LCDCRTVRER_MASK) 216 217 #define HD64461_LCDCRTVRER_SET(cr, val) \ 218 ((cr) | (((val) << HD64461_LCDCRTVRER_SHIFT) & \ 219 (HD64461_LCDCRTVRER_MASK << HD64461_LCDCRTVRER_SHIFT))) 220 221 /* 222 * Palette Register 223 */ 224 /* Color Palette Write Address Register */ 225 #define HD64461_LCDCPTWAR_REG16 0xb0001030 226 #define HD64461_LCDCPTWAR_SHIFT 8 227 #define HD64461_LCDCPTWAR_MASK 0xff 228 #define HD64461_LCDCPTWAR_SET(cr, val) \ 229 ((cr) | (((val) << HD64461_LCDCPTWAR_SHIFT) & \ 230 (HD64461_LCDCPTWAR_MASK << HD64461_LCDCPTWAR_SHIFT))) 231 232 /* Color Palette Write Data Register */ 233 #define HD64461_LCDCPTWDR_REG16 0xb0001032 234 #define HD64461_LCDCPTWDR_SHIFT 0 235 #define HD64461_LCDCPTWDR_MASK 0x3f 236 #define HD64461_LCDCPTWDR_SET(cr, val) \ 237 ((cr) | ((val) & HD64461_LCDCPTWDR_MASK)) 238 239 /* Color Palette READ Address Register */ 240 #define HD64461_LCDCPTRAR_REG16 0xb0001034 241 #define HD64461_LCDCPTRAR_SHIFT 8 242 #define HD64461_LCDCPTRAR_MASK 0xff 243 #define HD64461_LCDCPTRAR_SET(cr, val) \ 244 ((cr) | (((val) << HD64461_LCDCPTRAR_SHIFT) & \ 245 (HD64461_LCDCPTRAR_MASK << HD64461_LCDCPTRAR_SHIFT))) 246 247 /* Color Palette READ Data Register */ 248 #define HD64461_LCDCPTRDR_REG16 0xb0001036 249 #define HD64461_LCDCPTRDR_SHIFT 0 250 #define HD64461_LCDCPTRDR_MASK 0x3f 251 #define HD64461_LCDCPTRDR(cr) ((cr) & HD64461_LCDCPTRDR_MASK) 252 253 /* 254 * Acceleration Common Register 255 */ 256 /* Display Resolution Offset Register */ 257 #define HD64461_LCDGRDOR_REG16 0xb0001040 258 #define HD64461_LCDGRDOR_SHIFT 0 259 #define HD64461_LCDGRDOR_MASK 0x7ff 260 #define HD64461_LCDGRDOR(cr) \ 261 (((cr) >> HD64461_LCDGRDOR_SHIFT) & \ 262 HD64461_LCDGRDOR_MASK) 263 #define HD64461_LCDGRDOR_SET(cr, val) \ 264 ((cr) | (((val) << HD64461_LCDGRDOR_SHIFT) & \ 265 (HD64461_LCDGRDOR_MASK << HD64461_LCDGRDOR_SHIFT))) 266 267 /* Solid Color Register */ 268 #define HD64461_LCDGRSCR_REG16 0xb0001042 269 270 /* Accelerator Configuration Register */ 271 #define HD64461_LCDGRCFGR_REG16 0xb0001044 272 #define HD64461_LCDGRCFGR_ACCSTATUS 0x0010 273 #define HD64461_LCDGRCFGR_ACCRESET 0x0008 274 #define HD64461_LCDGRCFGR_ACCSTART_MASK 0x6 275 #define HD64461_LCDGRCFGR_ACCSTART_BITBLT 0x0006 276 #define HD64461_LCDGRCFGR_ACCSTART_LINE 0x0004 277 #define HD64461_LCDGRCFGR_ACCSTART_OFF 0x0000 278 #define HD64461_LCDGRCFGR_COLORDEPTH_8BPP 0x0001 279 280 /* 281 * Line Drawing Register 282 */ 283 /* Line Start Address Register */ 284 #define HD64461_LCDLNSARH_REG16 0xb0001046 285 #define HD64461_LCDLNSARH_MASK 0x0007 286 #define HD64461_LCDLNSARL_REG16 0xb0001048 287 #define HD64461_LCDLNSARL_MASK 0xffff 288 289 /* Axis Pixel Length Register */ 290 #define HD64461_LCDLNAXLR_REG16 0xb000104a 291 #define HD64461_LCDLNAXLR_MASK 0x07ff 292 293 /* Diagonal Regsiter */ 294 #define HD64461_LCDLNDGR_REG16 0xb000104c 295 #define HD64461_LCDLNDGR_LNDGR_SIGN 0x8000 296 #define HD64461_LCDLNDGR_LNDGR_MASK 0x07ff 297 #define HD64461_LCDLNDGR_LNDGR_SET(cr, x) \ 298 ((cr) | ((x) & HD64461_LCDLNDGR_LNDGR_MASK)) 299 300 /* Axial Register */ 301 #define HD64461_LCDLNAXR_REG16 0xb000104e 302 #define HD64461_LCDLNAXR_LNAXR_MASK 0x0fff 303 #define HD64461_LCDLNAXR_LNAXR_SET(cr, x) \ 304 ((cr) | ((x) & HD64461_LCDLNAXR_LNAXR_MASK)) 305 306 /* Start Error Term Register */ 307 #define HD64461_LCDLNERTR_REG16 0xb0001050 308 #define HD64461_LCDLNERTR_LNERTR_SIGN 0x8000 309 #define HD64461_LCDLNERTR_LNERTR_MASK 0x07ff 310 #define HD64461_LCDLNERTR_LNERTR_SET(cr, x) \ 311 ((cr) | ((x) & HD64461_LCDLNERTR_LNERTR_MASK)) 312 313 /* Line Mode Register */ 314 #define HD64461_LCDLNMDR_REG16 0xb0001052 315 #define HD64461_LCDLNMDR_MASK 0x0003 316 /* 317 * 2 1 318 * 3 0 319 * 4 7 320 * 5 6 321 * 322 * 1 or 5 ... 3 323 * 2 or 6 ... 2 324 * 0 or 4 ... 1 325 * 3 or 7 ... 0 326 */ 327 328 /* 329 * BitBLT Register 330 */ 331 /* Source Start Address Register (19 bit) */ 332 #define HD64461_LCDBBTSSARH_REG16 0xb0001054 333 #define HD64461_LCDBBTSSARH_SHIFT 16 334 #define HD64461_LCDBBTSSARH_MASK 0x0007 335 #define HD64461_LCDBBTSSARL_REG16 0xb0001056 336 #define HD64461_LCDBBTSSARL_MASK 0xffff 337 #define HD64461_LCDBBTSSARH(x) \ 338 (((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK) 339 #define HD64461_LCDBBTSSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK) 340 341 /* Destination Start Address Register (19 bit) */ 342 #define HD64461_LCDBBTDSARH_REG16 0xb0001058 343 #define HD64461_LCDBBTDSARH_SHIFT 16 344 #define HD64461_LCDBBTDSARH_MASK 0x0007 345 #define HD64461_LCDBBTDSARL_REG16 0xb000105a 346 #define HD64461_LCDBBTDSARL_MASK 0xffff 347 #define HD64461_LCDBBTDSARH(x) \ 348 (((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK) 349 #define HD64461_LCDBBTDSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK) 350 351 /* Destination Block Width Register */ 352 #define HD64461_LCDBBTDWR_REG16 0xb000105c 353 #define HD64461_LCDBBTDWR_MASK 0x07ff 354 355 /* Destination Block Height Register */ 356 #define HD64461_LCDBBTDHR_REG16 0xb000105e 357 #define HD64461_LCDBBTDHR_MASK 0x07ff 358 359 /* Pattern Start Address Register (19 bit) */ 360 #define HD64461_LCDBBTPARH_REG16 0xb0001060 361 #define HD64461_LCDBBTPARH_MASK 0x0007 362 #define HD64461_LCDBBTPARL_REG16 0xb0001062 363 364 /* Mask Start Address Register (19 bit) */ 365 #define HD64461_LCDBBTMARH_REG16 0xb0001064 366 #define HD64461_LCDBBTMARH_MASK 0x0007 367 #define HD64461_LCDBBTMARL_REG16 0xb0001066 368 369 /* ROP Register */ 370 #define HD64461_LCDBBTROPR_REG16 0xb0001068 371 372 /* BitBLT Mode Register */ 373 #define HD64461_LCDBBTMDR_REG16 0xb000106a 374 #define HD64461_LCDBBTMDR_MASKENABLE 0x0020 375 #define HD64461_LCDBBTMDR_PATSELECT_SOLIDCOLOR 0x0010 376 #define HD64461_LCDBBTMDR_SHIFT 2 377 #define HD64461_LCDBBTMDR_MASK 0x3 378 #define HD64461_LCDBBTMDR(cr) \ 379 (((cr) >> HD64461_LCDBBTMDR_SHIFT) & HD64461_LCDBBTMDR_MASK) 380 381 #define HD64461_LCDBBTMDR_SET(cr, val) \ 382 ((cr) | (((val) << HD64461_LCDBBTMDR_SHIFT) & \ 383 (HD64461_LCDBBTMDR_MASK << HD64461_LCDBBTMDR_SHIFT))) 384 #define HD64461_LCDBBTMDR_ON_SCREEN_TO_ON_SCREEN 0 385 #define HD64461_LCDBBTMDR_ON_SCREEN_TO_OFF_SCREEN 1 386 #define HD64461_LCDBBTMDR_OFF_SCREEN_TO_ON_SCREEN 3 387 388 #define HD64461_LCDBBTMDR_SCANDRCT 0x0001 389 #define HD64461_LCDBBTMDR_SCANDRCT_RL_BT 0x1 390 #define HD64461_LCDBBTMDR_SCANDRCT_LR_TB 0x0 391 392 /* 393 * BitBLT Function 394 */ 395 #define HD64461_LCDC_BITBLT_SRCAND 0x0088 396 #define HD64461_LCDC_BITBLT_SRCCOPY 0x00cc 397 #define HD64461_LCDC_BITBLT_SRCINVERT 0x0066 398 #define HD64461_LCDC_BITBLT_SRCPAINT 0x00ee 399 #define HD64461_LCDC_BITBLT_PATCOPY 0x00f0 400 #define HD64461_LCDC_BITBLT_PATINVERT 0x005a 401 #define HD64461_LCDC_BITBLT_DSTINVERT 0x0055 402 #define HD64461_LCDC_BITBLT_BLACKNESS 0x0000 403 #define HD64461_LCDC_BITBLT_WHITENESS 0x00ff 404 #define HD64461_LCDC_BITBLT_MASKEDSRCCOPY 0xccaa 405
Indexes created Tue Sep 30 17:09:57 GMT 2025