hd64461videoreg.h revision 1.2
1 /* $NetBSD: hd64461videoreg.h,v 1.2 2005/12/18 21:47:10 uwe Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _HPCSH_DEV_HD64461VIDEOREG_H_ 40 #define _HPCSH_DEV_HD64461VIDEOREG_H_ 41 42 /* 43 * LCD Controller Control Register 44 */ 45 46 /* Base Address Register */ 47 #define HD64461_LCDCBAR_REG16 0xb0001000 48 #define HD64461_LCDCBAR_MASK 0x3fff 49 #define HD64461_LCDCBAR_SHIFT 12 50 #define HD64461_LCDCBAR_BASEADDR(x) \ 51 (((x) & HD64461_LCDCBAR_MASK) << HD64461_LCDCBAR_SHIFT) 52 53 /* Line Address Offset Register */ 54 #define HD64461_LCDCLOR_REG16 0xb0001002 55 #define HD64461_LCDCLOR_MASK 0x07ff 56 #define HD64461_LCDCLOR(x) ((x) & HD64461_LCDCLOR_MASK) 57 58 /* LCDC Control Register */ 59 #define HD64461_LCDCCR_REG16 0xb0001004 60 #define HD64461_LCDCCR_STBAK 0x0400 61 #define HD64461_LCDCCR_STREQ 0x0100 62 #define HD64461_LCDCCR_MOFF 0x0080 63 #define HD64461_LCDCCR_REFSEL 0x0040 64 #define HD64461_LCDCCR_EPON 0x0020 65 #define HD64461_LCDCCR_SPON 0x0010 66 #define HD64461_LCDCCR_DSPSEL_MASK 0x7 67 #define HD64461_LCDCCR_DSPSEL(x) ((x) & HD64461_LCDCCR_DSPSEL_MASK) 68 #define HD64461_LCDCCR_DSPSEL_LCD_CRT 0x4 69 #define HD64461_LCDCCR_DSPSEL_CRT 0x2 70 #define HD64461_LCDCCR_DSPSEL_LCD 0x1 71 72 /* LCD Display Register */ 73 /* 1 */ 74 #define HD64461_LCDLDR1_REG16 0xb0001010 75 #define HD64461_LCDLDR1_DINV 0x0100 76 #define HD64461_LCDLDR1_DON 0x0001 77 /* 2 */ 78 #define HD64461_LCDLDR2_REG16 0xb0001012 79 #define HD64461_LCDLDR2_CC1 0x0080 80 #define HD64461_LCDLDR2_CC2 0x0040 81 #define HD64461_LCDLDR2_LM_MASK 0x7 82 #define HD64461_LCDLDR2_LM(x) ((x) & HD64461_LCDLDR2_LM_MASK) 83 #define HD64461_LCDLDR2_LM_COLOR 0x4 84 #define HD64461_LCDLDR2_LM_GRAY8 0x1 85 #define HD64461_LCDLDR2_LM_GRAY4 0x0 86 /* 3 */ 87 #define HD64461_LCDLDR3_REG16 0xb000101e 88 #define HD64461_LCDLDR3_CS_SHIFT 5 89 #define HD64461_LCDLDR3_CS_MASK 0x1f 90 #define HD64461_LCDLDR3_CS(cr) \ 91 (((cr) >> HD64461_LCDLDR3_CS_SHIFT) & \ 92 HD64461_LCDLDR3_CS_MASK) 93 #define HD64461_LCDLDR3_CS_SET(cr, val) \ 94 ((cr) | (((val) << HD64461_LCDLDR3_CS_SHIFT) & \ 95 (HD64461_LCDLDR3_CS_MASK << HD64461_LCDLDR3_CS_SHIFT))) 96 #define HD64461_LCDLDR3_CG_MASK 0xf 97 #define HD64461_LCDLDR3_CG(cr) \ 98 ((cr) & HD64461_LCDLDR3_CG_MASK) 99 #define HD64461_LCDLDR3_CG_CLR(cr) \ 100 ((cr) & ~HD64461_LCDLDR3_CG_MASK) 101 #define HD64461_LCDLDR3_CG_SET(cr, val) \ 102 ((cr) | ((val) & HD64461_LCDLDR3_CG_MASK)) 103 104 /* 105 * select CL2 frequency 106 * 0x0 15 MHz (color) 15/2 (monochrome) 107 * 0x1 2.5 MHz 108 * 0x2 3.75 Mhz 109 * 0x4 5 Mhz 110 * 0x8 7.5 Mhz 111 * 0x10 10 Mhz 112 */ 113 #define HD64461_LCDLDR3_CG_COLOR16 0x8 114 #define HD64461_LCDLDR3_CG_COLOR8 0x4 115 #define HD64461_LCDLDR3_CG_GRAY6 0x3 116 #define HD64461_LCDLDR3_CG_GRAY4 0x2 117 #define HD64461_LCDLDR3_CG_GRAY2 0x1 118 #define HD64461_LCDLDR3_CG_GRAY1 0x0 119 120 /* LCD Number of Characters in Horizontal Register */ 121 #define HD64461_LCDLDHNCR_REG16 0xb0001014 122 #define HD64461_LCDLDHNCR_NHD_SHIFT 8 123 #define HD64461_LCDLDHNCR_NHD_MASK 0xff 124 #define HD64461_LCDLDHNCR_NHD(cr) \ 125 (((cr) >> HD64461_LCDLDHNCR_NHD_SHIFT) & \ 126 HD64461_LCDLDHNCR_NHD_MASK) 127 #define HD64461_LCDLDHNCR_NHD_SET(cr, val) \ 128 ((cr) | (((val) << HD64461_LCDLDHNCR_NHD_SHIFT) & \ 129 (HD64461_LCDLDHNCR_NHD_MASK << HD64461_LCDLDHNCR_NHD_SHIFT))) 130 #define HD64461_LCDLDHNCR_NHT_SHIFT 0 131 #define HD64461_LCDLDHNCR_NHT_MASK 0xff 132 #define HD64461_LCDLDHNCR_NHT(cr) \ 133 (((cr) >> HD64461_LCDLDHNCR_NHT_SHIFT) & \ 134 HD64461_LCDLDHNCR_NHT_MASK) 135 #define HD64461_LCDLDHNCR_NHT_SET(cr, val) \ 136 ((cr) | (((val) << HD64461_LCDLDHNCR_NHT_SHIFT) & \ 137 (HD64461_LCDLDHNCR_NHT_MASK << HD64461_LCDLDHNCR_NHT_SHIFT))) 138 139 /* Start Position of Horizontal Register */ 140 #define HD64461_LCDLDHNSR_REG16 0xb0001016 141 #define HD64461_LCDLDHNSR_HSW_SHIFT 8 142 #define HD64461_LCDLDHNSR_HSW_MASK 0xf 143 #define HD64461_LCDLDHNSR_HSW(cr) \ 144 (((cr) >> HD64461_LCDLDHNSR_HSW_SHIFT) & \ 145 HD64461_LCDLDHNSR_HSW_MASK) 146 #define HD64461_LCDLDHNSR_HSW_SET(cr, val) \ 147 ((cr) | (((val) << HD64461_LCDLDHNSR_HSW_SHIFT) & \ 148 (HD64461_LCDLDHNSR_HSW_MASK << HD64461_LCDLDHNSR_HSW_SHIFT))) 149 #define HD64461_LCDLDHNSR_HSP_SHIFT 0 150 #define HD64461_LCDLDHNSR_HSP_MASK 0xff 151 #define HD64461_LCDLDHNSR_HSP(cr) \ 152 (((cr) >> HD64461_LCDLDHNSR_HSP_SHIFT) & \ 153 HD64461_LCDLDHNSR_HSP_MASK) 154 #define HD64461_LCDLDHNSR_HSP_SET(cr, val) \ 155 ((cr) | (((val) << HD64461_LCDLDHNSR_HSP_SHIFT) & \ 156 (HD64461_LCDLDHNSR_HSP_MASK << HD64461_LCDLDHNSR_HSP_SHIFT))) 157 158 /* Total Vertical Lines Register */ 159 #define HD64461_LCDLDVNTR_REG16 0xb0001018 160 #define HD64461_LCDLDVNTR_VTL_SHIFT 0 161 #define HD64461_LCDLDVNTR_VTL_MASK 0x3ff 162 #define HD64461_LCDLDVNTR_VTL(cr) \ 163 (((cr) >> HD64461_LCDLDVNTR_VTL_SHIFT) & \ 164 HD64461_LCDLDVNTR_VTL_MASK) 165 #define HD64461_LCDLDVNTR_VTL_SET(cr, val) \ 166 ((cr) | (((val) << HD64461_LCDLDVNTR_VTL_SHIFT) & \ 167 (HD64461_LCDLDVNTR_VTL_MASK << HD64461_LCDLDVNTR_VTL_SHIFT))) 168 169 /* Display Vertical Lines Register */ 170 #define HD64461_LCDLDVNDR_REG16 0xb000101a 171 #define HD64461_LCDLDVNDR_VDL_SHIFT 0 172 #define HD64461_LCDLDVNDR_VDL_MASK 0x3ff 173 #define HD64461_LCDLDVNDR_VDL(cr) \ 174 (((cr) >> HD64461_LCDLDVNDR_VDL_SHIFT) & \ 175 HD64461_LCDLDVNDR_VDL_MASK) 176 #define HD64461_LCDLDVNDR_VDL_SET(cr, val) \ 177 ((cr) | (((val) << HD64461_LCDLDVNDR_VDL_SHIFT) & \ 178 (HD64461_LCDLDVNDR_VDL_MASK << HD64461_LCDLDVNDR_VDL_SHIFT))) 179 180 /* Vertical Synchronization Position Register */ 181 #define HD64461_LCDLDVSPR_REG16 0xb000101c 182 #define HD64461_LCDLDVSPR_VSP_SHIFT 0 183 #define HD64461_LCDLDVSPR_VSP_MASK 0x3ff 184 #define HD64461_LCDLDVSPR_VSP(cr) \ 185 ((cr) & HD64461_LCDLDVSPR_VSP_MASK) 186 #define HD64461_LCDLDVSPR_VSP_SET(cr, val) \ 187 ((cr) | ((val) & HD64461_LCDLDVSPR_VSP_MASK)) 188 189 /* 190 * CRT Control Register 191 */ 192 /* CRTC Total Vertical Lines Register */ 193 #define HD64461_LCDCRTVTR_REG16 0xb0001020 194 #define HD64461_LCDCRTVTR_SHIFT 0 195 #define HD64461_LCDCRTVTR_MASK 0x3ff 196 #define HD64461_LCDCRTVTR(cr) \ 197 (((cr) >> HD64461_LCDCRTVTR_SHIFT) & \ 198 HD64461_LCDCRTVTR_MASK) 199 #define HD64461_LCDCRTVTR_SET(cr, val) \ 200 ((cr) | (((val) << HD64461_LCDCRTVTR_SHIFT) & \ 201 (HD64461_LCDCRTVTR_MASK << HD64461_LCDCRTVTR_SHIFT))) 202 203 /* CRTC Vertical Retrace Start Register */ 204 #define HD64461_LCDCRTVRSR_REG16 0xb0001022 205 #define HD64461_LCDCRTVRSR_SHIFT 0 206 #define HD64461_LCDCRTVRSR_MASK 0x3ff 207 #define HD64461_LCDCRTVRSR(cr) \ 208 (((cr) >> HD64461_LCDCRTVRSR_SHIFT) & \ 209 HD64461_LCDCRTVRSR_MASK) 210 #define HD64461_LCDCRTVRSR_SET(cr, val) \ 211 ((cr) | (((val) << HD64461_LCDCRTVRSR_SHIFT) & \ 212 (HD64461_LCDCRTVRSR_MASK << HD64461_LCDCRTVRSR_SHIFT))) 213 214 /* CRTC Vertical Retrace End Register */ 215 #define HD64461_LCDCRTVRER_REG16 0xb0001024 216 #define HD64461_LCDCRTVRER_SHIFT 0 217 #define HD64461_LCDCRTVRER_MASK 0xf 218 #define HD64461_LCDCRTVRER(cr) \ 219 (((cr) >> HD64461_LCDCRTVRER_SHIFT) & HD64461_LCDCRTVRER_MASK) 220 221 #define HD64461_LCDCRTVRER_SET(cr, val) \ 222 ((cr) | (((val) << HD64461_LCDCRTVRER_SHIFT) & \ 223 (HD64461_LCDCRTVRER_MASK << HD64461_LCDCRTVRER_SHIFT))) 224 225 /* 226 * Palette Register 227 */ 228 /* Color Palette Write Address Register */ 229 #define HD64461_LCDCPTWAR_REG16 0xb0001030 230 #define HD64461_LCDCPTWAR_SHIFT 8 231 #define HD64461_LCDCPTWAR_MASK 0xff 232 #define HD64461_LCDCPTWAR_SET(cr, val) \ 233 ((cr) | (((val) << HD64461_LCDCPTWAR_SHIFT) & \ 234 (HD64461_LCDCPTWAR_MASK << HD64461_LCDCPTWAR_SHIFT))) 235 236 /* Color Palette Write Data Register */ 237 #define HD64461_LCDCPTWDR_REG16 0xb0001032 238 #define HD64461_LCDCPTWDR_SHIFT 0 239 #define HD64461_LCDCPTWDR_MASK 0x3f 240 #define HD64461_LCDCPTWDR_SET(cr, val) \ 241 ((cr) | ((val) & HD64461_LCDCPTWDR_MASK)) 242 243 /* Color Palette READ Address Register */ 244 #define HD64461_LCDCPTRAR_REG16 0xb0001034 245 #define HD64461_LCDCPTRAR_SHIFT 8 246 #define HD64461_LCDCPTRAR_MASK 0xff 247 #define HD64461_LCDCPTRAR_SET(cr, val) \ 248 ((cr) | (((val) << HD64461_LCDCPTRAR_SHIFT) & \ 249 (HD64461_LCDCPTRAR_MASK << HD64461_LCDCPTRAR_SHIFT))) 250 251 /* Color Palette READ Data Register */ 252 #define HD64461_LCDCPTRDR_REG16 0xb0001036 253 #define HD64461_LCDCPTRDR_SHIFT 0 254 #define HD64461_LCDCPTRDR_MASK 0x3f 255 #define HD64461_LCDCPTRDR(cr) ((cr) & HD64461_LCDCPTRDR_MASK) 256 257 /* 258 * Acceleration Common Register 259 */ 260 /* Display Resolution Offset Register */ 261 #define HD64461_LCDGRDOR_REG16 0xb0001040 262 #define HD64461_LCDGRDOR_SHIFT 0 263 #define HD64461_LCDGRDOR_MASK 0x7ff 264 #define HD64461_LCDGRDOR(cr) \ 265 (((cr) >> HD64461_LCDGRDOR_SHIFT) & \ 266 HD64461_LCDGRDOR_MASK) 267 #define HD64461_LCDGRDOR_SET(cr, val) \ 268 ((cr) | (((val) << HD64461_LCDGRDOR_SHIFT) & \ 269 (HD64461_LCDGRDOR_MASK << HD64461_LCDGRDOR_SHIFT))) 270 271 /* Solid Color Register */ 272 #define HD64461_LCDGRSCR_REG16 0xb0001042 273 274 /* Accelerator Configuration Register */ 275 #define HD64461_LCDGRCFGR_REG16 0xb0001044 276 #define HD64461_LCDGRCFGR_ACCSTATUS 0x0010 277 #define HD64461_LCDGRCFGR_ACCRESET 0x0008 278 #define HD64461_LCDGRCFGR_ACCSTART_MASK 0x6 279 #define HD64461_LCDGRCFGR_ACCSTART_BITBLT 0x0006 280 #define HD64461_LCDGRCFGR_ACCSTART_LINE 0x0004 281 #define HD64461_LCDGRCFGR_ACCSTART_OFF 0x0000 282 #define HD64461_LCDGRCFGR_COLORDEPTH_8BPP 0x0001 283 284 /* 285 * Line Drawing Register 286 */ 287 /* Line Start Address Register */ 288 #define HD64461_LCDLNSARH_REG16 0xb0001046 289 #define HD64461_LCDLNSARH_MASK 0x0007 290 #define HD64461_LCDLNSARL_REG16 0xb0001048 291 #define HD64461_LCDLNSARL_MASK 0xffff 292 293 /* Axis Pixel Length Register */ 294 #define HD64461_LCDLNAXLR_REG16 0xb000104a 295 #define HD64461_LCDLNAXLR_MASK 0x07ff 296 297 /* Diagonal Regsiter */ 298 #define HD64461_LCDLNDGR_REG16 0xb000104c 299 #define HD64461_LCDLNDGR_LNDGR_SIGN 0x8000 300 #define HD64461_LCDLNDGR_LNDGR_MASK 0x07ff 301 #define HD64461_LCDLNDGR_LNDGR_SET(cr, x) \ 302 ((cr) | ((x) & HD64461_LCDLNDGR_LNDGR_MASK)) 303 304 /* Axial Register */ 305 #define HD64461_LCDLNAXR_REG16 0xb000104e 306 #define HD64461_LCDLNAXR_LNAXR_MASK 0x0fff 307 #define HD64461_LCDLNAXR_LNAXR_SET(cr, x) \ 308 ((cr) | ((x) & HD64461_LCDLNAXR_LNAXR_MASK)) 309 310 /* Start Error Term Register */ 311 #define HD64461_LCDLNERTR_REG16 0xb0001050 312 #define HD64461_LCDLNERTR_LNERTR_SIGN 0x8000 313 #define HD64461_LCDLNERTR_LNERTR_MASK 0x07ff 314 #define HD64461_LCDLNERTR_LNERTR_SET(cr, x) \ 315 ((cr) | ((x) & HD64461_LCDLNERTR_LNERTR_MASK)) 316 317 /* Line Mode Register */ 318 #define HD64461_LCDLNMDR_REG16 0xb0001052 319 #define HD64461_LCDLNMDR_MASK 0x0003 320 /* 321 * 2 1 322 * 3 0 323 * 4 7 324 * 5 6 325 * 326 * 1 or 5 ... 3 327 * 2 or 6 ... 2 328 * 0 or 4 ... 1 329 * 3 or 7 ... 0 330 */ 331 332 /* 333 * BitBLT Register 334 */ 335 /* Source Start Address Register (19 bit) */ 336 #define HD64461_LCDBBTSSARH_REG16 0xb0001054 337 #define HD64461_LCDBBTSSARH_SHIFT 16 338 #define HD64461_LCDBBTSSARH_MASK 0x0007 339 #define HD64461_LCDBBTSSARL_REG16 0xb0001056 340 #define HD64461_LCDBBTSSARL_MASK 0xffff 341 #define HD64461_LCDBBTSSARH(x) \ 342 (((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK) 343 #define HD64461_LCDBBTSSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK) 344 345 /* Destination Start Address Register (19 bit) */ 346 #define HD64461_LCDBBTDSARH_REG16 0xb0001058 347 #define HD64461_LCDBBTDSARH_SHIFT 16 348 #define HD64461_LCDBBTDSARH_MASK 0x0007 349 #define HD64461_LCDBBTDSARL_REG16 0xb000105a 350 #define HD64461_LCDBBTDSARL_MASK 0xffff 351 #define HD64461_LCDBBTDSARH(x) \ 352 (((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK) 353 #define HD64461_LCDBBTDSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK) 354 355 /* Destination Block Width Register */ 356 #define HD64461_LCDBBTDWR_REG16 0xb000105c 357 #define HD64461_LCDBBTDWR_MASK 0x07ff 358 359 /* Destination Block Height Register */ 360 #define HD64461_LCDBBTDHR_REG16 0xb000105e 361 #define HD64461_LCDBBTDHR_MASK 0x07ff 362 363 /* Pattern Start Address Register (19 bit) */ 364 #define HD64461_LCDBBTPARH_REG16 0xb0001060 365 #define HD64461_LCDBBTPARH_MASK 0x0007 366 #define HD64461_LCDBBTPARL_REG16 0xb0001062 367 368 /* Mask Start Address Register (19 bit) */ 369 #define HD64461_LCDBBTMARH_REG16 0xb0001064 370 #define HD64461_LCDBBTMARH_MASK 0x0007 371 #define HD64461_LCDBBTMARL_REG16 0xb0001066 372 373 /* ROP Register */ 374 #define HD64461_LCDBBTROPR_REG16 0xb0001068 375 376 /* BitBLT Mode Register */ 377 #define HD64461_LCDBBTMDR_REG16 0xb000106a 378 #define HD64461_LCDBBTMDR_MASKENABLE 0x0020 379 #define HD64461_LCDBBTMDR_PATSELECT_SOLIDCOLOR 0x0010 380 #define HD64461_LCDBBTMDR_SHIFT 2 381 #define HD64461_LCDBBTMDR_MASK 0x3 382 #define HD64461_LCDBBTMDR(cr) \ 383 (((cr) >> HD64461_LCDBBTMDR_SHIFT) & HD64461_LCDBBTMDR_MASK) 384 385 #define HD64461_LCDBBTMDR_SET(cr, val) \ 386 ((cr) | (((val) << HD64461_LCDBBTMDR_SHIFT) & \ 387 (HD64461_LCDBBTMDR_MASK << HD64461_LCDBBTMDR_SHIFT))) 388 #define HD64461_LCDBBTMDR_ON_SCREEN_TO_ON_SCREEN 0 389 #define HD64461_LCDBBTMDR_ON_SCREEN_TO_OFF_SCREEN 1 390 #define HD64461_LCDBBTMDR_OFF_SCREEN_TO_ON_SCREEN 3 391 392 #define HD64461_LCDBBTMDR_SCANDRCT 0x0001 393 #define HD64461_LCDBBTMDR_SCANDRCT_RL_BT 0x1 394 #define HD64461_LCDBBTMDR_SCANDRCT_LR_TB 0x0 395 396 /* 397 * BitBLT Function 398 */ 399 #define HD64461_LCDC_BITBLT_SRCAND 0x0088 400 #define HD64461_LCDC_BITBLT_SRCCOPY 0x00cc 401 #define HD64461_LCDC_BITBLT_SRCINVERT 0x0066 402 #define HD64461_LCDC_BITBLT_SRCPAINT 0x00ee 403 #define HD64461_LCDC_BITBLT_PATCOPY 0x00f0 404 #define HD64461_LCDC_BITBLT_PATINVERT 0x005a 405 #define HD64461_LCDC_BITBLT_DSTINVERT 0x0055 406 #define HD64461_LCDC_BITBLT_BLACKNESS 0x0000 407 #define HD64461_LCDC_BITBLT_WHITENESS 0x00ff 408 #define HD64461_LCDC_BITBLT_MASKEDSRCCOPY 0xccaa 409 410 #endif /* !_HPCSH_DEV_HD64461VIDEOREG_H_ */ 411
Indexes created Tue Sep 30 17:09:57 GMT 2025