hd64461videoreg.h revision 1.3.68.1
1 /* $NetBSD: hd64461videoreg.h,v 1.3.68.1 2008/05/16 02:22:30 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _HPCSH_DEV_HD64461VIDEOREG_H_ 33 #define _HPCSH_DEV_HD64461VIDEOREG_H_ 34 35 /* 36 * LCD Controller Control Register 37 */ 38 39 /* Base Address Register */ 40 #define HD64461_LCDCBAR_REG16 0xb0001000 41 #define HD64461_LCDCBAR_MASK 0x3fff 42 #define HD64461_LCDCBAR_SHIFT 12 43 #define HD64461_LCDCBAR_BASEADDR(x) \ 44 (((x) & HD64461_LCDCBAR_MASK) << HD64461_LCDCBAR_SHIFT) 45 46 /* Line Address Offset Register */ 47 #define HD64461_LCDCLOR_REG16 0xb0001002 48 #define HD64461_LCDCLOR_MASK 0x07ff 49 #define HD64461_LCDCLOR(x) ((x) & HD64461_LCDCLOR_MASK) 50 51 /* LCDC Control Register */ 52 #define HD64461_LCDCCR_REG16 0xb0001004 53 #define HD64461_LCDCCR_STBAK 0x0400 54 #define HD64461_LCDCCR_STREQ 0x0100 55 #define HD64461_LCDCCR_MOFF 0x0080 56 #define HD64461_LCDCCR_REFSEL 0x0040 57 #define HD64461_LCDCCR_EPON 0x0020 58 #define HD64461_LCDCCR_SPON 0x0010 59 #define HD64461_LCDCCR_DSPSEL_MASK 0x7 60 #define HD64461_LCDCCR_DSPSEL(x) ((x) & HD64461_LCDCCR_DSPSEL_MASK) 61 #define HD64461_LCDCCR_DSPSEL_LCD_CRT 0x4 62 #define HD64461_LCDCCR_DSPSEL_CRT 0x2 63 #define HD64461_LCDCCR_DSPSEL_LCD 0x1 64 65 /* LCD Display Register */ 66 /* 1 */ 67 #define HD64461_LCDLDR1_REG16 0xb0001010 68 #define HD64461_LCDLDR1_DINV 0x0100 69 #define HD64461_LCDLDR1_DON 0x0001 70 /* 2 */ 71 #define HD64461_LCDLDR2_REG16 0xb0001012 72 #define HD64461_LCDLDR2_CC1 0x0080 73 #define HD64461_LCDLDR2_CC2 0x0040 74 #define HD64461_LCDLDR2_LM_MASK 0x7 75 #define HD64461_LCDLDR2_LM(x) ((x) & HD64461_LCDLDR2_LM_MASK) 76 #define HD64461_LCDLDR2_LM_COLOR 0x4 77 #define HD64461_LCDLDR2_LM_GRAY8 0x1 78 #define HD64461_LCDLDR2_LM_GRAY4 0x0 79 /* 3 */ 80 #define HD64461_LCDLDR3_REG16 0xb000101e 81 #define HD64461_LCDLDR3_CS_SHIFT 5 82 #define HD64461_LCDLDR3_CS_MASK 0x1f 83 #define HD64461_LCDLDR3_CS(cr) \ 84 (((cr) >> HD64461_LCDLDR3_CS_SHIFT) & \ 85 HD64461_LCDLDR3_CS_MASK) 86 #define HD64461_LCDLDR3_CS_SET(cr, val) \ 87 ((cr) | (((val) << HD64461_LCDLDR3_CS_SHIFT) & \ 88 (HD64461_LCDLDR3_CS_MASK << HD64461_LCDLDR3_CS_SHIFT))) 89 #define HD64461_LCDLDR3_CG_MASK 0xf 90 #define HD64461_LCDLDR3_CG(cr) \ 91 ((cr) & HD64461_LCDLDR3_CG_MASK) 92 #define HD64461_LCDLDR3_CG_CLR(cr) \ 93 ((cr) & ~HD64461_LCDLDR3_CG_MASK) 94 #define HD64461_LCDLDR3_CG_SET(cr, val) \ 95 ((cr) | ((val) & HD64461_LCDLDR3_CG_MASK)) 96 97 /* 98 * select CL2 frequency 99 * 0x0 15 MHz (color) 15/2 (monochrome) 100 * 0x1 2.5 MHz 101 * 0x2 3.75 MHz 102 * 0x4 5 MHz 103 * 0x8 7.5 MHz 104 * 0x10 10 MHz 105 */ 106 #define HD64461_LCDLDR3_CG_COLOR16 0x8 107 #define HD64461_LCDLDR3_CG_COLOR8 0x4 108 #define HD64461_LCDLDR3_CG_GRAY6 0x3 109 #define HD64461_LCDLDR3_CG_GRAY4 0x2 110 #define HD64461_LCDLDR3_CG_GRAY2 0x1 111 #define HD64461_LCDLDR3_CG_GRAY1 0x0 112 113 /* LCD Number of Characters in Horizontal Register */ 114 #define HD64461_LCDLDHNCR_REG16 0xb0001014 115 #define HD64461_LCDLDHNCR_NHD_SHIFT 8 116 #define HD64461_LCDLDHNCR_NHD_MASK 0xff 117 #define HD64461_LCDLDHNCR_NHD(cr) \ 118 (((cr) >> HD64461_LCDLDHNCR_NHD_SHIFT) & \ 119 HD64461_LCDLDHNCR_NHD_MASK) 120 #define HD64461_LCDLDHNCR_NHD_SET(cr, val) \ 121 ((cr) | (((val) << HD64461_LCDLDHNCR_NHD_SHIFT) & \ 122 (HD64461_LCDLDHNCR_NHD_MASK << HD64461_LCDLDHNCR_NHD_SHIFT))) 123 #define HD64461_LCDLDHNCR_NHT_SHIFT 0 124 #define HD64461_LCDLDHNCR_NHT_MASK 0xff 125 #define HD64461_LCDLDHNCR_NHT(cr) \ 126 (((cr) >> HD64461_LCDLDHNCR_NHT_SHIFT) & \ 127 HD64461_LCDLDHNCR_NHT_MASK) 128 #define HD64461_LCDLDHNCR_NHT_SET(cr, val) \ 129 ((cr) | (((val) << HD64461_LCDLDHNCR_NHT_SHIFT) & \ 130 (HD64461_LCDLDHNCR_NHT_MASK << HD64461_LCDLDHNCR_NHT_SHIFT))) 131 132 /* Start Position of Horizontal Register */ 133 #define HD64461_LCDLDHNSR_REG16 0xb0001016 134 #define HD64461_LCDLDHNSR_HSW_SHIFT 8 135 #define HD64461_LCDLDHNSR_HSW_MASK 0xf 136 #define HD64461_LCDLDHNSR_HSW(cr) \ 137 (((cr) >> HD64461_LCDLDHNSR_HSW_SHIFT) & \ 138 HD64461_LCDLDHNSR_HSW_MASK) 139 #define HD64461_LCDLDHNSR_HSW_SET(cr, val) \ 140 ((cr) | (((val) << HD64461_LCDLDHNSR_HSW_SHIFT) & \ 141 (HD64461_LCDLDHNSR_HSW_MASK << HD64461_LCDLDHNSR_HSW_SHIFT))) 142 #define HD64461_LCDLDHNSR_HSP_SHIFT 0 143 #define HD64461_LCDLDHNSR_HSP_MASK 0xff 144 #define HD64461_LCDLDHNSR_HSP(cr) \ 145 (((cr) >> HD64461_LCDLDHNSR_HSP_SHIFT) & \ 146 HD64461_LCDLDHNSR_HSP_MASK) 147 #define HD64461_LCDLDHNSR_HSP_SET(cr, val) \ 148 ((cr) | (((val) << HD64461_LCDLDHNSR_HSP_SHIFT) & \ 149 (HD64461_LCDLDHNSR_HSP_MASK << HD64461_LCDLDHNSR_HSP_SHIFT))) 150 151 /* Total Vertical Lines Register */ 152 #define HD64461_LCDLDVNTR_REG16 0xb0001018 153 #define HD64461_LCDLDVNTR_VTL_SHIFT 0 154 #define HD64461_LCDLDVNTR_VTL_MASK 0x3ff 155 #define HD64461_LCDLDVNTR_VTL(cr) \ 156 (((cr) >> HD64461_LCDLDVNTR_VTL_SHIFT) & \ 157 HD64461_LCDLDVNTR_VTL_MASK) 158 #define HD64461_LCDLDVNTR_VTL_SET(cr, val) \ 159 ((cr) | (((val) << HD64461_LCDLDVNTR_VTL_SHIFT) & \ 160 (HD64461_LCDLDVNTR_VTL_MASK << HD64461_LCDLDVNTR_VTL_SHIFT))) 161 162 /* Display Vertical Lines Register */ 163 #define HD64461_LCDLDVNDR_REG16 0xb000101a 164 #define HD64461_LCDLDVNDR_VDL_SHIFT 0 165 #define HD64461_LCDLDVNDR_VDL_MASK 0x3ff 166 #define HD64461_LCDLDVNDR_VDL(cr) \ 167 (((cr) >> HD64461_LCDLDVNDR_VDL_SHIFT) & \ 168 HD64461_LCDLDVNDR_VDL_MASK) 169 #define HD64461_LCDLDVNDR_VDL_SET(cr, val) \ 170 ((cr) | (((val) << HD64461_LCDLDVNDR_VDL_SHIFT) & \ 171 (HD64461_LCDLDVNDR_VDL_MASK << HD64461_LCDLDVNDR_VDL_SHIFT))) 172 173 /* Vertical Synchronization Position Register */ 174 #define HD64461_LCDLDVSPR_REG16 0xb000101c 175 #define HD64461_LCDLDVSPR_VSP_SHIFT 0 176 #define HD64461_LCDLDVSPR_VSP_MASK 0x3ff 177 #define HD64461_LCDLDVSPR_VSP(cr) \ 178 ((cr) & HD64461_LCDLDVSPR_VSP_MASK) 179 #define HD64461_LCDLDVSPR_VSP_SET(cr, val) \ 180 ((cr) | ((val) & HD64461_LCDLDVSPR_VSP_MASK)) 181 182 /* 183 * CRT Control Register 184 */ 185 /* CRTC Total Vertical Lines Register */ 186 #define HD64461_LCDCRTVTR_REG16 0xb0001020 187 #define HD64461_LCDCRTVTR_SHIFT 0 188 #define HD64461_LCDCRTVTR_MASK 0x3ff 189 #define HD64461_LCDCRTVTR(cr) \ 190 (((cr) >> HD64461_LCDCRTVTR_SHIFT) & \ 191 HD64461_LCDCRTVTR_MASK) 192 #define HD64461_LCDCRTVTR_SET(cr, val) \ 193 ((cr) | (((val) << HD64461_LCDCRTVTR_SHIFT) & \ 194 (HD64461_LCDCRTVTR_MASK << HD64461_LCDCRTVTR_SHIFT))) 195 196 /* CRTC Vertical Retrace Start Register */ 197 #define HD64461_LCDCRTVRSR_REG16 0xb0001022 198 #define HD64461_LCDCRTVRSR_SHIFT 0 199 #define HD64461_LCDCRTVRSR_MASK 0x3ff 200 #define HD64461_LCDCRTVRSR(cr) \ 201 (((cr) >> HD64461_LCDCRTVRSR_SHIFT) & \ 202 HD64461_LCDCRTVRSR_MASK) 203 #define HD64461_LCDCRTVRSR_SET(cr, val) \ 204 ((cr) | (((val) << HD64461_LCDCRTVRSR_SHIFT) & \ 205 (HD64461_LCDCRTVRSR_MASK << HD64461_LCDCRTVRSR_SHIFT))) 206 207 /* CRTC Vertical Retrace End Register */ 208 #define HD64461_LCDCRTVRER_REG16 0xb0001024 209 #define HD64461_LCDCRTVRER_SHIFT 0 210 #define HD64461_LCDCRTVRER_MASK 0xf 211 #define HD64461_LCDCRTVRER(cr) \ 212 (((cr) >> HD64461_LCDCRTVRER_SHIFT) & HD64461_LCDCRTVRER_MASK) 213 214 #define HD64461_LCDCRTVRER_SET(cr, val) \ 215 ((cr) | (((val) << HD64461_LCDCRTVRER_SHIFT) & \ 216 (HD64461_LCDCRTVRER_MASK << HD64461_LCDCRTVRER_SHIFT))) 217 218 /* 219 * Palette Register 220 */ 221 /* Color Palette Write Address Register */ 222 #define HD64461_LCDCPTWAR_REG16 0xb0001030 223 #define HD64461_LCDCPTWAR_SHIFT 8 224 #define HD64461_LCDCPTWAR_MASK 0xff 225 #define HD64461_LCDCPTWAR_SET(cr, val) \ 226 ((cr) | (((val) << HD64461_LCDCPTWAR_SHIFT) & \ 227 (HD64461_LCDCPTWAR_MASK << HD64461_LCDCPTWAR_SHIFT))) 228 229 /* Color Palette Write Data Register */ 230 #define HD64461_LCDCPTWDR_REG16 0xb0001032 231 #define HD64461_LCDCPTWDR_SHIFT 0 232 #define HD64461_LCDCPTWDR_MASK 0x3f 233 #define HD64461_LCDCPTWDR_SET(cr, val) \ 234 ((cr) | ((val) & HD64461_LCDCPTWDR_MASK)) 235 236 /* Color Palette READ Address Register */ 237 #define HD64461_LCDCPTRAR_REG16 0xb0001034 238 #define HD64461_LCDCPTRAR_SHIFT 8 239 #define HD64461_LCDCPTRAR_MASK 0xff 240 #define HD64461_LCDCPTRAR_SET(cr, val) \ 241 ((cr) | (((val) << HD64461_LCDCPTRAR_SHIFT) & \ 242 (HD64461_LCDCPTRAR_MASK << HD64461_LCDCPTRAR_SHIFT))) 243 244 /* Color Palette READ Data Register */ 245 #define HD64461_LCDCPTRDR_REG16 0xb0001036 246 #define HD64461_LCDCPTRDR_SHIFT 0 247 #define HD64461_LCDCPTRDR_MASK 0x3f 248 #define HD64461_LCDCPTRDR(cr) ((cr) & HD64461_LCDCPTRDR_MASK) 249 250 /* 251 * Acceleration Common Register 252 */ 253 /* Display Resolution Offset Register */ 254 #define HD64461_LCDGRDOR_REG16 0xb0001040 255 #define HD64461_LCDGRDOR_SHIFT 0 256 #define HD64461_LCDGRDOR_MASK 0x7ff 257 #define HD64461_LCDGRDOR(cr) \ 258 (((cr) >> HD64461_LCDGRDOR_SHIFT) & \ 259 HD64461_LCDGRDOR_MASK) 260 #define HD64461_LCDGRDOR_SET(cr, val) \ 261 ((cr) | (((val) << HD64461_LCDGRDOR_SHIFT) & \ 262 (HD64461_LCDGRDOR_MASK << HD64461_LCDGRDOR_SHIFT))) 263 264 /* Solid Color Register */ 265 #define HD64461_LCDGRSCR_REG16 0xb0001042 266 267 /* Accelerator Configuration Register */ 268 #define HD64461_LCDGRCFGR_REG16 0xb0001044 269 #define HD64461_LCDGRCFGR_ACCSTATUS 0x0010 270 #define HD64461_LCDGRCFGR_ACCRESET 0x0008 271 #define HD64461_LCDGRCFGR_ACCSTART_MASK 0x6 272 #define HD64461_LCDGRCFGR_ACCSTART_BITBLT 0x0006 273 #define HD64461_LCDGRCFGR_ACCSTART_LINE 0x0004 274 #define HD64461_LCDGRCFGR_ACCSTART_OFF 0x0000 275 #define HD64461_LCDGRCFGR_COLORDEPTH_8BPP 0x0001 276 277 /* 278 * Line Drawing Register 279 */ 280 /* Line Start Address Register */ 281 #define HD64461_LCDLNSARH_REG16 0xb0001046 282 #define HD64461_LCDLNSARH_MASK 0x0007 283 #define HD64461_LCDLNSARL_REG16 0xb0001048 284 #define HD64461_LCDLNSARL_MASK 0xffff 285 286 /* Axis Pixel Length Register */ 287 #define HD64461_LCDLNAXLR_REG16 0xb000104a 288 #define HD64461_LCDLNAXLR_MASK 0x07ff 289 290 /* Diagonal Regsiter */ 291 #define HD64461_LCDLNDGR_REG16 0xb000104c 292 #define HD64461_LCDLNDGR_LNDGR_SIGN 0x8000 293 #define HD64461_LCDLNDGR_LNDGR_MASK 0x07ff 294 #define HD64461_LCDLNDGR_LNDGR_SET(cr, x) \ 295 ((cr) | ((x) & HD64461_LCDLNDGR_LNDGR_MASK)) 296 297 /* Axial Register */ 298 #define HD64461_LCDLNAXR_REG16 0xb000104e 299 #define HD64461_LCDLNAXR_LNAXR_MASK 0x0fff 300 #define HD64461_LCDLNAXR_LNAXR_SET(cr, x) \ 301 ((cr) | ((x) & HD64461_LCDLNAXR_LNAXR_MASK)) 302 303 /* Start Error Term Register */ 304 #define HD64461_LCDLNERTR_REG16 0xb0001050 305 #define HD64461_LCDLNERTR_LNERTR_SIGN 0x8000 306 #define HD64461_LCDLNERTR_LNERTR_MASK 0x07ff 307 #define HD64461_LCDLNERTR_LNERTR_SET(cr, x) \ 308 ((cr) | ((x) & HD64461_LCDLNERTR_LNERTR_MASK)) 309 310 /* Line Mode Register */ 311 #define HD64461_LCDLNMDR_REG16 0xb0001052 312 #define HD64461_LCDLNMDR_MASK 0x0003 313 /* 314 * 2 1 315 * 3 0 316 * 4 7 317 * 5 6 318 * 319 * 1 or 5 ... 3 320 * 2 or 6 ... 2 321 * 0 or 4 ... 1 322 * 3 or 7 ... 0 323 */ 324 325 /* 326 * BitBLT Register 327 */ 328 /* Source Start Address Register (19 bit) */ 329 #define HD64461_LCDBBTSSARH_REG16 0xb0001054 330 #define HD64461_LCDBBTSSARH_SHIFT 16 331 #define HD64461_LCDBBTSSARH_MASK 0x0007 332 #define HD64461_LCDBBTSSARL_REG16 0xb0001056 333 #define HD64461_LCDBBTSSARL_MASK 0xffff 334 #define HD64461_LCDBBTSSARH(x) \ 335 (((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK) 336 #define HD64461_LCDBBTSSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK) 337 338 /* Destination Start Address Register (19 bit) */ 339 #define HD64461_LCDBBTDSARH_REG16 0xb0001058 340 #define HD64461_LCDBBTDSARH_SHIFT 16 341 #define HD64461_LCDBBTDSARH_MASK 0x0007 342 #define HD64461_LCDBBTDSARL_REG16 0xb000105a 343 #define HD64461_LCDBBTDSARL_MASK 0xffff 344 #define HD64461_LCDBBTDSARH(x) \ 345 (((x) >> HD64461_LCDBBTSSARH_SHIFT) & HD64461_LCDBBTSSARH_MASK) 346 #define HD64461_LCDBBTDSARL(x) ((x) & HD64461_LCDBBTSSARL_MASK) 347 348 /* Destination Block Width Register */ 349 #define HD64461_LCDBBTDWR_REG16 0xb000105c 350 #define HD64461_LCDBBTDWR_MASK 0x07ff 351 352 /* Destination Block Height Register */ 353 #define HD64461_LCDBBTDHR_REG16 0xb000105e 354 #define HD64461_LCDBBTDHR_MASK 0x07ff 355 356 /* Pattern Start Address Register (19 bit) */ 357 #define HD64461_LCDBBTPARH_REG16 0xb0001060 358 #define HD64461_LCDBBTPARH_MASK 0x0007 359 #define HD64461_LCDBBTPARL_REG16 0xb0001062 360 361 /* Mask Start Address Register (19 bit) */ 362 #define HD64461_LCDBBTMARH_REG16 0xb0001064 363 #define HD64461_LCDBBTMARH_MASK 0x0007 364 #define HD64461_LCDBBTMARL_REG16 0xb0001066 365 366 /* ROP Register */ 367 #define HD64461_LCDBBTROPR_REG16 0xb0001068 368 369 /* BitBLT Mode Register */ 370 #define HD64461_LCDBBTMDR_REG16 0xb000106a 371 #define HD64461_LCDBBTMDR_MASKENABLE 0x0020 372 #define HD64461_LCDBBTMDR_PATSELECT_SOLIDCOLOR 0x0010 373 #define HD64461_LCDBBTMDR_SHIFT 2 374 #define HD64461_LCDBBTMDR_MASK 0x3 375 #define HD64461_LCDBBTMDR(cr) \ 376 (((cr) >> HD64461_LCDBBTMDR_SHIFT) & HD64461_LCDBBTMDR_MASK) 377 378 #define HD64461_LCDBBTMDR_SET(cr, val) \ 379 ((cr) | (((val) << HD64461_LCDBBTMDR_SHIFT) & \ 380 (HD64461_LCDBBTMDR_MASK << HD64461_LCDBBTMDR_SHIFT))) 381 #define HD64461_LCDBBTMDR_ON_SCREEN_TO_ON_SCREEN 0 382 #define HD64461_LCDBBTMDR_ON_SCREEN_TO_OFF_SCREEN 1 383 #define HD64461_LCDBBTMDR_OFF_SCREEN_TO_ON_SCREEN 3 384 385 #define HD64461_LCDBBTMDR_SCANDRCT 0x0001 386 #define HD64461_LCDBBTMDR_SCANDRCT_RL_BT 0x1 387 #define HD64461_LCDBBTMDR_SCANDRCT_LR_TB 0x0 388 389 /* 390 * BitBLT Function 391 */ 392 #define HD64461_LCDC_BITBLT_SRCAND 0x0088 393 #define HD64461_LCDC_BITBLT_SRCCOPY 0x00cc 394 #define HD64461_LCDC_BITBLT_SRCINVERT 0x0066 395 #define HD64461_LCDC_BITBLT_SRCPAINT 0x00ee 396 #define HD64461_LCDC_BITBLT_PATCOPY 0x00f0 397 #define HD64461_LCDC_BITBLT_PATINVERT 0x005a 398 #define HD64461_LCDC_BITBLT_DSTINVERT 0x0055 399 #define HD64461_LCDC_BITBLT_BLACKNESS 0x0000 400 #define HD64461_LCDC_BITBLT_WHITENESS 0x00ff 401 #define HD64461_LCDC_BITBLT_MASKEDSRCCOPY 0xccaa 402 403 #endif /* !_HPCSH_DEV_HD64461VIDEOREG_H_ */ 404
Indexes created Wed Oct 22 06:10:02 GMT 2025