hd64465pcmcia.c revision 1.1
1 /* $NetBSD: hd64465pcmcia.c,v 1.1 2002/02/11 17:27:16 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/kthread.h> 44 #include <sys/boot_flag.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/bscreg.h> 56 57 #include <hpcsh/dev/hd64465/hd64465reg.h> 58 #include <hpcsh/dev/hd64465/hd64465var.h> 59 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 60 61 #include "locators.h" 62 63 #ifdef HD64465PCMCIA_DEBUG 64 #define DPRINTF_ENABLE 65 #define DPRINTF_DEBUG hd64465pcmcia_debug 66 #endif 67 #include <machine/debug.h> 68 69 enum memory_window_16 { 70 MEMWIN_16M_COMMON_0, 71 MEMWIN_16M_COMMON_1, 72 MEMWIN_16M_COMMON_2, 73 MEMWIN_16M_COMMON_3, 74 }; 75 #define MEMWIN_16M_MAX 4 76 77 enum hd64465pcmcia_event_type { 78 EVENT_NONE, 79 EVENT_INSERT, 80 EVENT_REMOVE, 81 }; 82 #define EVENT_QUEUE_MAX 5 83 84 struct hd64465pcmcia_softc; /* forward declaration */ 85 86 struct hd64465pcmcia_window_cookie { 87 bus_space_tag_t wc_tag; 88 bus_space_handle_t wc_handle; 89 int wc_size; 90 int wc_window; 91 }; 92 93 struct hd64465pcmcia_channel { 94 struct hd64465pcmcia_softc *ch_parent; 95 struct device *ch_pcmcia; 96 int ch_channel; 97 98 /* memory space */ 99 bus_space_tag_t ch_memt; 100 bus_space_handle_t ch_memh; 101 bus_addr_t ch_membase_addr; 102 bus_size_t ch_memsize; 103 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 104 105 /* I/O space */ 106 bus_space_tag_t ch_iot; 107 bus_addr_t ch_iobase; 108 bus_size_t ch_iosize; 109 110 /* card interrupt */ 111 int (*ch_ih_card_func)(void *); 112 void *ch_ih_card_arg; 113 int ch_attached; 114 }; 115 116 struct hd64465pcmcia_event { 117 int __queued; 118 enum hd64465pcmcia_event_type pe_type; 119 struct hd64465pcmcia_channel *pe_ch; 120 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 121 }; 122 123 struct hd64465pcmcia_softc { 124 struct device sc_dev; 125 enum hd64465_module_id sc_module_id; 126 int sc_shutdown; 127 128 /* kv mapped Area 5, 6 */ 129 vaddr_t sc_area5; 130 vaddr_t sc_area6; 131 132 /* CSC event */ 133 struct proc *sc_event_thread; 134 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 135 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 136 137 struct hd64465pcmcia_channel sc_ch[2]; 138 }; 139 140 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 141 struct pcmcia_mem_handle *); 142 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 143 struct pcmcia_mem_handle *); 144 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 145 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 146 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 147 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 148 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 149 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 150 struct pcmcia_io_handle *); 151 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 152 bus_size_t, struct pcmcia_io_handle *, int *); 153 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 154 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 155 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 156 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 157 struct pcmcia_function *, int, int (*)(void *), void *); 158 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 159 void *); 160 161 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 162 hd64465pcmcia_chip_mem_alloc, 163 hd64465pcmcia_chip_mem_free, 164 hd64465pcmcia_chip_mem_map, 165 hd64465pcmcia_chip_mem_unmap, 166 hd64465pcmcia_chip_io_alloc, 167 hd64465pcmcia_chip_io_free, 168 hd64465pcmcia_chip_io_map, 169 hd64465pcmcia_chip_io_unmap, 170 hd64465pcmcia_chip_intr_establish, 171 hd64465pcmcia_chip_intr_disestablish, 172 hd64465pcmcia_chip_socket_enable, 173 hd64465pcmcia_chip_socket_disable, 174 }; 175 176 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 177 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 178 STATIC int hd64465pcmcia_print(void *, const char *); 179 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 180 181 struct cfattach hd64465pcmcia_ca = { 182 sizeof(struct hd64465pcmcia_softc), hd64465pcmcia_match, 183 hd64465pcmcia_attach 184 }; 185 186 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 187 /* hot plug */ 188 STATIC void hd64465pcmcia_create_event_thread(void *); 189 STATIC void hd64465pcmcia_event_thread(void *); 190 STATIC void queue_event(struct hd64465pcmcia_channel *, 191 enum hd64465pcmcia_event_type); 192 /* interrupt handler */ 193 STATIC int hd64465pcmcia_intr(void *); 194 /* card status */ 195 STATIC enum hd64465pcmcia_event_type detect_card(int); 196 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 197 /* bus width */ 198 STATIC void __sh_set_bus_width(int, int); 199 /* bus space access */ 200 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 201 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 202 203 #define DELAY_MS(x) delay((x) * 1000) 204 205 int 206 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 207 { 208 struct hd64465_attach_args *ha = aux; 209 210 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 211 } 212 213 void 214 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 215 { 216 struct hd64465_attach_args *ha = aux; 217 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 218 219 sc->sc_module_id = ha->ha_module_id; 220 221 printf("\n"); 222 223 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 224 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 225 226 if (sc->sc_area5 == NULL || sc->sc_area6 == NULL) { 227 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 228 if (sc->sc_area5) 229 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000); 230 if (sc->sc_area6) 231 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000); 232 233 return; 234 } 235 236 /* Channel 0/1 common CSC event queue */ 237 SIMPLEQ_INIT (&sc->sc_event_head); 238 kthread_create(hd64465pcmcia_create_event_thread, sc); 239 240 hd64465pcmcia_attach_channel(sc, 0); 241 hd64465pcmcia_attach_channel(sc, 1); 242 } 243 244 void 245 hd64465pcmcia_create_event_thread(void *arg) 246 { 247 struct hd64465pcmcia_softc *sc = arg; 248 int error; 249 250 error = kthread_create1(hd64465pcmcia_event_thread, sc, 251 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 252 253 KASSERT(error == 0); 254 } 255 256 void 257 hd64465pcmcia_event_thread(void *arg) 258 { 259 struct hd64465pcmcia_softc *sc = arg; 260 struct hd64465pcmcia_event *pe; 261 int s; 262 263 while (!sc->sc_shutdown) { 264 tsleep(sc, PWAIT, "CSC wait", 0); 265 s = splhigh(); 266 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 267 splx(s); 268 switch (pe->pe_type) { 269 default: 270 printf("%s: unknown event.\n", __FUNCTION__); 271 break; 272 case EVENT_INSERT: 273 DPRINTF("insert event.\n"); 274 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 275 break; 276 case EVENT_REMOVE: 277 DPRINTF("remove event.\n"); 278 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 279 DETACH_FORCE); 280 break; 281 } 282 s = splhigh(); 283 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 284 pe->__queued = 0; 285 } 286 splx(s); 287 } 288 /* NOTREACHED */ 289 } 290 291 int 292 hd64465pcmcia_print(void *arg, const char *pnp) 293 { 294 295 if (pnp) 296 printf("pcmcia at %s", pnp); 297 298 return (UNCONF); 299 } 300 301 int 302 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 303 { 304 struct pcmciabus_attach_args *paa = aux; 305 struct hd64465pcmcia_channel *ch = 306 (struct hd64465pcmcia_channel *)paa->pch; 307 308 if (ch->ch_channel == 0) { 309 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 310 PCMCIABUSCF_CONTROLLER_DEFAULT && 311 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 312 return 0; 313 } else { 314 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 315 PCMCIABUSCF_CONTROLLER_DEFAULT && 316 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 317 return 0; 318 } 319 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 320 321 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 322 } 323 324 void 325 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 326 { 327 struct device *parent = (struct device *)sc; 328 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 329 struct pcmciabus_attach_args paa; 330 bus_addr_t baseaddr; 331 u_int8_t r; 332 int i; 333 334 ch->ch_parent = sc; 335 ch->ch_channel = channel; 336 337 /* 338 * Continuous 16-MB Area Mode 339 */ 340 /* set Continuous 16-MB Area Mode */ 341 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 342 r &= ~HD64461_PCCGCR_MMOD; 343 r |= HD64461_PCCGCR_MMOD_16M; 344 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 345 346 /* Attibute/Common memory extent */ 347 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 348 349 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 350 baseaddr, 0x01000000); /* 16MB */ 351 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 352 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 353 354 /* Common memory space extent */ 355 ch->ch_memsize = 0x01000000; 356 for (i = 0; i < MEMWIN_16M_MAX; i++) { 357 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 358 baseaddr + 0x01000000, ch->ch_memsize); 359 } 360 361 /* I/O port extent */ 362 ch->ch_iobase = 0; 363 ch->ch_iosize = 0x01000000; 364 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 365 baseaddr + 0x01000000 * 2, ch->ch_iosize); 366 367 /* Interrupt */ 368 hd64465_intr_establish(channel ? HD64465_IRQ_PCC1 : HD64465_IRQ_PCC0, 369 IST_EDGE, IPL_TTY, hd64465pcmcia_intr, ch); 370 371 paa.paa_busname = "pcmcia"; 372 paa.pch = (pcmcia_chipset_handle_t)ch; 373 paa.iobase = ch->ch_iobase; 374 paa.iosize = ch->ch_iosize; 375 376 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 377 hd64465pcmcia_submatch); 378 379 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) { 380 ch->ch_attached = 1; 381 pcmcia_card_attach(ch->ch_pcmcia); 382 } 383 } 384 385 int 386 hd64465pcmcia_intr(void *arg) 387 { 388 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 389 u_int32_t cscr; 390 u_int8_t r; 391 int ret = 0; 392 393 cscr = HD64461_PCCCSCR(ch->ch_channel); 394 r = hd64465_reg_read_1(cscr); 395 396 /* clear interrtupt (don't change power switch select) */ 397 hd64465_reg_write_1(cscr, r & ~0x40); 398 399 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 400 if (ch->ch_ih_card_func) { 401 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 402 } else { 403 DPRINTF("spurious IREQ interrupt.\n"); 404 } 405 } 406 407 if (r & HD64461_PCC0CSCR_P0CDC) 408 queue_event(ch, detect_card(ch->ch_channel)); 409 410 return (ret); 411 } 412 413 void 414 queue_event(struct hd64465pcmcia_channel *ch, 415 enum hd64465pcmcia_event_type type) 416 { 417 struct hd64465pcmcia_event *pe, *pool; 418 struct hd64465pcmcia_softc *sc = ch->ch_parent; 419 int i; 420 int s = splhigh(); 421 422 if (type == EVENT_NONE) 423 goto out; 424 425 pe = 0; 426 pool = sc->sc_event_pool; 427 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 428 if (!pool[i].__queued) { 429 pe = &pool[i]; 430 break; 431 } 432 } 433 434 if (pe == 0) { 435 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 436 EVENT_QUEUE_MAX); 437 goto out; 438 } 439 440 if ((ch->ch_attached && (type == EVENT_INSERT)) || 441 (!ch->ch_attached && (type == EVENT_REMOVE))) { 442 DPRINTF("spurious CSC interrupt.\n"); 443 goto out; 444 } 445 446 ch->ch_attached = (type == EVENT_INSERT); 447 pe->__queued = 1; 448 pe->pe_type = type; 449 pe->pe_ch = ch; 450 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 451 wakeup(sc); 452 out: 453 splx(s); 454 } 455 456 /* 457 * Interface for pcmcia driver. 458 */ 459 /* 460 * Interrupt. 461 */ 462 void * 463 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 464 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 465 { 466 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 467 int channel = ch->ch_channel; 468 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 469 u_int8_t r; 470 int s = splhigh(); 471 472 ch->ch_ih_card_func = ih_func; 473 ch->ch_ih_card_arg = ih_arg; 474 475 /* Enable card interrupt */ 476 r = hd64465_reg_read_1(cscier); 477 /* set level mode */ 478 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 479 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 480 hd64465_reg_write_1(cscier, r); 481 482 splx(s); 483 484 return (void *)ih_func; 485 } 486 487 void 488 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 489 { 490 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 491 int channel = ch->ch_channel; 492 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 493 int s = splhigh(); 494 u_int8_t r; 495 496 /* Disable card interrupt */ 497 r = hd64465_reg_read_1(cscier); 498 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 499 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 500 hd64465_reg_write_1(cscier, r); 501 502 ch->ch_ih_card_func = 0; 503 504 splx(s); 505 } 506 507 /* 508 * Bus resources. 509 */ 510 int 511 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 512 struct pcmcia_mem_handle *pcmhp) 513 { 514 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 515 516 pcmhp->memt = ch->ch_memt; 517 pcmhp->addr = ch->ch_membase_addr; 518 pcmhp->memh = ch->ch_memh; 519 pcmhp->size = size; 520 pcmhp->realsize = size; 521 522 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 523 524 return (0); 525 } 526 527 void 528 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 529 struct pcmcia_mem_handle *pcmhp) 530 { 531 /* NO-OP */ 532 } 533 534 int 535 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 536 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 537 bus_size_t *offsetp, int *windowp) 538 { 539 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 540 struct hd64465pcmcia_window_cookie *cookie; 541 bus_addr_t ofs; 542 543 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 544 M_DEVBUF, M_NOWAIT); 545 KASSERT(cookie); 546 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 547 548 /* Address */ 549 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 550 cookie->wc_tag = ch->ch_memt; 551 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 552 size, &cookie->wc_handle) != 0) 553 goto bad; 554 555 *offsetp = card_addr; 556 cookie->wc_window = -1; 557 } else { 558 int window = card_addr / ch->ch_memsize; 559 KASSERT(window < MEMWIN_16M_MAX); 560 561 cookie->wc_tag = ch->ch_cmemt[window]; 562 ofs = card_addr - window * ch->ch_memsize; 563 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 564 &cookie->wc_handle) != 0) 565 goto bad; 566 567 /* XXX bogus. check window per common memory access. */ 568 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 569 *offsetp = ofs + 0x01000000; /* skip attribute area */ 570 cookie->wc_window = window; 571 } 572 cookie->wc_size = size; 573 *windowp = (int)cookie; 574 575 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 576 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 577 578 return (0); 579 bad: 580 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 581 free(cookie, M_DEVBUF); 582 583 return (1); 584 } 585 586 void 587 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 588 { 589 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 590 591 if (cookie->wc_window != -1) 592 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 593 cookie->wc_size); 594 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 595 free(cookie, M_DEVBUF); 596 } 597 598 int 599 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 600 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 601 { 602 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 603 604 if (start) { 605 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 606 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 607 return (1); 608 } 609 pcihp->addr = pcihp->ioh; 610 DPRINTF("map %#lx+%#lx\n", start, size); 611 } else { 612 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 613 ch->ch_iobase + ch->ch_iosize - 1, 614 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 615 DPRINTF("couldn't allocate %#lx\n", size); 616 return (1); 617 } 618 pcihp->flags = PCMCIA_IO_ALLOCATED; 619 } 620 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 621 622 pcihp->iot = ch->ch_iot; 623 pcihp->size = size; 624 625 return (0); 626 } 627 628 int 629 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 630 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 631 int *windowp) 632 { 633 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 634 #ifdef HD64465PCMCIA_DEBUG 635 static const char *width_names[] = { "auto", "io8", "io16" }; 636 #endif 637 638 __sh_set_bus_width(ch->ch_channel, width); 639 640 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 641 width_names[width]); 642 643 return (0); 644 } 645 646 void 647 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 648 struct pcmcia_io_handle *pcihp) 649 { 650 651 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 652 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 653 else 654 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 655 656 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 657 } 658 659 void 660 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 661 { 662 /* nothing to do */ 663 } 664 665 /* 666 * Enable/Disable 667 */ 668 void 669 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 670 { 671 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 672 int channel = ch->ch_channel; 673 bus_addr_t isr, gcr; 674 u_int8_t r; 675 int cardtype; 676 677 DPRINTF("enable channel %d\n", channel); 678 isr = HD64461_PCCISR(channel); 679 gcr = HD64461_PCCGCR(channel); 680 681 /* Set Common memory area #0. */ 682 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 683 684 /* Set the card type */ 685 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 686 687 r = hd64465_reg_read_1(gcr); 688 if (cardtype == PCMCIA_IFTYPE_IO) 689 r |= HD64461_PCC0GCR_P0PCCT; 690 else 691 r &= ~HD64461_PCC0GCR_P0PCCT; 692 hd64465_reg_write_1(gcr, r); 693 694 DPRINTF("OK.\n"); 695 } 696 697 void 698 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 699 { 700 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 701 int channel = ch->ch_channel; 702 703 /* dont' disable CSC interrupt */ 704 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 705 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 706 } 707 708 /* 709 * Card detect 710 */ 711 enum hd64465pcmcia_event_type 712 detect_card(int channel) 713 { 714 u_int8_t r; 715 716 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 717 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 718 719 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 720 DPRINTF("remove\n"); 721 return EVENT_REMOVE; 722 } 723 if (r == 0) { 724 DPRINTF("insert\n"); 725 return EVENT_INSERT; 726 } 727 DPRINTF("transition\n"); 728 729 return (EVENT_NONE); 730 } 731 732 /* 733 * Memory window access ops. 734 */ 735 void 736 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 737 { 738 bus_addr_t a = HD64461_PCCGCR(channel); 739 u_int8_t r; 740 741 r = hd64465_reg_read_1(a); 742 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 743 744 switch (window) { 745 case MEMWIN_16M_COMMON_0: 746 break; 747 case MEMWIN_16M_COMMON_1: 748 r |= HD64461_PCCGCR_PA24; 749 break; 750 case MEMWIN_16M_COMMON_2: 751 r |= HD64461_PCCGCR_PA25; 752 break; 753 case MEMWIN_16M_COMMON_3: 754 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 755 break; 756 } 757 758 hd64465_reg_write_1(a, r); 759 } 760 761 /* 762 * SH interface. 763 */ 764 void 765 __sh_set_bus_width(int channel, int width) 766 { 767 u_int16_t r16; 768 769 r16 = SHREG_BCR2; 770 #ifdef HD64465PCMCIA_DEBUG 771 dbg_bit_print_msg(r16, "BCR2"); 772 #endif 773 if (channel == 0) { 774 r16 &= ~((1 << 13)|(1 << 12)); 775 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 776 } else { 777 r16 &= ~((1 << 11)|(1 << 10)); 778 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 779 } 780 SHREG_BCR2 = r16; 781 } 782 783 vaddr_t 784 __sh_hd64465_map_2page(paddr_t pa) 785 { 786 static const u_int32_t mode[] = 787 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 788 vaddr_t va, v; 789 int i; 790 791 /* allocate kernel virtual */ 792 v = va = uvm_km_valloc(kernel_map, 0x03000000); 793 if (va == NULL) { 794 PRINTF("can't allocate virtual for paddr 0x%08x\n", 795 (unsigned)pa); 796 797 return (0); 798 } 799 800 /* map to physical addreess with specified memory type. */ 801 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 802 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 803 uvm_km_free(kernel_map, v, 0x03000000); 804 return (0); 805 } 806 } 807 808 return (v); 809 } 810 811 int 812 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 813 { 814 pt_entry_t *pte; 815 paddr_t epa; 816 817 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 818 ((sz & PAGE_MASK) == 0)); 819 820 epa = pa + sz; 821 while (pa < epa) { 822 if (pmap_enter(pmap_kernel(), va, pa, 823 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED) != 0) { 824 PRINTF("can't map va 0x%08x -> pa 0x%08x\n", 825 (unsigned)va, (unsigned)pa); 826 return (1); 827 } 828 829 pte = kvtopte(va); 830 *pte &= ~PG_N; /* uncacheable */ 831 *pte |= flags; /* PTEA PCMCIA assistant bit */ 832 pmap_update_pg(va); 833 834 pa += NBPG; 835 va += NBPG; 836 } 837 838 pmap_update(pmap_kernel()); 839 840 return (0); 841 } 842
Indexes created Fri Oct 03 15:10:06 GMT 2025