hd64465pcmcia.c revision 1.11
1 /* $NetBSD: hd64465pcmcia.c,v 1.11 2003/01/01 01:41:34 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/kthread.h> 44 #include <sys/boot_flag.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/bscreg.h> 56 #include <sh3/mmu.h> 57 58 #include <hpcsh/dev/hd64465/hd64465reg.h> 59 #include <hpcsh/dev/hd64465/hd64465var.h> 60 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 61 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 62 63 #include "locators.h" 64 65 #ifdef HD64465PCMCIA_DEBUG 66 #define DPRINTF_ENABLE 67 #define DPRINTF_DEBUG hd64465pcmcia_debug 68 #endif 69 #include <machine/debug.h> 70 71 enum memory_window_16 { 72 MEMWIN_16M_COMMON_0, 73 MEMWIN_16M_COMMON_1, 74 MEMWIN_16M_COMMON_2, 75 MEMWIN_16M_COMMON_3, 76 }; 77 #define MEMWIN_16M_MAX 4 78 79 enum hd64465pcmcia_event_type { 80 EVENT_NONE, 81 EVENT_INSERT, 82 EVENT_REMOVE, 83 }; 84 #define EVENT_QUEUE_MAX 5 85 86 struct hd64465pcmcia_softc; /* forward declaration */ 87 88 struct hd64465pcmcia_window_cookie { 89 bus_space_tag_t wc_tag; 90 bus_space_handle_t wc_handle; 91 int wc_size; 92 int wc_window; 93 }; 94 95 struct hd64465pcmcia_channel { 96 struct hd64465pcmcia_softc *ch_parent; 97 struct device *ch_pcmcia; 98 int ch_channel; 99 100 /* memory space */ 101 bus_space_tag_t ch_memt; 102 bus_space_handle_t ch_memh; 103 bus_addr_t ch_membase_addr; 104 bus_size_t ch_memsize; 105 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 106 107 /* I/O space */ 108 bus_space_tag_t ch_iot; 109 bus_addr_t ch_iobase; 110 bus_size_t ch_iosize; 111 112 /* card interrupt */ 113 int (*ch_ih_card_func)(void *); 114 void *ch_ih_card_arg; 115 int ch_attached; 116 }; 117 118 struct hd64465pcmcia_event { 119 int __queued; 120 enum hd64465pcmcia_event_type pe_type; 121 struct hd64465pcmcia_channel *pe_ch; 122 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 123 }; 124 125 struct hd64465pcmcia_softc { 126 struct device sc_dev; 127 enum hd64465_module_id sc_module_id; 128 int sc_shutdown; 129 130 /* kv mapped Area 5, 6 */ 131 vaddr_t sc_area5; 132 vaddr_t sc_area6; 133 134 /* CSC event */ 135 struct proc *sc_event_thread; 136 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 137 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 138 139 struct hd64465pcmcia_channel sc_ch[2]; 140 }; 141 142 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 143 struct pcmcia_mem_handle *); 144 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 145 struct pcmcia_mem_handle *); 146 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 147 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 148 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 149 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 150 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 151 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 152 struct pcmcia_io_handle *); 153 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_io_handle *, int *); 155 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 156 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 157 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 158 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 159 struct pcmcia_function *, int, int (*)(void *), void *); 160 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 161 void *); 162 163 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 164 hd64465pcmcia_chip_mem_alloc, 165 hd64465pcmcia_chip_mem_free, 166 hd64465pcmcia_chip_mem_map, 167 hd64465pcmcia_chip_mem_unmap, 168 hd64465pcmcia_chip_io_alloc, 169 hd64465pcmcia_chip_io_free, 170 hd64465pcmcia_chip_io_map, 171 hd64465pcmcia_chip_io_unmap, 172 hd64465pcmcia_chip_intr_establish, 173 hd64465pcmcia_chip_intr_disestablish, 174 hd64465pcmcia_chip_socket_enable, 175 hd64465pcmcia_chip_socket_disable, 176 }; 177 178 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 179 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 180 STATIC int hd64465pcmcia_print(void *, const char *); 181 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 182 183 CFATTACH_DECL(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 184 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 185 186 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 187 /* hot plug */ 188 STATIC void hd64465pcmcia_create_event_thread(void *); 189 STATIC void hd64465pcmcia_event_thread(void *); 190 STATIC void __queue_event(struct hd64465pcmcia_channel *, 191 enum hd64465pcmcia_event_type); 192 /* interrupt handler */ 193 STATIC int hd64465pcmcia_intr(void *); 194 /* card status */ 195 STATIC enum hd64465pcmcia_event_type __detect_card(int); 196 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 197 /* bus width */ 198 STATIC void __sh_set_bus_width(int, int); 199 /* bus space access */ 200 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 201 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 202 203 #define DELAY_MS(x) delay((x) * 1000) 204 205 int 206 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 207 { 208 struct hd64465_attach_args *ha = aux; 209 210 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 211 } 212 213 void 214 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 215 { 216 struct hd64465_attach_args *ha = aux; 217 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 218 219 sc->sc_module_id = ha->ha_module_id; 220 221 printf("\n"); 222 223 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 224 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 225 226 if (sc->sc_area5 == NULL || sc->sc_area6 == NULL) { 227 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 228 if (sc->sc_area5) 229 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000); 230 if (sc->sc_area6) 231 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000); 232 233 return; 234 } 235 236 /* Channel 0/1 common CSC event queue */ 237 SIMPLEQ_INIT (&sc->sc_event_head); 238 kthread_create(hd64465pcmcia_create_event_thread, sc); 239 240 hd64465pcmcia_attach_channel(sc, 0); 241 hd64465pcmcia_attach_channel(sc, 1); 242 } 243 244 void 245 hd64465pcmcia_create_event_thread(void *arg) 246 { 247 struct hd64465pcmcia_softc *sc = arg; 248 int error; 249 250 error = kthread_create1(hd64465pcmcia_event_thread, sc, 251 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 252 253 KASSERT(error == 0); 254 } 255 256 void 257 hd64465pcmcia_event_thread(void *arg) 258 { 259 struct hd64465pcmcia_softc *sc = arg; 260 struct hd64465pcmcia_event *pe; 261 int s; 262 263 while (!sc->sc_shutdown) { 264 tsleep(sc, PWAIT, "CSC wait", 0); 265 s = splhigh(); 266 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 267 splx(s); 268 switch (pe->pe_type) { 269 default: 270 printf("%s: unknown event.\n", __FUNCTION__); 271 break; 272 case EVENT_INSERT: 273 DPRINTF("insert event.\n"); 274 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 275 break; 276 case EVENT_REMOVE: 277 DPRINTF("remove event.\n"); 278 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 279 DETACH_FORCE); 280 break; 281 } 282 s = splhigh(); 283 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 284 pe->__queued = 0; 285 } 286 splx(s); 287 } 288 /* NOTREACHED */ 289 } 290 291 int 292 hd64465pcmcia_print(void *arg, const char *pnp) 293 { 294 295 if (pnp) 296 aprint_normal("pcmcia at %s", pnp); 297 298 return (UNCONF); 299 } 300 301 int 302 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 303 { 304 struct pcmciabus_attach_args *paa = aux; 305 struct hd64465pcmcia_channel *ch = 306 (struct hd64465pcmcia_channel *)paa->pch; 307 308 if (ch->ch_channel == 0) { 309 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 310 PCMCIABUSCF_CONTROLLER_DEFAULT && 311 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 312 return 0; 313 } else { 314 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 315 PCMCIABUSCF_CONTROLLER_DEFAULT && 316 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 317 return 0; 318 } 319 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 320 321 return (config_match(parent, cf, aux)); 322 } 323 324 void 325 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 326 { 327 struct device *parent = (struct device *)sc; 328 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 329 struct pcmciabus_attach_args paa; 330 bus_addr_t baseaddr; 331 u_int8_t r; 332 int i; 333 334 ch->ch_parent = sc; 335 ch->ch_channel = channel; 336 337 /* 338 * Continuous 16-MB Area Mode 339 */ 340 /* set Continuous 16-MB Area Mode */ 341 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 342 r &= ~HD64461_PCCGCR_MMOD; 343 r |= HD64461_PCCGCR_MMOD_16M; 344 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 345 346 /* Attibute/Common memory extent */ 347 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 348 349 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 350 baseaddr, 0x01000000); /* 16MB */ 351 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 352 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 353 354 /* Common memory space extent */ 355 ch->ch_memsize = 0x01000000; 356 for (i = 0; i < MEMWIN_16M_MAX; i++) { 357 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 358 baseaddr + 0x01000000, ch->ch_memsize); 359 } 360 361 /* I/O port extent */ 362 ch->ch_iobase = 0; 363 ch->ch_iosize = 0x01000000; 364 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 365 baseaddr + 0x01000000 * 2, ch->ch_iosize); 366 367 /* Interrupt */ 368 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 369 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 370 371 paa.paa_busname = "pcmcia"; 372 paa.pch = (pcmcia_chipset_handle_t)ch; 373 paa.iobase = ch->ch_iobase; 374 paa.iosize = ch->ch_iosize; 375 376 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 377 hd64465pcmcia_submatch); 378 379 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 380 ch->ch_attached = 1; 381 pcmcia_card_attach(ch->ch_pcmcia); 382 } 383 } 384 385 int 386 hd64465pcmcia_intr(void *arg) 387 { 388 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 389 u_int32_t cscr; 390 u_int8_t r; 391 int ret = 0; 392 393 cscr = HD64461_PCCCSCR(ch->ch_channel); 394 r = hd64465_reg_read_1(cscr); 395 396 /* clear interrtupt (don't change power switch select) */ 397 hd64465_reg_write_1(cscr, r & ~0x40); 398 399 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 400 if (ch->ch_ih_card_func) { 401 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 402 } else { 403 DPRINTF("spurious IREQ interrupt.\n"); 404 } 405 } 406 407 if (r & HD64461_PCC0CSCR_P0CDC) 408 __queue_event(ch, __detect_card(ch->ch_channel)); 409 410 return (ret); 411 } 412 413 void 414 __queue_event(struct hd64465pcmcia_channel *ch, 415 enum hd64465pcmcia_event_type type) 416 { 417 struct hd64465pcmcia_event *pe, *pool; 418 struct hd64465pcmcia_softc *sc = ch->ch_parent; 419 int i; 420 int s = splhigh(); 421 422 if (type == EVENT_NONE) 423 goto out; 424 425 pe = 0; 426 pool = sc->sc_event_pool; 427 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 428 if (!pool[i].__queued) { 429 pe = &pool[i]; 430 break; 431 } 432 } 433 434 if (pe == 0) { 435 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 436 EVENT_QUEUE_MAX); 437 goto out; 438 } 439 440 if ((ch->ch_attached && (type == EVENT_INSERT)) || 441 (!ch->ch_attached && (type == EVENT_REMOVE))) { 442 DPRINTF("spurious CSC interrupt.\n"); 443 goto out; 444 } 445 446 ch->ch_attached = (type == EVENT_INSERT); 447 pe->__queued = 1; 448 pe->pe_type = type; 449 pe->pe_ch = ch; 450 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 451 wakeup(sc); 452 out: 453 splx(s); 454 } 455 456 /* 457 * Interface for pcmcia driver. 458 */ 459 /* 460 * Interrupt. 461 */ 462 void * 463 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 464 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 465 { 466 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 467 int channel = ch->ch_channel; 468 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 469 u_int8_t r; 470 int s = splhigh(); 471 472 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 473 ipl); 474 475 ch->ch_ih_card_func = ih_func; 476 ch->ch_ih_card_arg = ih_arg; 477 478 /* Enable card interrupt */ 479 r = hd64465_reg_read_1(cscier); 480 /* set level mode */ 481 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 482 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 483 hd64465_reg_write_1(cscier, r); 484 485 splx(s); 486 487 return (void *)ih_func; 488 } 489 490 void 491 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 492 { 493 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 494 int channel = ch->ch_channel; 495 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 496 int s = splhigh(); 497 u_int8_t r; 498 499 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 500 IPL_TTY); 501 502 /* Disable card interrupt */ 503 r = hd64465_reg_read_1(cscier); 504 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 505 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 506 hd64465_reg_write_1(cscier, r); 507 508 ch->ch_ih_card_func = 0; 509 510 splx(s); 511 } 512 513 /* 514 * Bus resources. 515 */ 516 int 517 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 518 struct pcmcia_mem_handle *pcmhp) 519 { 520 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 521 522 pcmhp->memt = ch->ch_memt; 523 pcmhp->addr = ch->ch_membase_addr; 524 pcmhp->memh = ch->ch_memh; 525 pcmhp->size = size; 526 pcmhp->realsize = size; 527 528 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 529 530 return (0); 531 } 532 533 void 534 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 535 struct pcmcia_mem_handle *pcmhp) 536 { 537 /* NO-OP */ 538 } 539 540 int 541 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 542 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 543 bus_size_t *offsetp, int *windowp) 544 { 545 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 546 struct hd64465pcmcia_window_cookie *cookie; 547 bus_addr_t ofs; 548 549 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 550 M_DEVBUF, M_NOWAIT); 551 KASSERT(cookie); 552 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 553 554 /* Address */ 555 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 556 cookie->wc_tag = ch->ch_memt; 557 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 558 size, &cookie->wc_handle) != 0) 559 goto bad; 560 561 *offsetp = card_addr; 562 cookie->wc_window = -1; 563 } else { 564 int window = card_addr / ch->ch_memsize; 565 KASSERT(window < MEMWIN_16M_MAX); 566 567 cookie->wc_tag = ch->ch_cmemt[window]; 568 ofs = card_addr - window * ch->ch_memsize; 569 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 570 &cookie->wc_handle) != 0) 571 goto bad; 572 573 /* XXX bogus. check window per common memory access. */ 574 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 575 *offsetp = ofs + 0x01000000; /* skip attribute area */ 576 cookie->wc_window = window; 577 } 578 cookie->wc_size = size; 579 *windowp = (int)cookie; 580 581 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 582 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 583 584 return (0); 585 bad: 586 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 587 free(cookie, M_DEVBUF); 588 589 return (1); 590 } 591 592 void 593 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 594 { 595 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 596 597 if (cookie->wc_window != -1) 598 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 599 cookie->wc_size); 600 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 601 free(cookie, M_DEVBUF); 602 } 603 604 int 605 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 606 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 607 { 608 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 609 610 if (start) { 611 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 612 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 613 return (1); 614 } 615 pcihp->addr = pcihp->ioh; 616 DPRINTF("map %#lx+%#lx\n", start, size); 617 } else { 618 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 619 ch->ch_iobase + ch->ch_iosize - 1, 620 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 621 DPRINTF("couldn't allocate %#lx\n", size); 622 return (1); 623 } 624 pcihp->flags = PCMCIA_IO_ALLOCATED; 625 } 626 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 627 628 pcihp->iot = ch->ch_iot; 629 pcihp->size = size; 630 631 return (0); 632 } 633 634 int 635 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 636 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 637 int *windowp) 638 { 639 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 640 #ifdef HD64465PCMCIA_DEBUG 641 static const char *width_names[] = { "auto", "io8", "io16" }; 642 #endif 643 644 __sh_set_bus_width(ch->ch_channel, width); 645 646 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 647 width_names[width]); 648 649 return (0); 650 } 651 652 void 653 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 654 struct pcmcia_io_handle *pcihp) 655 { 656 657 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 658 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 659 else 660 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 661 662 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 663 } 664 665 void 666 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 667 { 668 /* nothing to do */ 669 } 670 671 /* 672 * Enable/Disable 673 */ 674 void 675 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 676 { 677 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 678 int channel = ch->ch_channel; 679 bus_addr_t isr, gcr; 680 u_int8_t r; 681 int cardtype; 682 683 DPRINTF("enable channel %d\n", channel); 684 isr = HD64461_PCCISR(channel); 685 gcr = HD64461_PCCGCR(channel); 686 687 /* Set Common memory area #0. */ 688 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 689 690 /* Set the card type */ 691 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 692 693 r = hd64465_reg_read_1(gcr); 694 if (cardtype == PCMCIA_IFTYPE_IO) 695 r |= HD64461_PCC0GCR_P0PCCT; 696 else 697 r &= ~HD64461_PCC0GCR_P0PCCT; 698 hd64465_reg_write_1(gcr, r); 699 700 DPRINTF("OK.\n"); 701 } 702 703 void 704 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 705 { 706 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 707 int channel = ch->ch_channel; 708 709 /* dont' disable CSC interrupt */ 710 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 711 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 712 } 713 714 /* 715 * Card detect 716 */ 717 enum hd64465pcmcia_event_type 718 __detect_card(int channel) 719 { 720 u_int8_t r; 721 722 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 723 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 724 725 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 726 DPRINTF("remove\n"); 727 return EVENT_REMOVE; 728 } 729 if (r == 0) { 730 DPRINTF("insert\n"); 731 return EVENT_INSERT; 732 } 733 DPRINTF("transition\n"); 734 735 return (EVENT_NONE); 736 } 737 738 /* 739 * Memory window access ops. 740 */ 741 void 742 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 743 { 744 bus_addr_t a = HD64461_PCCGCR(channel); 745 u_int8_t r; 746 747 r = hd64465_reg_read_1(a); 748 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 749 750 switch (window) { 751 case MEMWIN_16M_COMMON_0: 752 break; 753 case MEMWIN_16M_COMMON_1: 754 r |= HD64461_PCCGCR_PA24; 755 break; 756 case MEMWIN_16M_COMMON_2: 757 r |= HD64461_PCCGCR_PA25; 758 break; 759 case MEMWIN_16M_COMMON_3: 760 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 761 break; 762 } 763 764 hd64465_reg_write_1(a, r); 765 } 766 767 /* 768 * SH interface. 769 */ 770 void 771 __sh_set_bus_width(int channel, int width) 772 { 773 u_int16_t r16; 774 775 r16 = _reg_read_2(SH4_BCR2); 776 #ifdef HD64465PCMCIA_DEBUG 777 dbg_bit_print_msg(r16, "BCR2"); 778 #endif 779 if (channel == 0) { 780 r16 &= ~((1 << 13)|(1 << 12)); 781 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 782 } else { 783 r16 &= ~((1 << 11)|(1 << 10)); 784 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 785 } 786 _reg_write_2(SH4_BCR2, r16); 787 } 788 789 vaddr_t 790 __sh_hd64465_map_2page(paddr_t pa) 791 { 792 static const u_int32_t mode[] = 793 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 794 vaddr_t va, v; 795 int i; 796 797 /* allocate kernel virtual */ 798 v = va = uvm_km_valloc(kernel_map, 0x03000000); 799 if (va == NULL) { 800 PRINTF("can't allocate virtual for paddr 0x%08x\n", 801 (unsigned)pa); 802 803 return (0); 804 } 805 806 /* map to physical addreess with specified memory type. */ 807 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 808 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 809 uvm_km_free(kernel_map, v, 0x03000000); 810 return (0); 811 } 812 } 813 814 return (v); 815 } 816 817 int 818 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 819 { 820 pt_entry_t *pte; 821 paddr_t epa; 822 823 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 824 ((sz & PAGE_MASK) == 0)); 825 826 epa = pa + sz; 827 while (pa < epa) { 828 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 829 pte = __pmap_kpte_lookup(va); 830 KDASSERT(pte); 831 *pte |= flags; /* PTEA PCMCIA assistant bit */ 832 sh_tlb_update(0, va, *pte); 833 pa += NBPG; 834 va += NBPG; 835 } 836 837 return (0); 838 } 839
Indexes created Fri Oct 03 02:09:57 GMT 2025