hd64465pcmcia.c revision 1.13
1 /* $NetBSD: hd64465pcmcia.c,v 1.13 2003/07/15 02:29:37 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.13 2003/07/15 02:29:37 lukem Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/kthread.h> 47 #include <sys/boot_flag.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 #include <sh3/mmu.h> 60 61 #include <hpcsh/dev/hd64465/hd64465reg.h> 62 #include <hpcsh/dev/hd64465/hd64465var.h> 63 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64465PCMCIA_DEBUG 69 #define DPRINTF_ENABLE 70 #define DPRINTF_DEBUG hd64465pcmcia_debug 71 #endif 72 #include <machine/debug.h> 73 74 enum memory_window_16 { 75 MEMWIN_16M_COMMON_0, 76 MEMWIN_16M_COMMON_1, 77 MEMWIN_16M_COMMON_2, 78 MEMWIN_16M_COMMON_3, 79 }; 80 #define MEMWIN_16M_MAX 4 81 82 enum hd64465pcmcia_event_type { 83 EVENT_NONE, 84 EVENT_INSERT, 85 EVENT_REMOVE, 86 }; 87 #define EVENT_QUEUE_MAX 5 88 89 struct hd64465pcmcia_softc; /* forward declaration */ 90 91 struct hd64465pcmcia_window_cookie { 92 bus_space_tag_t wc_tag; 93 bus_space_handle_t wc_handle; 94 int wc_size; 95 int wc_window; 96 }; 97 98 struct hd64465pcmcia_channel { 99 struct hd64465pcmcia_softc *ch_parent; 100 struct device *ch_pcmcia; 101 int ch_channel; 102 103 /* memory space */ 104 bus_space_tag_t ch_memt; 105 bus_space_handle_t ch_memh; 106 bus_addr_t ch_membase_addr; 107 bus_size_t ch_memsize; 108 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 109 110 /* I/O space */ 111 bus_space_tag_t ch_iot; 112 bus_addr_t ch_iobase; 113 bus_size_t ch_iosize; 114 115 /* card interrupt */ 116 int (*ch_ih_card_func)(void *); 117 void *ch_ih_card_arg; 118 int ch_attached; 119 }; 120 121 struct hd64465pcmcia_event { 122 int __queued; 123 enum hd64465pcmcia_event_type pe_type; 124 struct hd64465pcmcia_channel *pe_ch; 125 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 126 }; 127 128 struct hd64465pcmcia_softc { 129 struct device sc_dev; 130 enum hd64465_module_id sc_module_id; 131 int sc_shutdown; 132 133 /* kv mapped Area 5, 6 */ 134 vaddr_t sc_area5; 135 vaddr_t sc_area6; 136 137 /* CSC event */ 138 struct proc *sc_event_thread; 139 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 140 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 141 142 struct hd64465pcmcia_channel sc_ch[2]; 143 }; 144 145 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *); 147 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *); 149 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 151 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 152 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 154 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *); 156 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *); 158 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 159 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 160 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 161 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 162 struct pcmcia_function *, int, int (*)(void *), void *); 163 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 164 void *); 165 166 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 167 hd64465pcmcia_chip_mem_alloc, 168 hd64465pcmcia_chip_mem_free, 169 hd64465pcmcia_chip_mem_map, 170 hd64465pcmcia_chip_mem_unmap, 171 hd64465pcmcia_chip_io_alloc, 172 hd64465pcmcia_chip_io_free, 173 hd64465pcmcia_chip_io_map, 174 hd64465pcmcia_chip_io_unmap, 175 hd64465pcmcia_chip_intr_establish, 176 hd64465pcmcia_chip_intr_disestablish, 177 hd64465pcmcia_chip_socket_enable, 178 hd64465pcmcia_chip_socket_disable, 179 }; 180 181 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 182 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 183 STATIC int hd64465pcmcia_print(void *, const char *); 184 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 185 186 CFATTACH_DECL(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 187 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 188 189 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 190 /* hot plug */ 191 STATIC void hd64465pcmcia_create_event_thread(void *); 192 STATIC void hd64465pcmcia_event_thread(void *); 193 STATIC void __queue_event(struct hd64465pcmcia_channel *, 194 enum hd64465pcmcia_event_type); 195 /* interrupt handler */ 196 STATIC int hd64465pcmcia_intr(void *); 197 /* card status */ 198 STATIC enum hd64465pcmcia_event_type __detect_card(int); 199 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 200 /* bus width */ 201 STATIC void __sh_set_bus_width(int, int); 202 /* bus space access */ 203 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 204 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 205 206 #define DELAY_MS(x) delay((x) * 1000) 207 208 int 209 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 210 { 211 struct hd64465_attach_args *ha = aux; 212 213 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 214 } 215 216 void 217 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 218 { 219 struct hd64465_attach_args *ha = aux; 220 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 221 222 sc->sc_module_id = ha->ha_module_id; 223 224 printf("\n"); 225 226 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 227 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 228 229 if (sc->sc_area5 == NULL || sc->sc_area6 == NULL) { 230 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 231 if (sc->sc_area5) 232 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000); 233 if (sc->sc_area6) 234 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000); 235 236 return; 237 } 238 239 /* Channel 0/1 common CSC event queue */ 240 SIMPLEQ_INIT (&sc->sc_event_head); 241 kthread_create(hd64465pcmcia_create_event_thread, sc); 242 243 hd64465pcmcia_attach_channel(sc, 0); 244 hd64465pcmcia_attach_channel(sc, 1); 245 } 246 247 void 248 hd64465pcmcia_create_event_thread(void *arg) 249 { 250 struct hd64465pcmcia_softc *sc = arg; 251 int error; 252 253 error = kthread_create1(hd64465pcmcia_event_thread, sc, 254 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 255 256 KASSERT(error == 0); 257 } 258 259 void 260 hd64465pcmcia_event_thread(void *arg) 261 { 262 struct hd64465pcmcia_softc *sc = arg; 263 struct hd64465pcmcia_event *pe; 264 int s; 265 266 while (!sc->sc_shutdown) { 267 tsleep(sc, PWAIT, "CSC wait", 0); 268 s = splhigh(); 269 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 270 splx(s); 271 switch (pe->pe_type) { 272 default: 273 printf("%s: unknown event.\n", __FUNCTION__); 274 break; 275 case EVENT_INSERT: 276 DPRINTF("insert event.\n"); 277 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 278 break; 279 case EVENT_REMOVE: 280 DPRINTF("remove event.\n"); 281 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 282 DETACH_FORCE); 283 break; 284 } 285 s = splhigh(); 286 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 287 pe->__queued = 0; 288 } 289 splx(s); 290 } 291 /* NOTREACHED */ 292 } 293 294 int 295 hd64465pcmcia_print(void *arg, const char *pnp) 296 { 297 298 if (pnp) 299 aprint_normal("pcmcia at %s", pnp); 300 301 return (UNCONF); 302 } 303 304 int 305 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 306 { 307 struct pcmciabus_attach_args *paa = aux; 308 struct hd64465pcmcia_channel *ch = 309 (struct hd64465pcmcia_channel *)paa->pch; 310 311 if (ch->ch_channel == 0) { 312 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 313 PCMCIABUSCF_CONTROLLER_DEFAULT && 314 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 315 return 0; 316 } else { 317 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 318 PCMCIABUSCF_CONTROLLER_DEFAULT && 319 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 320 return 0; 321 } 322 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 323 324 return (config_match(parent, cf, aux)); 325 } 326 327 void 328 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 329 { 330 struct device *parent = (struct device *)sc; 331 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 332 struct pcmciabus_attach_args paa; 333 bus_addr_t baseaddr; 334 u_int8_t r; 335 int i; 336 337 ch->ch_parent = sc; 338 ch->ch_channel = channel; 339 340 /* 341 * Continuous 16-MB Area Mode 342 */ 343 /* set Continuous 16-MB Area Mode */ 344 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 345 r &= ~HD64461_PCCGCR_MMOD; 346 r |= HD64461_PCCGCR_MMOD_16M; 347 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 348 349 /* Attibute/Common memory extent */ 350 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 351 352 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 353 baseaddr, 0x01000000); /* 16MB */ 354 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 355 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 356 357 /* Common memory space extent */ 358 ch->ch_memsize = 0x01000000; 359 for (i = 0; i < MEMWIN_16M_MAX; i++) { 360 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 361 baseaddr + 0x01000000, ch->ch_memsize); 362 } 363 364 /* I/O port extent */ 365 ch->ch_iobase = 0; 366 ch->ch_iosize = 0x01000000; 367 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 368 baseaddr + 0x01000000 * 2, ch->ch_iosize); 369 370 /* Interrupt */ 371 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 372 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 373 374 paa.paa_busname = "pcmcia"; 375 paa.pch = (pcmcia_chipset_handle_t)ch; 376 paa.iobase = ch->ch_iobase; 377 paa.iosize = ch->ch_iosize; 378 379 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 380 hd64465pcmcia_submatch); 381 382 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 383 ch->ch_attached = 1; 384 pcmcia_card_attach(ch->ch_pcmcia); 385 } 386 } 387 388 int 389 hd64465pcmcia_intr(void *arg) 390 { 391 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 392 u_int32_t cscr; 393 u_int8_t r; 394 int ret = 0; 395 396 cscr = HD64461_PCCCSCR(ch->ch_channel); 397 r = hd64465_reg_read_1(cscr); 398 399 /* clear interrtupt (don't change power switch select) */ 400 hd64465_reg_write_1(cscr, r & ~0x40); 401 402 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 403 if (ch->ch_ih_card_func) { 404 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 405 } else { 406 DPRINTF("spurious IREQ interrupt.\n"); 407 } 408 } 409 410 if (r & HD64461_PCC0CSCR_P0CDC) 411 __queue_event(ch, __detect_card(ch->ch_channel)); 412 413 return (ret); 414 } 415 416 void 417 __queue_event(struct hd64465pcmcia_channel *ch, 418 enum hd64465pcmcia_event_type type) 419 { 420 struct hd64465pcmcia_event *pe, *pool; 421 struct hd64465pcmcia_softc *sc = ch->ch_parent; 422 int i; 423 int s = splhigh(); 424 425 if (type == EVENT_NONE) 426 goto out; 427 428 pe = 0; 429 pool = sc->sc_event_pool; 430 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 431 if (!pool[i].__queued) { 432 pe = &pool[i]; 433 break; 434 } 435 } 436 437 if (pe == 0) { 438 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 439 EVENT_QUEUE_MAX); 440 goto out; 441 } 442 443 if ((ch->ch_attached && (type == EVENT_INSERT)) || 444 (!ch->ch_attached && (type == EVENT_REMOVE))) { 445 DPRINTF("spurious CSC interrupt.\n"); 446 goto out; 447 } 448 449 ch->ch_attached = (type == EVENT_INSERT); 450 pe->__queued = 1; 451 pe->pe_type = type; 452 pe->pe_ch = ch; 453 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 454 wakeup(sc); 455 out: 456 splx(s); 457 } 458 459 /* 460 * Interface for pcmcia driver. 461 */ 462 /* 463 * Interrupt. 464 */ 465 void * 466 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 467 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 468 { 469 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 470 int channel = ch->ch_channel; 471 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 472 u_int8_t r; 473 int s = splhigh(); 474 475 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 476 ipl); 477 478 ch->ch_ih_card_func = ih_func; 479 ch->ch_ih_card_arg = ih_arg; 480 481 /* Enable card interrupt */ 482 r = hd64465_reg_read_1(cscier); 483 /* set level mode */ 484 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 485 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 486 hd64465_reg_write_1(cscier, r); 487 488 splx(s); 489 490 return (void *)ih_func; 491 } 492 493 void 494 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 495 { 496 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 497 int channel = ch->ch_channel; 498 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 499 int s = splhigh(); 500 u_int8_t r; 501 502 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 503 IPL_TTY); 504 505 /* Disable card interrupt */ 506 r = hd64465_reg_read_1(cscier); 507 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 508 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 509 hd64465_reg_write_1(cscier, r); 510 511 ch->ch_ih_card_func = 0; 512 513 splx(s); 514 } 515 516 /* 517 * Bus resources. 518 */ 519 int 520 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 521 struct pcmcia_mem_handle *pcmhp) 522 { 523 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 524 525 pcmhp->memt = ch->ch_memt; 526 pcmhp->addr = ch->ch_membase_addr; 527 pcmhp->memh = ch->ch_memh; 528 pcmhp->size = size; 529 pcmhp->realsize = size; 530 531 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 532 533 return (0); 534 } 535 536 void 537 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 538 struct pcmcia_mem_handle *pcmhp) 539 { 540 /* NO-OP */ 541 } 542 543 int 544 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 545 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 546 bus_size_t *offsetp, int *windowp) 547 { 548 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 549 struct hd64465pcmcia_window_cookie *cookie; 550 bus_addr_t ofs; 551 552 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 553 M_DEVBUF, M_NOWAIT); 554 KASSERT(cookie); 555 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 556 557 /* Address */ 558 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 559 cookie->wc_tag = ch->ch_memt; 560 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 561 size, &cookie->wc_handle) != 0) 562 goto bad; 563 564 *offsetp = card_addr; 565 cookie->wc_window = -1; 566 } else { 567 int window = card_addr / ch->ch_memsize; 568 KASSERT(window < MEMWIN_16M_MAX); 569 570 cookie->wc_tag = ch->ch_cmemt[window]; 571 ofs = card_addr - window * ch->ch_memsize; 572 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 573 &cookie->wc_handle) != 0) 574 goto bad; 575 576 /* XXX bogus. check window per common memory access. */ 577 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 578 *offsetp = ofs + 0x01000000; /* skip attribute area */ 579 cookie->wc_window = window; 580 } 581 cookie->wc_size = size; 582 *windowp = (int)cookie; 583 584 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 585 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 586 587 return (0); 588 bad: 589 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 590 free(cookie, M_DEVBUF); 591 592 return (1); 593 } 594 595 void 596 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 597 { 598 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 599 600 if (cookie->wc_window != -1) 601 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 602 cookie->wc_size); 603 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 604 free(cookie, M_DEVBUF); 605 } 606 607 int 608 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 609 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 610 { 611 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 612 613 if (start) { 614 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 615 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 616 return (1); 617 } 618 pcihp->addr = pcihp->ioh; 619 DPRINTF("map %#lx+%#lx\n", start, size); 620 } else { 621 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 622 ch->ch_iobase + ch->ch_iosize - 1, 623 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 624 DPRINTF("couldn't allocate %#lx\n", size); 625 return (1); 626 } 627 pcihp->flags = PCMCIA_IO_ALLOCATED; 628 } 629 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 630 631 pcihp->iot = ch->ch_iot; 632 pcihp->size = size; 633 634 return (0); 635 } 636 637 int 638 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 639 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 640 int *windowp) 641 { 642 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 643 #ifdef HD64465PCMCIA_DEBUG 644 static const char *width_names[] = { "auto", "io8", "io16" }; 645 #endif 646 647 __sh_set_bus_width(ch->ch_channel, width); 648 649 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 650 width_names[width]); 651 652 return (0); 653 } 654 655 void 656 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 657 struct pcmcia_io_handle *pcihp) 658 { 659 660 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 661 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 662 else 663 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 664 665 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 666 } 667 668 void 669 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 670 { 671 /* nothing to do */ 672 } 673 674 /* 675 * Enable/Disable 676 */ 677 void 678 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 679 { 680 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 681 int channel = ch->ch_channel; 682 bus_addr_t isr, gcr; 683 u_int8_t r; 684 int cardtype; 685 686 DPRINTF("enable channel %d\n", channel); 687 isr = HD64461_PCCISR(channel); 688 gcr = HD64461_PCCGCR(channel); 689 690 /* Set Common memory area #0. */ 691 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 692 693 /* Set the card type */ 694 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 695 696 r = hd64465_reg_read_1(gcr); 697 if (cardtype == PCMCIA_IFTYPE_IO) 698 r |= HD64461_PCC0GCR_P0PCCT; 699 else 700 r &= ~HD64461_PCC0GCR_P0PCCT; 701 hd64465_reg_write_1(gcr, r); 702 703 DPRINTF("OK.\n"); 704 } 705 706 void 707 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 708 { 709 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 710 int channel = ch->ch_channel; 711 712 /* dont' disable CSC interrupt */ 713 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 714 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 715 } 716 717 /* 718 * Card detect 719 */ 720 enum hd64465pcmcia_event_type 721 __detect_card(int channel) 722 { 723 u_int8_t r; 724 725 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 726 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 727 728 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 729 DPRINTF("remove\n"); 730 return EVENT_REMOVE; 731 } 732 if (r == 0) { 733 DPRINTF("insert\n"); 734 return EVENT_INSERT; 735 } 736 DPRINTF("transition\n"); 737 738 return (EVENT_NONE); 739 } 740 741 /* 742 * Memory window access ops. 743 */ 744 void 745 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 746 { 747 bus_addr_t a = HD64461_PCCGCR(channel); 748 u_int8_t r; 749 750 r = hd64465_reg_read_1(a); 751 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 752 753 switch (window) { 754 case MEMWIN_16M_COMMON_0: 755 break; 756 case MEMWIN_16M_COMMON_1: 757 r |= HD64461_PCCGCR_PA24; 758 break; 759 case MEMWIN_16M_COMMON_2: 760 r |= HD64461_PCCGCR_PA25; 761 break; 762 case MEMWIN_16M_COMMON_3: 763 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 764 break; 765 } 766 767 hd64465_reg_write_1(a, r); 768 } 769 770 /* 771 * SH interface. 772 */ 773 void 774 __sh_set_bus_width(int channel, int width) 775 { 776 u_int16_t r16; 777 778 r16 = _reg_read_2(SH4_BCR2); 779 #ifdef HD64465PCMCIA_DEBUG 780 dbg_bit_print_msg(r16, "BCR2"); 781 #endif 782 if (channel == 0) { 783 r16 &= ~((1 << 13)|(1 << 12)); 784 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 785 } else { 786 r16 &= ~((1 << 11)|(1 << 10)); 787 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 788 } 789 _reg_write_2(SH4_BCR2, r16); 790 } 791 792 vaddr_t 793 __sh_hd64465_map_2page(paddr_t pa) 794 { 795 static const u_int32_t mode[] = 796 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 797 vaddr_t va, v; 798 int i; 799 800 /* allocate kernel virtual */ 801 v = va = uvm_km_valloc(kernel_map, 0x03000000); 802 if (va == NULL) { 803 PRINTF("can't allocate virtual for paddr 0x%08x\n", 804 (unsigned)pa); 805 806 return (0); 807 } 808 809 /* map to physical addreess with specified memory type. */ 810 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 811 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 812 uvm_km_free(kernel_map, v, 0x03000000); 813 return (0); 814 } 815 } 816 817 return (v); 818 } 819 820 int 821 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 822 { 823 pt_entry_t *pte; 824 paddr_t epa; 825 826 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 827 ((sz & PAGE_MASK) == 0)); 828 829 epa = pa + sz; 830 while (pa < epa) { 831 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 832 pte = __pmap_kpte_lookup(va); 833 KDASSERT(pte); 834 *pte |= flags; /* PTEA PCMCIA assistant bit */ 835 sh_tlb_update(0, va, *pte); 836 pa += PAGE_SIZE; 837 va += PAGE_SIZE; 838 } 839 840 return (0); 841 } 842
Indexes created Fri Oct 03 02:09:57 GMT 2025