hd64465pcmcia.c revision 1.16
1 /* $NetBSD: hd64465pcmcia.c,v 1.16 2004/08/11 06:30:15 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.16 2004/08/11 06:30:15 mycroft Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/kthread.h> 47 #include <sys/boot_flag.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 #include <sh3/mmu.h> 60 61 #include <hpcsh/dev/hd64465/hd64465reg.h> 62 #include <hpcsh/dev/hd64465/hd64465var.h> 63 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64465PCMCIA_DEBUG 69 #define DPRINTF_ENABLE 70 #define DPRINTF_DEBUG hd64465pcmcia_debug 71 #endif 72 #include <machine/debug.h> 73 74 enum memory_window_16 { 75 MEMWIN_16M_COMMON_0, 76 MEMWIN_16M_COMMON_1, 77 MEMWIN_16M_COMMON_2, 78 MEMWIN_16M_COMMON_3, 79 }; 80 #define MEMWIN_16M_MAX 4 81 82 enum hd64465pcmcia_event_type { 83 EVENT_NONE, 84 EVENT_INSERT, 85 EVENT_REMOVE, 86 }; 87 #define EVENT_QUEUE_MAX 5 88 89 struct hd64465pcmcia_softc; /* forward declaration */ 90 91 struct hd64465pcmcia_window_cookie { 92 bus_space_tag_t wc_tag; 93 bus_space_handle_t wc_handle; 94 int wc_size; 95 int wc_window; 96 }; 97 98 struct hd64465pcmcia_channel { 99 struct hd64465pcmcia_softc *ch_parent; 100 struct device *ch_pcmcia; 101 int ch_channel; 102 103 /* memory space */ 104 bus_space_tag_t ch_memt; 105 bus_space_handle_t ch_memh; 106 bus_addr_t ch_membase_addr; 107 bus_size_t ch_memsize; 108 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 109 110 /* I/O space */ 111 bus_space_tag_t ch_iot; 112 bus_addr_t ch_iobase; 113 bus_size_t ch_iosize; 114 115 /* card interrupt */ 116 int (*ch_ih_card_func)(void *); 117 void *ch_ih_card_arg; 118 int ch_attached; 119 }; 120 121 struct hd64465pcmcia_event { 122 int __queued; 123 enum hd64465pcmcia_event_type pe_type; 124 struct hd64465pcmcia_channel *pe_ch; 125 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 126 }; 127 128 struct hd64465pcmcia_softc { 129 struct device sc_dev; 130 enum hd64465_module_id sc_module_id; 131 int sc_shutdown; 132 133 /* kv mapped Area 5, 6 */ 134 vaddr_t sc_area5; 135 vaddr_t sc_area6; 136 137 /* CSC event */ 138 struct proc *sc_event_thread; 139 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 140 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 141 142 struct hd64465pcmcia_channel sc_ch[2]; 143 }; 144 145 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *); 147 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *); 149 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 151 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 152 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 154 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *); 156 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *); 158 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 159 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 160 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 161 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 162 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 165 void *); 166 167 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 168 hd64465pcmcia_chip_mem_alloc, 169 hd64465pcmcia_chip_mem_free, 170 hd64465pcmcia_chip_mem_map, 171 hd64465pcmcia_chip_mem_unmap, 172 hd64465pcmcia_chip_io_alloc, 173 hd64465pcmcia_chip_io_free, 174 hd64465pcmcia_chip_io_map, 175 hd64465pcmcia_chip_io_unmap, 176 hd64465pcmcia_chip_intr_establish, 177 hd64465pcmcia_chip_intr_disestablish, 178 hd64465pcmcia_chip_socket_enable, 179 hd64465pcmcia_chip_socket_disable, 180 hd64465pcmcia_chip_socket_settype, 181 }; 182 183 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 184 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 185 STATIC int hd64465pcmcia_print(void *, const char *); 186 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 187 188 CFATTACH_DECL(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 189 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 190 191 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 192 /* hot plug */ 193 STATIC void hd64465pcmcia_create_event_thread(void *); 194 STATIC void hd64465pcmcia_event_thread(void *); 195 STATIC void __queue_event(struct hd64465pcmcia_channel *, 196 enum hd64465pcmcia_event_type); 197 /* interrupt handler */ 198 STATIC int hd64465pcmcia_intr(void *); 199 /* card status */ 200 STATIC enum hd64465pcmcia_event_type __detect_card(int); 201 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 202 /* bus width */ 203 STATIC void __sh_set_bus_width(int, int); 204 /* bus space access */ 205 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 206 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 207 208 #define DELAY_MS(x) delay((x) * 1000) 209 210 int 211 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 struct hd64465_attach_args *ha = aux; 214 215 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 216 } 217 218 void 219 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 220 { 221 struct hd64465_attach_args *ha = aux; 222 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 223 224 sc->sc_module_id = ha->ha_module_id; 225 226 printf("\n"); 227 228 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 229 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 230 231 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) { 232 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 233 if (sc->sc_area5) 234 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000); 235 if (sc->sc_area6) 236 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000); 237 238 return; 239 } 240 241 /* Channel 0/1 common CSC event queue */ 242 SIMPLEQ_INIT (&sc->sc_event_head); 243 kthread_create(hd64465pcmcia_create_event_thread, sc); 244 245 hd64465pcmcia_attach_channel(sc, 0); 246 hd64465pcmcia_attach_channel(sc, 1); 247 } 248 249 void 250 hd64465pcmcia_create_event_thread(void *arg) 251 { 252 struct hd64465pcmcia_softc *sc = arg; 253 int error; 254 255 error = kthread_create1(hd64465pcmcia_event_thread, sc, 256 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 257 258 KASSERT(error == 0); 259 } 260 261 void 262 hd64465pcmcia_event_thread(void *arg) 263 { 264 struct hd64465pcmcia_softc *sc = arg; 265 struct hd64465pcmcia_event *pe; 266 int s; 267 268 while (!sc->sc_shutdown) { 269 tsleep(sc, PWAIT, "CSC wait", 0); 270 s = splhigh(); 271 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 272 splx(s); 273 switch (pe->pe_type) { 274 default: 275 printf("%s: unknown event.\n", __FUNCTION__); 276 break; 277 case EVENT_INSERT: 278 DPRINTF("insert event.\n"); 279 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 280 break; 281 case EVENT_REMOVE: 282 DPRINTF("remove event.\n"); 283 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 284 DETACH_FORCE); 285 break; 286 } 287 s = splhigh(); 288 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 289 pe->__queued = 0; 290 } 291 splx(s); 292 } 293 /* NOTREACHED */ 294 } 295 296 int 297 hd64465pcmcia_print(void *arg, const char *pnp) 298 { 299 300 if (pnp) 301 aprint_normal("pcmcia at %s", pnp); 302 303 return (UNCONF); 304 } 305 306 int 307 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 308 { 309 struct pcmciabus_attach_args *paa = aux; 310 struct hd64465pcmcia_channel *ch = 311 (struct hd64465pcmcia_channel *)paa->pch; 312 313 if (ch->ch_channel == 0) { 314 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 315 PCMCIABUSCF_CONTROLLER_DEFAULT && 316 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 317 return 0; 318 } else { 319 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 320 PCMCIABUSCF_CONTROLLER_DEFAULT && 321 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 322 return 0; 323 } 324 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 325 326 return (config_match(parent, cf, aux)); 327 } 328 329 void 330 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 331 { 332 struct device *parent = (struct device *)sc; 333 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 334 struct pcmciabus_attach_args paa; 335 bus_addr_t baseaddr; 336 u_int8_t r; 337 int i; 338 339 ch->ch_parent = sc; 340 ch->ch_channel = channel; 341 342 /* 343 * Continuous 16-MB Area Mode 344 */ 345 /* set Continuous 16-MB Area Mode */ 346 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 347 r &= ~HD64461_PCCGCR_MMOD; 348 r |= HD64461_PCCGCR_MMOD_16M; 349 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 350 351 /* Attibute/Common memory extent */ 352 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 353 354 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 355 baseaddr, 0x01000000); /* 16MB */ 356 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 357 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 358 359 /* Common memory space extent */ 360 ch->ch_memsize = 0x01000000; 361 for (i = 0; i < MEMWIN_16M_MAX; i++) { 362 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 363 baseaddr + 0x01000000, ch->ch_memsize); 364 } 365 366 /* I/O port extent */ 367 ch->ch_iobase = 0; 368 ch->ch_iosize = 0x01000000; 369 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 370 baseaddr + 0x01000000 * 2, ch->ch_iosize); 371 372 /* Interrupt */ 373 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 374 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 375 376 paa.paa_busname = "pcmcia"; 377 paa.pch = (pcmcia_chipset_handle_t)ch; 378 paa.iobase = ch->ch_iobase; 379 paa.iosize = ch->ch_iosize; 380 381 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 382 hd64465pcmcia_submatch); 383 384 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 385 ch->ch_attached = 1; 386 pcmcia_card_attach(ch->ch_pcmcia); 387 } 388 } 389 390 int 391 hd64465pcmcia_intr(void *arg) 392 { 393 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 394 u_int32_t cscr; 395 u_int8_t r; 396 int ret = 0; 397 398 cscr = HD64461_PCCCSCR(ch->ch_channel); 399 r = hd64465_reg_read_1(cscr); 400 401 /* clear interrtupt (don't change power switch select) */ 402 hd64465_reg_write_1(cscr, r & ~0x40); 403 404 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 405 if (ch->ch_ih_card_func) { 406 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 407 } else { 408 DPRINTF("spurious IREQ interrupt.\n"); 409 } 410 } 411 412 if (r & HD64461_PCC0CSCR_P0CDC) 413 __queue_event(ch, __detect_card(ch->ch_channel)); 414 415 return (ret); 416 } 417 418 void 419 __queue_event(struct hd64465pcmcia_channel *ch, 420 enum hd64465pcmcia_event_type type) 421 { 422 struct hd64465pcmcia_event *pe, *pool; 423 struct hd64465pcmcia_softc *sc = ch->ch_parent; 424 int i; 425 int s = splhigh(); 426 427 if (type == EVENT_NONE) 428 goto out; 429 430 pe = 0; 431 pool = sc->sc_event_pool; 432 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 433 if (!pool[i].__queued) { 434 pe = &pool[i]; 435 break; 436 } 437 } 438 439 if (pe == 0) { 440 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 441 EVENT_QUEUE_MAX); 442 goto out; 443 } 444 445 if ((ch->ch_attached && (type == EVENT_INSERT)) || 446 (!ch->ch_attached && (type == EVENT_REMOVE))) { 447 DPRINTF("spurious CSC interrupt.\n"); 448 goto out; 449 } 450 451 ch->ch_attached = (type == EVENT_INSERT); 452 pe->__queued = 1; 453 pe->pe_type = type; 454 pe->pe_ch = ch; 455 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 456 wakeup(sc); 457 out: 458 splx(s); 459 } 460 461 /* 462 * Interface for pcmcia driver. 463 */ 464 /* 465 * Interrupt. 466 */ 467 void * 468 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 469 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 470 { 471 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 472 int channel = ch->ch_channel; 473 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 474 u_int8_t r; 475 int s = splhigh(); 476 477 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 478 ipl); 479 480 ch->ch_ih_card_func = ih_func; 481 ch->ch_ih_card_arg = ih_arg; 482 483 /* Enable card interrupt */ 484 r = hd64465_reg_read_1(cscier); 485 /* set level mode */ 486 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 487 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 488 hd64465_reg_write_1(cscier, r); 489 490 splx(s); 491 492 return (void *)ih_func; 493 } 494 495 void 496 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 497 { 498 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 499 int channel = ch->ch_channel; 500 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 501 int s = splhigh(); 502 u_int8_t r; 503 504 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 505 IPL_TTY); 506 507 /* Disable card interrupt */ 508 r = hd64465_reg_read_1(cscier); 509 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 510 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 511 hd64465_reg_write_1(cscier, r); 512 513 ch->ch_ih_card_func = 0; 514 515 splx(s); 516 } 517 518 /* 519 * Bus resources. 520 */ 521 int 522 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 523 struct pcmcia_mem_handle *pcmhp) 524 { 525 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 526 527 pcmhp->memt = ch->ch_memt; 528 pcmhp->addr = ch->ch_membase_addr; 529 pcmhp->memh = ch->ch_memh; 530 pcmhp->size = size; 531 pcmhp->realsize = size; 532 533 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 534 535 return (0); 536 } 537 538 void 539 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 540 struct pcmcia_mem_handle *pcmhp) 541 { 542 /* NO-OP */ 543 } 544 545 int 546 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 547 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 548 bus_size_t *offsetp, int *windowp) 549 { 550 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 551 struct hd64465pcmcia_window_cookie *cookie; 552 bus_addr_t ofs; 553 554 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 555 M_DEVBUF, M_NOWAIT); 556 KASSERT(cookie); 557 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 558 559 /* Address */ 560 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 561 cookie->wc_tag = ch->ch_memt; 562 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 563 size, &cookie->wc_handle) != 0) 564 goto bad; 565 566 *offsetp = card_addr; 567 cookie->wc_window = -1; 568 } else { 569 int window = card_addr / ch->ch_memsize; 570 KASSERT(window < MEMWIN_16M_MAX); 571 572 cookie->wc_tag = ch->ch_cmemt[window]; 573 ofs = card_addr - window * ch->ch_memsize; 574 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 575 &cookie->wc_handle) != 0) 576 goto bad; 577 578 /* XXX bogus. check window per common memory access. */ 579 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 580 *offsetp = ofs + 0x01000000; /* skip attribute area */ 581 cookie->wc_window = window; 582 } 583 cookie->wc_size = size; 584 *windowp = (int)cookie; 585 586 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 587 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 588 589 return (0); 590 bad: 591 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 592 free(cookie, M_DEVBUF); 593 594 return (1); 595 } 596 597 void 598 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 599 { 600 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 601 602 if (cookie->wc_window != -1) 603 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 604 cookie->wc_size); 605 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 606 free(cookie, M_DEVBUF); 607 } 608 609 int 610 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 611 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 612 { 613 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 614 615 if (start) { 616 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 617 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 618 return (1); 619 } 620 pcihp->addr = pcihp->ioh; 621 DPRINTF("map %#lx+%#lx\n", start, size); 622 } else { 623 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 624 ch->ch_iobase + ch->ch_iosize - 1, 625 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 626 DPRINTF("couldn't allocate %#lx\n", size); 627 return (1); 628 } 629 pcihp->flags = PCMCIA_IO_ALLOCATED; 630 } 631 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 632 633 pcihp->iot = ch->ch_iot; 634 pcihp->size = size; 635 636 return (0); 637 } 638 639 int 640 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 641 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 642 int *windowp) 643 { 644 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 645 #ifdef HD64465PCMCIA_DEBUG 646 static const char *width_names[] = { "auto", "io8", "io16" }; 647 #endif 648 649 __sh_set_bus_width(ch->ch_channel, width); 650 651 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 652 width_names[width]); 653 654 return (0); 655 } 656 657 void 658 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 659 struct pcmcia_io_handle *pcihp) 660 { 661 662 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 663 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 664 else 665 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 666 667 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 668 } 669 670 void 671 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 672 { 673 /* nothing to do */ 674 } 675 676 /* 677 * Enable/Disable 678 */ 679 void 680 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 681 { 682 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 683 int channel = ch->ch_channel; 684 bus_addr_t gcr; 685 u_int8_t r; 686 687 DPRINTF("enable channel %d\n", channel); 688 gcr = HD64461_PCCGCR(channel); 689 690 r = hd64465_reg_read_1(gcr); 691 r &= ~HD64461_PCC0GCR_P0PCCT; 692 hd64465_reg_write_1(gcr, r); 693 694 /* Set Common memory area #0. */ 695 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 696 697 DPRINTF("OK.\n"); 698 } 699 700 void 701 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 702 { 703 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 704 int channel = ch->ch_channel; 705 bus_addr_t gcr; 706 u_int8_t r; 707 708 DPRINTF("settype channel %d\n", channel); 709 gcr = HD64461_PCCGCR(channel); 710 711 /* Set the card type */ 712 r = hd64465_reg_read_1(gcr); 713 if (type == PCMCIA_IFTYPE_IO) 714 r |= HD64461_PCC0GCR_P0PCCT; 715 else 716 r &= ~HD64461_PCC0GCR_P0PCCT; 717 hd64465_reg_write_1(gcr, r); 718 719 DPRINTF("OK.\n"); 720 } 721 722 void 723 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 724 { 725 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 726 int channel = ch->ch_channel; 727 728 /* dont' disable CSC interrupt */ 729 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 730 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 731 } 732 733 /* 734 * Card detect 735 */ 736 enum hd64465pcmcia_event_type 737 __detect_card(int channel) 738 { 739 u_int8_t r; 740 741 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 742 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 743 744 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 745 DPRINTF("remove\n"); 746 return EVENT_REMOVE; 747 } 748 if (r == 0) { 749 DPRINTF("insert\n"); 750 return EVENT_INSERT; 751 } 752 DPRINTF("transition\n"); 753 754 return (EVENT_NONE); 755 } 756 757 /* 758 * Memory window access ops. 759 */ 760 void 761 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 762 { 763 bus_addr_t a = HD64461_PCCGCR(channel); 764 u_int8_t r; 765 766 r = hd64465_reg_read_1(a); 767 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 768 769 switch (window) { 770 case MEMWIN_16M_COMMON_0: 771 break; 772 case MEMWIN_16M_COMMON_1: 773 r |= HD64461_PCCGCR_PA24; 774 break; 775 case MEMWIN_16M_COMMON_2: 776 r |= HD64461_PCCGCR_PA25; 777 break; 778 case MEMWIN_16M_COMMON_3: 779 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 780 break; 781 } 782 783 hd64465_reg_write_1(a, r); 784 } 785 786 /* 787 * SH interface. 788 */ 789 void 790 __sh_set_bus_width(int channel, int width) 791 { 792 u_int16_t r16; 793 794 r16 = _reg_read_2(SH4_BCR2); 795 #ifdef HD64465PCMCIA_DEBUG 796 dbg_bit_print_msg(r16, "BCR2"); 797 #endif 798 if (channel == 0) { 799 r16 &= ~((1 << 13)|(1 << 12)); 800 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 801 } else { 802 r16 &= ~((1 << 11)|(1 << 10)); 803 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 804 } 805 _reg_write_2(SH4_BCR2, r16); 806 } 807 808 vaddr_t 809 __sh_hd64465_map_2page(paddr_t pa) 810 { 811 static const u_int32_t mode[] = 812 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 813 vaddr_t va, v; 814 int i; 815 816 /* allocate kernel virtual */ 817 v = va = uvm_km_valloc(kernel_map, 0x03000000); 818 if (va == 0) { 819 PRINTF("can't allocate virtual for paddr 0x%08x\n", 820 (unsigned)pa); 821 822 return (0); 823 } 824 825 /* map to physical addreess with specified memory type. */ 826 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 827 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 828 uvm_km_free(kernel_map, v, 0x03000000); 829 return (0); 830 } 831 } 832 833 return (v); 834 } 835 836 int 837 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 838 { 839 pt_entry_t *pte; 840 paddr_t epa; 841 842 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 843 ((sz & PAGE_MASK) == 0)); 844 845 epa = pa + sz; 846 while (pa < epa) { 847 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 848 pte = __pmap_kpte_lookup(va); 849 KDASSERT(pte); 850 *pte |= flags; /* PTEA PCMCIA assistant bit */ 851 sh_tlb_update(0, va, *pte); 852 pa += PAGE_SIZE; 853 va += PAGE_SIZE; 854 } 855 856 return (0); 857 } 858
Indexes created Fri Oct 03 02:09:57 GMT 2025