hd64465pcmcia.c revision 1.17
1 /* $NetBSD: hd64465pcmcia.c,v 1.17 2005/04/01 11:59:29 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.17 2005/04/01 11:59:29 yamt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/kthread.h> 47 #include <sys/boot_flag.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 #include <sh3/mmu.h> 60 61 #include <hpcsh/dev/hd64465/hd64465reg.h> 62 #include <hpcsh/dev/hd64465/hd64465var.h> 63 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64465PCMCIA_DEBUG 69 #define DPRINTF_ENABLE 70 #define DPRINTF_DEBUG hd64465pcmcia_debug 71 #endif 72 #include <machine/debug.h> 73 74 enum memory_window_16 { 75 MEMWIN_16M_COMMON_0, 76 MEMWIN_16M_COMMON_1, 77 MEMWIN_16M_COMMON_2, 78 MEMWIN_16M_COMMON_3, 79 }; 80 #define MEMWIN_16M_MAX 4 81 82 enum hd64465pcmcia_event_type { 83 EVENT_NONE, 84 EVENT_INSERT, 85 EVENT_REMOVE, 86 }; 87 #define EVENT_QUEUE_MAX 5 88 89 struct hd64465pcmcia_softc; /* forward declaration */ 90 91 struct hd64465pcmcia_window_cookie { 92 bus_space_tag_t wc_tag; 93 bus_space_handle_t wc_handle; 94 int wc_size; 95 int wc_window; 96 }; 97 98 struct hd64465pcmcia_channel { 99 struct hd64465pcmcia_softc *ch_parent; 100 struct device *ch_pcmcia; 101 int ch_channel; 102 103 /* memory space */ 104 bus_space_tag_t ch_memt; 105 bus_space_handle_t ch_memh; 106 bus_addr_t ch_membase_addr; 107 bus_size_t ch_memsize; 108 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 109 110 /* I/O space */ 111 bus_space_tag_t ch_iot; 112 bus_addr_t ch_iobase; 113 bus_size_t ch_iosize; 114 115 /* card interrupt */ 116 int (*ch_ih_card_func)(void *); 117 void *ch_ih_card_arg; 118 int ch_attached; 119 }; 120 121 struct hd64465pcmcia_event { 122 int __queued; 123 enum hd64465pcmcia_event_type pe_type; 124 struct hd64465pcmcia_channel *pe_ch; 125 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 126 }; 127 128 struct hd64465pcmcia_softc { 129 struct device sc_dev; 130 enum hd64465_module_id sc_module_id; 131 int sc_shutdown; 132 133 /* kv mapped Area 5, 6 */ 134 vaddr_t sc_area5; 135 vaddr_t sc_area6; 136 137 /* CSC event */ 138 struct proc *sc_event_thread; 139 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 140 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 141 142 struct hd64465pcmcia_channel sc_ch[2]; 143 }; 144 145 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *); 147 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *); 149 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 151 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 152 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 154 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *); 156 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *); 158 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 159 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 160 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 161 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 162 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 165 void *); 166 167 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 168 hd64465pcmcia_chip_mem_alloc, 169 hd64465pcmcia_chip_mem_free, 170 hd64465pcmcia_chip_mem_map, 171 hd64465pcmcia_chip_mem_unmap, 172 hd64465pcmcia_chip_io_alloc, 173 hd64465pcmcia_chip_io_free, 174 hd64465pcmcia_chip_io_map, 175 hd64465pcmcia_chip_io_unmap, 176 hd64465pcmcia_chip_intr_establish, 177 hd64465pcmcia_chip_intr_disestablish, 178 hd64465pcmcia_chip_socket_enable, 179 hd64465pcmcia_chip_socket_disable, 180 hd64465pcmcia_chip_socket_settype, 181 }; 182 183 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 184 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 185 STATIC int hd64465pcmcia_print(void *, const char *); 186 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 187 188 CFATTACH_DECL(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 189 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 190 191 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 192 /* hot plug */ 193 STATIC void hd64465pcmcia_create_event_thread(void *); 194 STATIC void hd64465pcmcia_event_thread(void *); 195 STATIC void __queue_event(struct hd64465pcmcia_channel *, 196 enum hd64465pcmcia_event_type); 197 /* interrupt handler */ 198 STATIC int hd64465pcmcia_intr(void *); 199 /* card status */ 200 STATIC enum hd64465pcmcia_event_type __detect_card(int); 201 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 202 /* bus width */ 203 STATIC void __sh_set_bus_width(int, int); 204 /* bus space access */ 205 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 206 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 207 208 #define DELAY_MS(x) delay((x) * 1000) 209 210 int 211 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 struct hd64465_attach_args *ha = aux; 214 215 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 216 } 217 218 void 219 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 220 { 221 struct hd64465_attach_args *ha = aux; 222 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 223 224 sc->sc_module_id = ha->ha_module_id; 225 226 printf("\n"); 227 228 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 229 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 230 231 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) { 232 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 233 if (sc->sc_area5) 234 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000, 235 UVM_KMF_VAONLY); 236 if (sc->sc_area6) 237 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000, 238 UVM_KMF_VAONLY); 239 240 return; 241 } 242 243 /* Channel 0/1 common CSC event queue */ 244 SIMPLEQ_INIT (&sc->sc_event_head); 245 kthread_create(hd64465pcmcia_create_event_thread, sc); 246 247 hd64465pcmcia_attach_channel(sc, 0); 248 hd64465pcmcia_attach_channel(sc, 1); 249 } 250 251 void 252 hd64465pcmcia_create_event_thread(void *arg) 253 { 254 struct hd64465pcmcia_softc *sc = arg; 255 int error; 256 257 error = kthread_create1(hd64465pcmcia_event_thread, sc, 258 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 259 260 KASSERT(error == 0); 261 } 262 263 void 264 hd64465pcmcia_event_thread(void *arg) 265 { 266 struct hd64465pcmcia_softc *sc = arg; 267 struct hd64465pcmcia_event *pe; 268 int s; 269 270 while (!sc->sc_shutdown) { 271 tsleep(sc, PWAIT, "CSC wait", 0); 272 s = splhigh(); 273 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 274 splx(s); 275 switch (pe->pe_type) { 276 default: 277 printf("%s: unknown event.\n", __FUNCTION__); 278 break; 279 case EVENT_INSERT: 280 DPRINTF("insert event.\n"); 281 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 282 break; 283 case EVENT_REMOVE: 284 DPRINTF("remove event.\n"); 285 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 286 DETACH_FORCE); 287 break; 288 } 289 s = splhigh(); 290 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 291 pe->__queued = 0; 292 } 293 splx(s); 294 } 295 /* NOTREACHED */ 296 } 297 298 int 299 hd64465pcmcia_print(void *arg, const char *pnp) 300 { 301 302 if (pnp) 303 aprint_normal("pcmcia at %s", pnp); 304 305 return (UNCONF); 306 } 307 308 int 309 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 310 { 311 struct pcmciabus_attach_args *paa = aux; 312 struct hd64465pcmcia_channel *ch = 313 (struct hd64465pcmcia_channel *)paa->pch; 314 315 if (ch->ch_channel == 0) { 316 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 317 PCMCIABUSCF_CONTROLLER_DEFAULT && 318 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 319 return 0; 320 } else { 321 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 322 PCMCIABUSCF_CONTROLLER_DEFAULT && 323 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 324 return 0; 325 } 326 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 327 328 return (config_match(parent, cf, aux)); 329 } 330 331 void 332 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 333 { 334 struct device *parent = (struct device *)sc; 335 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 336 struct pcmciabus_attach_args paa; 337 bus_addr_t baseaddr; 338 u_int8_t r; 339 int i; 340 341 ch->ch_parent = sc; 342 ch->ch_channel = channel; 343 344 /* 345 * Continuous 16-MB Area Mode 346 */ 347 /* set Continuous 16-MB Area Mode */ 348 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 349 r &= ~HD64461_PCCGCR_MMOD; 350 r |= HD64461_PCCGCR_MMOD_16M; 351 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 352 353 /* Attibute/Common memory extent */ 354 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 355 356 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 357 baseaddr, 0x01000000); /* 16MB */ 358 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 359 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 360 361 /* Common memory space extent */ 362 ch->ch_memsize = 0x01000000; 363 for (i = 0; i < MEMWIN_16M_MAX; i++) { 364 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 365 baseaddr + 0x01000000, ch->ch_memsize); 366 } 367 368 /* I/O port extent */ 369 ch->ch_iobase = 0; 370 ch->ch_iosize = 0x01000000; 371 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 372 baseaddr + 0x01000000 * 2, ch->ch_iosize); 373 374 /* Interrupt */ 375 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 376 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 377 378 paa.paa_busname = "pcmcia"; 379 paa.pch = (pcmcia_chipset_handle_t)ch; 380 paa.iobase = ch->ch_iobase; 381 paa.iosize = ch->ch_iosize; 382 383 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 384 hd64465pcmcia_submatch); 385 386 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 387 ch->ch_attached = 1; 388 pcmcia_card_attach(ch->ch_pcmcia); 389 } 390 } 391 392 int 393 hd64465pcmcia_intr(void *arg) 394 { 395 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 396 u_int32_t cscr; 397 u_int8_t r; 398 int ret = 0; 399 400 cscr = HD64461_PCCCSCR(ch->ch_channel); 401 r = hd64465_reg_read_1(cscr); 402 403 /* clear interrtupt (don't change power switch select) */ 404 hd64465_reg_write_1(cscr, r & ~0x40); 405 406 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 407 if (ch->ch_ih_card_func) { 408 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 409 } else { 410 DPRINTF("spurious IREQ interrupt.\n"); 411 } 412 } 413 414 if (r & HD64461_PCC0CSCR_P0CDC) 415 __queue_event(ch, __detect_card(ch->ch_channel)); 416 417 return (ret); 418 } 419 420 void 421 __queue_event(struct hd64465pcmcia_channel *ch, 422 enum hd64465pcmcia_event_type type) 423 { 424 struct hd64465pcmcia_event *pe, *pool; 425 struct hd64465pcmcia_softc *sc = ch->ch_parent; 426 int i; 427 int s = splhigh(); 428 429 if (type == EVENT_NONE) 430 goto out; 431 432 pe = 0; 433 pool = sc->sc_event_pool; 434 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 435 if (!pool[i].__queued) { 436 pe = &pool[i]; 437 break; 438 } 439 } 440 441 if (pe == 0) { 442 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 443 EVENT_QUEUE_MAX); 444 goto out; 445 } 446 447 if ((ch->ch_attached && (type == EVENT_INSERT)) || 448 (!ch->ch_attached && (type == EVENT_REMOVE))) { 449 DPRINTF("spurious CSC interrupt.\n"); 450 goto out; 451 } 452 453 ch->ch_attached = (type == EVENT_INSERT); 454 pe->__queued = 1; 455 pe->pe_type = type; 456 pe->pe_ch = ch; 457 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 458 wakeup(sc); 459 out: 460 splx(s); 461 } 462 463 /* 464 * Interface for pcmcia driver. 465 */ 466 /* 467 * Interrupt. 468 */ 469 void * 470 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 471 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 472 { 473 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 474 int channel = ch->ch_channel; 475 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 476 u_int8_t r; 477 int s = splhigh(); 478 479 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 480 ipl); 481 482 ch->ch_ih_card_func = ih_func; 483 ch->ch_ih_card_arg = ih_arg; 484 485 /* Enable card interrupt */ 486 r = hd64465_reg_read_1(cscier); 487 /* set level mode */ 488 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 489 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 490 hd64465_reg_write_1(cscier, r); 491 492 splx(s); 493 494 return (void *)ih_func; 495 } 496 497 void 498 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 499 { 500 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 501 int channel = ch->ch_channel; 502 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 503 int s = splhigh(); 504 u_int8_t r; 505 506 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 507 IPL_TTY); 508 509 /* Disable card interrupt */ 510 r = hd64465_reg_read_1(cscier); 511 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 512 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 513 hd64465_reg_write_1(cscier, r); 514 515 ch->ch_ih_card_func = 0; 516 517 splx(s); 518 } 519 520 /* 521 * Bus resources. 522 */ 523 int 524 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 525 struct pcmcia_mem_handle *pcmhp) 526 { 527 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 528 529 pcmhp->memt = ch->ch_memt; 530 pcmhp->addr = ch->ch_membase_addr; 531 pcmhp->memh = ch->ch_memh; 532 pcmhp->size = size; 533 pcmhp->realsize = size; 534 535 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 536 537 return (0); 538 } 539 540 void 541 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 542 struct pcmcia_mem_handle *pcmhp) 543 { 544 /* NO-OP */ 545 } 546 547 int 548 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 549 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 550 bus_size_t *offsetp, int *windowp) 551 { 552 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 553 struct hd64465pcmcia_window_cookie *cookie; 554 bus_addr_t ofs; 555 556 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 557 M_DEVBUF, M_NOWAIT); 558 KASSERT(cookie); 559 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 560 561 /* Address */ 562 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 563 cookie->wc_tag = ch->ch_memt; 564 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 565 size, &cookie->wc_handle) != 0) 566 goto bad; 567 568 *offsetp = card_addr; 569 cookie->wc_window = -1; 570 } else { 571 int window = card_addr / ch->ch_memsize; 572 KASSERT(window < MEMWIN_16M_MAX); 573 574 cookie->wc_tag = ch->ch_cmemt[window]; 575 ofs = card_addr - window * ch->ch_memsize; 576 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 577 &cookie->wc_handle) != 0) 578 goto bad; 579 580 /* XXX bogus. check window per common memory access. */ 581 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 582 *offsetp = ofs + 0x01000000; /* skip attribute area */ 583 cookie->wc_window = window; 584 } 585 cookie->wc_size = size; 586 *windowp = (int)cookie; 587 588 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 589 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 590 591 return (0); 592 bad: 593 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 594 free(cookie, M_DEVBUF); 595 596 return (1); 597 } 598 599 void 600 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 601 { 602 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 603 604 if (cookie->wc_window != -1) 605 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 606 cookie->wc_size); 607 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 608 free(cookie, M_DEVBUF); 609 } 610 611 int 612 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 613 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 614 { 615 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 616 617 if (start) { 618 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 619 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 620 return (1); 621 } 622 pcihp->addr = pcihp->ioh; 623 DPRINTF("map %#lx+%#lx\n", start, size); 624 } else { 625 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 626 ch->ch_iobase + ch->ch_iosize - 1, 627 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 628 DPRINTF("couldn't allocate %#lx\n", size); 629 return (1); 630 } 631 pcihp->flags = PCMCIA_IO_ALLOCATED; 632 } 633 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 634 635 pcihp->iot = ch->ch_iot; 636 pcihp->size = size; 637 638 return (0); 639 } 640 641 int 642 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 643 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 644 int *windowp) 645 { 646 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 647 #ifdef HD64465PCMCIA_DEBUG 648 static const char *width_names[] = { "auto", "io8", "io16" }; 649 #endif 650 651 __sh_set_bus_width(ch->ch_channel, width); 652 653 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 654 width_names[width]); 655 656 return (0); 657 } 658 659 void 660 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 661 struct pcmcia_io_handle *pcihp) 662 { 663 664 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 665 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 666 else 667 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 668 669 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 670 } 671 672 void 673 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 674 { 675 /* nothing to do */ 676 } 677 678 /* 679 * Enable/Disable 680 */ 681 void 682 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 683 { 684 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 685 int channel = ch->ch_channel; 686 bus_addr_t gcr; 687 u_int8_t r; 688 689 DPRINTF("enable channel %d\n", channel); 690 gcr = HD64461_PCCGCR(channel); 691 692 r = hd64465_reg_read_1(gcr); 693 r &= ~HD64461_PCC0GCR_P0PCCT; 694 hd64465_reg_write_1(gcr, r); 695 696 /* Set Common memory area #0. */ 697 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 698 699 DPRINTF("OK.\n"); 700 } 701 702 void 703 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 704 { 705 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 706 int channel = ch->ch_channel; 707 bus_addr_t gcr; 708 u_int8_t r; 709 710 DPRINTF("settype channel %d\n", channel); 711 gcr = HD64461_PCCGCR(channel); 712 713 /* Set the card type */ 714 r = hd64465_reg_read_1(gcr); 715 if (type == PCMCIA_IFTYPE_IO) 716 r |= HD64461_PCC0GCR_P0PCCT; 717 else 718 r &= ~HD64461_PCC0GCR_P0PCCT; 719 hd64465_reg_write_1(gcr, r); 720 721 DPRINTF("OK.\n"); 722 } 723 724 void 725 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 726 { 727 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 728 int channel = ch->ch_channel; 729 730 /* dont' disable CSC interrupt */ 731 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 732 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 733 } 734 735 /* 736 * Card detect 737 */ 738 enum hd64465pcmcia_event_type 739 __detect_card(int channel) 740 { 741 u_int8_t r; 742 743 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 744 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 745 746 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 747 DPRINTF("remove\n"); 748 return EVENT_REMOVE; 749 } 750 if (r == 0) { 751 DPRINTF("insert\n"); 752 return EVENT_INSERT; 753 } 754 DPRINTF("transition\n"); 755 756 return (EVENT_NONE); 757 } 758 759 /* 760 * Memory window access ops. 761 */ 762 void 763 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 764 { 765 bus_addr_t a = HD64461_PCCGCR(channel); 766 u_int8_t r; 767 768 r = hd64465_reg_read_1(a); 769 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 770 771 switch (window) { 772 case MEMWIN_16M_COMMON_0: 773 break; 774 case MEMWIN_16M_COMMON_1: 775 r |= HD64461_PCCGCR_PA24; 776 break; 777 case MEMWIN_16M_COMMON_2: 778 r |= HD64461_PCCGCR_PA25; 779 break; 780 case MEMWIN_16M_COMMON_3: 781 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 782 break; 783 } 784 785 hd64465_reg_write_1(a, r); 786 } 787 788 /* 789 * SH interface. 790 */ 791 void 792 __sh_set_bus_width(int channel, int width) 793 { 794 u_int16_t r16; 795 796 r16 = _reg_read_2(SH4_BCR2); 797 #ifdef HD64465PCMCIA_DEBUG 798 dbg_bit_print_msg(r16, "BCR2"); 799 #endif 800 if (channel == 0) { 801 r16 &= ~((1 << 13)|(1 << 12)); 802 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 803 } else { 804 r16 &= ~((1 << 11)|(1 << 10)); 805 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 806 } 807 _reg_write_2(SH4_BCR2, r16); 808 } 809 810 vaddr_t 811 __sh_hd64465_map_2page(paddr_t pa) 812 { 813 static const u_int32_t mode[] = 814 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 815 vaddr_t va, v; 816 int i; 817 818 /* allocate kernel virtual */ 819 v = va = uvm_km_alloc(kernel_map, 0x03000000, 0, UVM_KMF_VAONLY); 820 if (va == 0) { 821 PRINTF("can't allocate virtual for paddr 0x%08x\n", 822 (unsigned)pa); 823 824 return (0); 825 } 826 827 /* map to physical addreess with specified memory type. */ 828 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 829 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 830 pmap_kremove(v, 0x03000000); 831 uvm_km_free(kernel_map, v, 0x03000000, UVM_KMF_VAONLY); 832 return (0); 833 } 834 } 835 836 return (v); 837 } 838 839 int 840 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 841 { 842 pt_entry_t *pte; 843 paddr_t epa; 844 845 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 846 ((sz & PAGE_MASK) == 0)); 847 848 epa = pa + sz; 849 while (pa < epa) { 850 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 851 pte = __pmap_kpte_lookup(va); 852 KDASSERT(pte); 853 *pte |= flags; /* PTEA PCMCIA assistant bit */ 854 sh_tlb_update(0, va, *pte); 855 pa += PAGE_SIZE; 856 va += PAGE_SIZE; 857 } 858 859 return (0); 860 } 861
Indexes created Fri Oct 03 02:09:57 GMT 2025