hd64465pcmcia.c revision 1.22
1 /* $NetBSD: hd64465pcmcia.c,v 1.22 2007/07/17 11:16:14 he Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.22 2007/07/17 11:16:14 he Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/kthread.h> 47 #include <sys/boot_flag.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/pcmcia/pcmciareg.h> 55 #include <dev/pcmcia/pcmciavar.h> 56 #include <dev/pcmcia/pcmciachip.h> 57 58 #include <sh3/bscreg.h> 59 #include <sh3/mmu.h> 60 61 #include <hpcsh/dev/hd64465/hd64465reg.h> 62 #include <hpcsh/dev/hd64465/hd64465var.h> 63 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 64 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 65 66 #include "locators.h" 67 68 #ifdef HD64465PCMCIA_DEBUG 69 #define DPRINTF_ENABLE 70 #define DPRINTF_DEBUG hd64465pcmcia_debug 71 #endif 72 #include <machine/debug.h> 73 74 enum memory_window_16 { 75 MEMWIN_16M_COMMON_0, 76 MEMWIN_16M_COMMON_1, 77 MEMWIN_16M_COMMON_2, 78 MEMWIN_16M_COMMON_3, 79 }; 80 #define MEMWIN_16M_MAX 4 81 82 enum hd64465pcmcia_event_type { 83 EVENT_NONE, 84 EVENT_INSERT, 85 EVENT_REMOVE, 86 }; 87 #define EVENT_QUEUE_MAX 5 88 89 struct hd64465pcmcia_softc; /* forward declaration */ 90 91 struct hd64465pcmcia_window_cookie { 92 bus_space_tag_t wc_tag; 93 bus_space_handle_t wc_handle; 94 int wc_size; 95 int wc_window; 96 }; 97 98 struct hd64465pcmcia_channel { 99 struct hd64465pcmcia_softc *ch_parent; 100 struct device *ch_pcmcia; 101 int ch_channel; 102 103 /* memory space */ 104 bus_space_tag_t ch_memt; 105 bus_space_handle_t ch_memh; 106 bus_addr_t ch_membase_addr; 107 bus_size_t ch_memsize; 108 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 109 110 /* I/O space */ 111 bus_space_tag_t ch_iot; 112 bus_addr_t ch_iobase; 113 bus_size_t ch_iosize; 114 115 /* card interrupt */ 116 int (*ch_ih_card_func)(void *); 117 void *ch_ih_card_arg; 118 int ch_attached; 119 }; 120 121 struct hd64465pcmcia_event { 122 int __queued; 123 enum hd64465pcmcia_event_type pe_type; 124 struct hd64465pcmcia_channel *pe_ch; 125 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 126 }; 127 128 struct hd64465pcmcia_softc { 129 struct device sc_dev; 130 enum hd64465_module_id sc_module_id; 131 int sc_shutdown; 132 133 /* kv mapped Area 5, 6 */ 134 vaddr_t sc_area5; 135 vaddr_t sc_area6; 136 137 /* CSC event */ 138 lwp_t *sc_event_thread; 139 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 140 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 141 142 struct hd64465pcmcia_channel sc_ch[2]; 143 }; 144 145 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 146 struct pcmcia_mem_handle *); 147 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 148 struct pcmcia_mem_handle *); 149 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 151 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 152 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 153 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 154 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 155 struct pcmcia_io_handle *); 156 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 157 bus_size_t, struct pcmcia_io_handle *, int *); 158 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 159 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 160 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 161 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 162 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 163 struct pcmcia_function *, int, int (*)(void *), void *); 164 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 165 void *); 166 167 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 168 hd64465pcmcia_chip_mem_alloc, 169 hd64465pcmcia_chip_mem_free, 170 hd64465pcmcia_chip_mem_map, 171 hd64465pcmcia_chip_mem_unmap, 172 hd64465pcmcia_chip_io_alloc, 173 hd64465pcmcia_chip_io_free, 174 hd64465pcmcia_chip_io_map, 175 hd64465pcmcia_chip_io_unmap, 176 hd64465pcmcia_chip_intr_establish, 177 hd64465pcmcia_chip_intr_disestablish, 178 hd64465pcmcia_chip_socket_enable, 179 hd64465pcmcia_chip_socket_disable, 180 hd64465pcmcia_chip_socket_settype, 181 }; 182 183 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 184 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 185 STATIC int hd64465pcmcia_print(void *, const char *); 186 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, 187 const int *, void *); 188 189 CFATTACH_DECL(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 190 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 191 192 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 193 /* hot plug */ 194 STATIC void hd64465pcmcia_event_thread(void *); 195 STATIC void __queue_event(struct hd64465pcmcia_channel *, 196 enum hd64465pcmcia_event_type); 197 /* interrupt handler */ 198 STATIC int hd64465pcmcia_intr(void *); 199 /* card status */ 200 STATIC enum hd64465pcmcia_event_type __detect_card(int); 201 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 202 /* bus width */ 203 STATIC void __sh_set_bus_width(int, int); 204 /* bus space access */ 205 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, uint32_t); 206 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 207 208 #define DELAY_MS(x) delay((x) * 1000) 209 210 int 211 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 struct hd64465_attach_args *ha = aux; 214 215 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 216 } 217 218 void 219 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 220 { 221 struct hd64465_attach_args *ha = aux; 222 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 223 int error; 224 225 sc->sc_module_id = ha->ha_module_id; 226 227 printf("\n"); 228 229 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 230 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 231 232 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) { 233 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 234 if (sc->sc_area5) 235 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000, 236 UVM_KMF_VAONLY); 237 if (sc->sc_area6) 238 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000, 239 UVM_KMF_VAONLY); 240 241 return; 242 } 243 244 /* Channel 0/1 common CSC event queue */ 245 SIMPLEQ_INIT (&sc->sc_event_head); 246 247 error = kthread_create(PRI_NONE, 0, NULL, hd64465pcmcia_event_thread, 248 sc, &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 249 KASSERT(error == 0); 250 251 hd64465pcmcia_attach_channel(sc, 0); 252 hd64465pcmcia_attach_channel(sc, 1); 253 } 254 255 void 256 hd64465pcmcia_event_thread(void *arg) 257 { 258 struct hd64465pcmcia_softc *sc = arg; 259 struct hd64465pcmcia_event *pe; 260 int s; 261 262 while (!sc->sc_shutdown) { 263 tsleep(sc, PWAIT, "CSC wait", 0); 264 s = splhigh(); 265 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 266 splx(s); 267 switch (pe->pe_type) { 268 default: 269 printf("%s: unknown event.\n", __FUNCTION__); 270 break; 271 case EVENT_INSERT: 272 DPRINTF("insert event.\n"); 273 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 274 break; 275 case EVENT_REMOVE: 276 DPRINTF("remove event.\n"); 277 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 278 DETACH_FORCE); 279 break; 280 } 281 s = splhigh(); 282 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 283 pe->__queued = 0; 284 } 285 splx(s); 286 } 287 /* NOTREACHED */ 288 } 289 290 int 291 hd64465pcmcia_print(void *arg, const char *pnp) 292 { 293 294 if (pnp) 295 aprint_normal("pcmcia at %s", pnp); 296 297 return (UNCONF); 298 } 299 300 int 301 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, 302 const int *ldesc, void *aux) 303 { 304 struct pcmciabus_attach_args *paa = aux; 305 struct hd64465pcmcia_channel *ch = 306 (struct hd64465pcmcia_channel *)paa->pch; 307 308 if (ch->ch_channel == 0) { 309 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 310 PCMCIABUSCF_CONTROLLER_DEFAULT && 311 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 312 return 0; 313 } else { 314 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 315 PCMCIABUSCF_CONTROLLER_DEFAULT && 316 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 317 return 0; 318 } 319 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 320 321 return (config_match(parent, cf, aux)); 322 } 323 324 void 325 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 326 { 327 struct device *parent = (struct device *)sc; 328 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 329 struct pcmciabus_attach_args paa; 330 bus_addr_t baseaddr; 331 uint8_t r; 332 int i; 333 334 ch->ch_parent = sc; 335 ch->ch_channel = channel; 336 337 /* 338 * Continuous 16-MB Area Mode 339 */ 340 /* set Continuous 16-MB Area Mode */ 341 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 342 r &= ~HD64461_PCCGCR_MMOD; 343 r |= HD64461_PCCGCR_MMOD_16M; 344 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 345 346 /* Attibute/Common memory extent */ 347 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 348 349 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 350 baseaddr, 0x01000000); /* 16MB */ 351 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 352 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 353 354 /* Common memory space extent */ 355 ch->ch_memsize = 0x01000000; 356 for (i = 0; i < MEMWIN_16M_MAX; i++) { 357 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 358 baseaddr + 0x01000000, ch->ch_memsize); 359 } 360 361 /* I/O port extent */ 362 ch->ch_iobase = 0; 363 ch->ch_iosize = 0x01000000; 364 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 365 baseaddr + 0x01000000 * 2, ch->ch_iosize); 366 367 /* Interrupt */ 368 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 369 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 370 371 paa.paa_busname = "pcmcia"; 372 paa.pch = (pcmcia_chipset_handle_t)ch; 373 paa.iobase = ch->ch_iobase; 374 paa.iosize = ch->ch_iosize; 375 376 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 377 hd64465pcmcia_print, hd64465pcmcia_submatch); 378 379 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 380 ch->ch_attached = 1; 381 pcmcia_card_attach(ch->ch_pcmcia); 382 } 383 } 384 385 int 386 hd64465pcmcia_intr(void *arg) 387 { 388 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 389 uint32_t cscr; 390 uint8_t r; 391 int ret = 0; 392 393 cscr = HD64461_PCCCSCR(ch->ch_channel); 394 r = hd64465_reg_read_1(cscr); 395 396 /* clear interrtupt (don't change power switch select) */ 397 hd64465_reg_write_1(cscr, r & ~0x40); 398 399 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 400 if (ch->ch_ih_card_func) { 401 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 402 } else { 403 DPRINTF("spurious IREQ interrupt.\n"); 404 } 405 } 406 407 if (r & HD64461_PCC0CSCR_P0CDC) 408 __queue_event(ch, __detect_card(ch->ch_channel)); 409 410 return (ret); 411 } 412 413 void 414 __queue_event(struct hd64465pcmcia_channel *ch, 415 enum hd64465pcmcia_event_type type) 416 { 417 struct hd64465pcmcia_event *pe, *pool; 418 struct hd64465pcmcia_softc *sc = ch->ch_parent; 419 int i; 420 int s = splhigh(); 421 422 if (type == EVENT_NONE) 423 goto out; 424 425 pe = 0; 426 pool = sc->sc_event_pool; 427 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 428 if (!pool[i].__queued) { 429 pe = &pool[i]; 430 break; 431 } 432 } 433 434 if (pe == 0) { 435 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 436 EVENT_QUEUE_MAX); 437 goto out; 438 } 439 440 if ((ch->ch_attached && (type == EVENT_INSERT)) || 441 (!ch->ch_attached && (type == EVENT_REMOVE))) { 442 DPRINTF("spurious CSC interrupt.\n"); 443 goto out; 444 } 445 446 ch->ch_attached = (type == EVENT_INSERT); 447 pe->__queued = 1; 448 pe->pe_type = type; 449 pe->pe_ch = ch; 450 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 451 wakeup(sc); 452 out: 453 splx(s); 454 } 455 456 /* 457 * Interface for pcmcia driver. 458 */ 459 /* 460 * Interrupt. 461 */ 462 void * 463 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 464 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 465 { 466 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 467 int channel = ch->ch_channel; 468 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 469 uint8_t r; 470 int s = splhigh(); 471 472 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 473 ipl); 474 475 ch->ch_ih_card_func = ih_func; 476 ch->ch_ih_card_arg = ih_arg; 477 478 /* Enable card interrupt */ 479 r = hd64465_reg_read_1(cscier); 480 /* set level mode */ 481 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 482 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 483 hd64465_reg_write_1(cscier, r); 484 485 splx(s); 486 487 return (void *)ih_func; 488 } 489 490 void 491 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 492 { 493 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 494 int channel = ch->ch_channel; 495 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 496 int s = splhigh(); 497 uint8_t r; 498 499 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 500 IPL_TTY); 501 502 /* Disable card interrupt */ 503 r = hd64465_reg_read_1(cscier); 504 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 505 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 506 hd64465_reg_write_1(cscier, r); 507 508 ch->ch_ih_card_func = 0; 509 510 splx(s); 511 } 512 513 /* 514 * Bus resources. 515 */ 516 int 517 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 518 struct pcmcia_mem_handle *pcmhp) 519 { 520 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 521 522 pcmhp->memt = ch->ch_memt; 523 pcmhp->addr = ch->ch_membase_addr; 524 pcmhp->memh = ch->ch_memh; 525 pcmhp->size = size; 526 pcmhp->realsize = size; 527 528 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 529 530 return (0); 531 } 532 533 void 534 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 535 struct pcmcia_mem_handle *pcmhp) 536 { 537 /* NO-OP */ 538 } 539 540 int 541 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 542 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 543 bus_size_t *offsetp, int *windowp) 544 { 545 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 546 struct hd64465pcmcia_window_cookie *cookie; 547 bus_addr_t ofs; 548 549 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 550 M_DEVBUF, M_NOWAIT); 551 KASSERT(cookie); 552 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 553 554 /* Address */ 555 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 556 cookie->wc_tag = ch->ch_memt; 557 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 558 size, &cookie->wc_handle) != 0) 559 goto bad; 560 561 *offsetp = card_addr; 562 cookie->wc_window = -1; 563 } else { 564 int window = card_addr / ch->ch_memsize; 565 KASSERT(window < MEMWIN_16M_MAX); 566 567 cookie->wc_tag = ch->ch_cmemt[window]; 568 ofs = card_addr - window * ch->ch_memsize; 569 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 570 &cookie->wc_handle) != 0) 571 goto bad; 572 573 /* XXX bogus. check window per common memory access. */ 574 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 575 *offsetp = ofs + 0x01000000; /* skip attribute area */ 576 cookie->wc_window = window; 577 } 578 cookie->wc_size = size; 579 *windowp = (int)cookie; 580 581 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 582 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 583 584 return (0); 585 bad: 586 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 587 free(cookie, M_DEVBUF); 588 589 return (1); 590 } 591 592 void 593 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 594 { 595 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 596 597 if (cookie->wc_window != -1) 598 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 599 cookie->wc_size); 600 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 601 free(cookie, M_DEVBUF); 602 } 603 604 int 605 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 606 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 607 { 608 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 609 610 if (start) { 611 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 612 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 613 return (1); 614 } 615 pcihp->addr = pcihp->ioh; 616 DPRINTF("map %#lx+%#lx\n", start, size); 617 } else { 618 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 619 ch->ch_iobase + ch->ch_iosize - 1, 620 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 621 DPRINTF("couldn't allocate %#lx\n", size); 622 return (1); 623 } 624 pcihp->flags = PCMCIA_IO_ALLOCATED; 625 } 626 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 627 628 pcihp->iot = ch->ch_iot; 629 pcihp->size = size; 630 631 return (0); 632 } 633 634 int 635 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 636 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 637 int *windowp) 638 { 639 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 640 #ifdef HD64465PCMCIA_DEBUG 641 static const char *width_names[] = { "auto", "io8", "io16" }; 642 #endif 643 644 __sh_set_bus_width(ch->ch_channel, width); 645 646 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 647 width_names[width]); 648 649 return (0); 650 } 651 652 void 653 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 654 struct pcmcia_io_handle *pcihp) 655 { 656 657 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 658 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 659 else 660 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 661 662 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 663 } 664 665 void 666 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 667 { 668 /* nothing to do */ 669 } 670 671 /* 672 * Enable/Disable 673 */ 674 void 675 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 676 { 677 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 678 int channel = ch->ch_channel; 679 bus_addr_t gcr; 680 uint8_t r; 681 682 DPRINTF("enable channel %d\n", channel); 683 gcr = HD64461_PCCGCR(channel); 684 685 r = hd64465_reg_read_1(gcr); 686 r &= ~HD64461_PCC0GCR_P0PCCT; 687 hd64465_reg_write_1(gcr, r); 688 689 /* Set Common memory area #0. */ 690 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 691 692 DPRINTF("OK.\n"); 693 } 694 695 void 696 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 697 { 698 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 699 int channel = ch->ch_channel; 700 bus_addr_t gcr; 701 uint8_t r; 702 703 DPRINTF("settype channel %d\n", channel); 704 gcr = HD64461_PCCGCR(channel); 705 706 /* Set the card type */ 707 r = hd64465_reg_read_1(gcr); 708 if (type == PCMCIA_IFTYPE_IO) 709 r |= HD64461_PCC0GCR_P0PCCT; 710 else 711 r &= ~HD64461_PCC0GCR_P0PCCT; 712 hd64465_reg_write_1(gcr, r); 713 714 DPRINTF("OK.\n"); 715 } 716 717 void 718 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 719 { 720 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 721 int channel = ch->ch_channel; 722 723 /* dont' disable CSC interrupt */ 724 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 725 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 726 } 727 728 /* 729 * Card detect 730 */ 731 enum hd64465pcmcia_event_type 732 __detect_card(int channel) 733 { 734 uint8_t r; 735 736 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 737 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 738 739 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 740 DPRINTF("remove\n"); 741 return EVENT_REMOVE; 742 } 743 if (r == 0) { 744 DPRINTF("insert\n"); 745 return EVENT_INSERT; 746 } 747 DPRINTF("transition\n"); 748 749 return (EVENT_NONE); 750 } 751 752 /* 753 * Memory window access ops. 754 */ 755 void 756 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 757 { 758 bus_addr_t a = HD64461_PCCGCR(channel); 759 uint8_t r; 760 761 r = hd64465_reg_read_1(a); 762 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 763 764 switch (window) { 765 case MEMWIN_16M_COMMON_0: 766 break; 767 case MEMWIN_16M_COMMON_1: 768 r |= HD64461_PCCGCR_PA24; 769 break; 770 case MEMWIN_16M_COMMON_2: 771 r |= HD64461_PCCGCR_PA25; 772 break; 773 case MEMWIN_16M_COMMON_3: 774 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 775 break; 776 } 777 778 hd64465_reg_write_1(a, r); 779 } 780 781 /* 782 * SH interface. 783 */ 784 void 785 __sh_set_bus_width(int channel, int width) 786 { 787 uint16_t r16; 788 789 r16 = _reg_read_2(SH4_BCR2); 790 #ifdef HD64465PCMCIA_DEBUG 791 dbg_bit_print_msg(r16, "BCR2"); 792 #endif 793 if (channel == 0) { 794 r16 &= ~((1 << 13)|(1 << 12)); 795 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 796 } else { 797 r16 &= ~((1 << 11)|(1 << 10)); 798 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 799 } 800 _reg_write_2(SH4_BCR2, r16); 801 } 802 803 vaddr_t 804 __sh_hd64465_map_2page(paddr_t pa) 805 { 806 static const uint32_t mode[] = 807 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 808 vaddr_t va, v; 809 int i; 810 811 /* allocate kernel virtual */ 812 v = va = uvm_km_alloc(kernel_map, 0x03000000, 0, UVM_KMF_VAONLY); 813 if (va == 0) { 814 PRINTF("can't allocate virtual for paddr 0x%08x\n", 815 (unsigned)pa); 816 817 return (0); 818 } 819 820 /* map to physical addreess with specified memory type. */ 821 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 822 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 823 pmap_kremove(v, 0x03000000); 824 uvm_km_free(kernel_map, v, 0x03000000, UVM_KMF_VAONLY); 825 return (0); 826 } 827 } 828 829 return (v); 830 } 831 832 int 833 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, uint32_t flags) 834 { 835 pt_entry_t *pte; 836 paddr_t epa; 837 838 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 839 ((sz & PAGE_MASK) == 0)); 840 841 epa = pa + sz; 842 while (pa < epa) { 843 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 844 pte = __pmap_kpte_lookup(va); 845 KDASSERT(pte); 846 *pte |= flags; /* PTEA PCMCIA assistant bit */ 847 sh_tlb_update(0, va, *pte); 848 pa += PAGE_SIZE; 849 va += PAGE_SIZE; 850 } 851 852 return (0); 853 } 854
Indexes created Fri Oct 03 02:09:57 GMT 2025