hd64465pcmcia.c revision 1.26
1 /* $NetBSD: hd64465pcmcia.c,v 1.26 2009/11/07 07:27:44 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.26 2009/11/07 07:27:44 cegger Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kthread.h> 40 #include <sys/boot_flag.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 #include <sh3/mmu.h> 53 54 #include <hpcsh/dev/hd64465/hd64465reg.h> 55 #include <hpcsh/dev/hd64465/hd64465var.h> 56 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 58 59 #include "locators.h" 60 61 #ifdef HD64465PCMCIA_DEBUG 62 #define DPRINTF_ENABLE 63 #define DPRINTF_DEBUG hd64465pcmcia_debug 64 #endif 65 #include <machine/debug.h> 66 67 enum memory_window_16 { 68 MEMWIN_16M_COMMON_0, 69 MEMWIN_16M_COMMON_1, 70 MEMWIN_16M_COMMON_2, 71 MEMWIN_16M_COMMON_3, 72 }; 73 #define MEMWIN_16M_MAX 4 74 75 enum hd64465pcmcia_event_type { 76 EVENT_NONE, 77 EVENT_INSERT, 78 EVENT_REMOVE, 79 }; 80 #define EVENT_QUEUE_MAX 5 81 82 struct hd64465pcmcia_softc; /* forward declaration */ 83 84 struct hd64465pcmcia_window_cookie { 85 bus_space_tag_t wc_tag; 86 bus_space_handle_t wc_handle; 87 int wc_size; 88 int wc_window; 89 }; 90 91 struct hd64465pcmcia_channel { 92 struct hd64465pcmcia_softc *ch_parent; 93 struct device *ch_pcmcia; 94 int ch_channel; 95 96 /* memory space */ 97 bus_space_tag_t ch_memt; 98 bus_space_handle_t ch_memh; 99 bus_addr_t ch_membase_addr; 100 bus_size_t ch_memsize; 101 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 102 103 /* I/O space */ 104 bus_space_tag_t ch_iot; 105 bus_addr_t ch_iobase; 106 bus_size_t ch_iosize; 107 108 /* card interrupt */ 109 int (*ch_ih_card_func)(void *); 110 void *ch_ih_card_arg; 111 int ch_attached; 112 }; 113 114 struct hd64465pcmcia_event { 115 int __queued; 116 enum hd64465pcmcia_event_type pe_type; 117 struct hd64465pcmcia_channel *pe_ch; 118 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 119 }; 120 121 struct hd64465pcmcia_softc { 122 struct device sc_dev; 123 enum hd64465_module_id sc_module_id; 124 int sc_shutdown; 125 126 /* kv mapped Area 5, 6 */ 127 vaddr_t sc_area5; 128 vaddr_t sc_area6; 129 130 /* CSC event */ 131 lwp_t *sc_event_thread; 132 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 133 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 134 135 struct hd64465pcmcia_channel sc_ch[2]; 136 }; 137 138 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 139 struct pcmcia_mem_handle *); 140 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 141 struct pcmcia_mem_handle *); 142 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 143 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 144 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 145 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 146 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 147 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 148 struct pcmcia_io_handle *); 149 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_io_handle *, int *); 151 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 152 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 153 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 154 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 155 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*)(void *), void *); 157 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 158 void *); 159 160 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 161 hd64465pcmcia_chip_mem_alloc, 162 hd64465pcmcia_chip_mem_free, 163 hd64465pcmcia_chip_mem_map, 164 hd64465pcmcia_chip_mem_unmap, 165 hd64465pcmcia_chip_io_alloc, 166 hd64465pcmcia_chip_io_free, 167 hd64465pcmcia_chip_io_map, 168 hd64465pcmcia_chip_io_unmap, 169 hd64465pcmcia_chip_intr_establish, 170 hd64465pcmcia_chip_intr_disestablish, 171 hd64465pcmcia_chip_socket_enable, 172 hd64465pcmcia_chip_socket_disable, 173 hd64465pcmcia_chip_socket_settype, 174 }; 175 176 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 177 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 178 STATIC int hd64465pcmcia_print(void *, const char *); 179 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, 180 const int *, void *); 181 182 CFATTACH_DECL(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 183 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 184 185 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 186 /* hot plug */ 187 STATIC void hd64465pcmcia_event_thread(void *); 188 STATIC void __queue_event(struct hd64465pcmcia_channel *, 189 enum hd64465pcmcia_event_type); 190 /* interrupt handler */ 191 STATIC int hd64465pcmcia_intr(void *); 192 /* card status */ 193 STATIC enum hd64465pcmcia_event_type __detect_card(int); 194 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 195 /* bus width */ 196 STATIC void __sh_set_bus_width(int, int); 197 /* bus space access */ 198 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, uint32_t); 199 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 200 201 #define DELAY_MS(x) delay((x) * 1000) 202 203 int 204 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 205 { 206 struct hd64465_attach_args *ha = aux; 207 208 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 209 } 210 211 void 212 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 213 { 214 struct hd64465_attach_args *ha = aux; 215 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 216 int error; 217 218 sc->sc_module_id = ha->ha_module_id; 219 220 printf("\n"); 221 222 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 223 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 224 225 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) { 226 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 227 if (sc->sc_area5) 228 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000, 229 UVM_KMF_VAONLY); 230 if (sc->sc_area6) 231 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000, 232 UVM_KMF_VAONLY); 233 234 return; 235 } 236 237 /* Channel 0/1 common CSC event queue */ 238 SIMPLEQ_INIT (&sc->sc_event_head); 239 240 error = kthread_create(PRI_NONE, 0, NULL, hd64465pcmcia_event_thread, 241 sc, &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 242 KASSERT(error == 0); 243 244 hd64465pcmcia_attach_channel(sc, 0); 245 hd64465pcmcia_attach_channel(sc, 1); 246 } 247 248 void 249 hd64465pcmcia_event_thread(void *arg) 250 { 251 struct hd64465pcmcia_softc *sc = arg; 252 struct hd64465pcmcia_event *pe; 253 int s; 254 255 while (!sc->sc_shutdown) { 256 tsleep(sc, PWAIT, "CSC wait", 0); 257 s = splhigh(); 258 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 259 splx(s); 260 switch (pe->pe_type) { 261 default: 262 printf("%s: unknown event.\n", __func__); 263 break; 264 case EVENT_INSERT: 265 DPRINTF("insert event.\n"); 266 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 267 break; 268 case EVENT_REMOVE: 269 DPRINTF("remove event.\n"); 270 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 271 DETACH_FORCE); 272 break; 273 } 274 s = splhigh(); 275 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 276 pe->__queued = 0; 277 } 278 splx(s); 279 } 280 /* NOTREACHED */ 281 } 282 283 int 284 hd64465pcmcia_print(void *arg, const char *pnp) 285 { 286 287 if (pnp) 288 aprint_normal("pcmcia at %s", pnp); 289 290 return (UNCONF); 291 } 292 293 int 294 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, 295 const int *ldesc, void *aux) 296 { 297 struct pcmciabus_attach_args *paa = aux; 298 struct hd64465pcmcia_channel *ch = 299 (struct hd64465pcmcia_channel *)paa->pch; 300 301 if (ch->ch_channel == 0) { 302 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 303 PCMCIABUSCF_CONTROLLER_DEFAULT && 304 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 305 return 0; 306 } else { 307 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 308 PCMCIABUSCF_CONTROLLER_DEFAULT && 309 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 310 return 0; 311 } 312 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 313 314 return (config_match(parent, cf, aux)); 315 } 316 317 void 318 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 319 { 320 struct device *parent = (struct device *)sc; 321 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 322 struct pcmciabus_attach_args paa; 323 bus_addr_t baseaddr; 324 uint8_t r; 325 int i; 326 327 ch->ch_parent = sc; 328 ch->ch_channel = channel; 329 330 /* 331 * Continuous 16-MB Area Mode 332 */ 333 /* set Continuous 16-MB Area Mode */ 334 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 335 r &= ~HD64461_PCCGCR_MMOD; 336 r |= HD64461_PCCGCR_MMOD_16M; 337 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 338 339 /* Attibute/Common memory extent */ 340 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 341 342 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 343 baseaddr, 0x01000000); /* 16MB */ 344 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 345 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 346 347 /* Common memory space extent */ 348 ch->ch_memsize = 0x01000000; 349 for (i = 0; i < MEMWIN_16M_MAX; i++) { 350 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 351 baseaddr + 0x01000000, ch->ch_memsize); 352 } 353 354 /* I/O port extent */ 355 ch->ch_iobase = 0; 356 ch->ch_iosize = 0x01000000; 357 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 358 baseaddr + 0x01000000 * 2, ch->ch_iosize); 359 360 /* Interrupt */ 361 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 362 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 363 364 paa.paa_busname = "pcmcia"; 365 paa.pch = (pcmcia_chipset_handle_t)ch; 366 paa.iobase = ch->ch_iobase; 367 paa.iosize = ch->ch_iosize; 368 369 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 370 hd64465pcmcia_print, hd64465pcmcia_submatch); 371 372 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 373 ch->ch_attached = 1; 374 pcmcia_card_attach(ch->ch_pcmcia); 375 } 376 } 377 378 int 379 hd64465pcmcia_intr(void *arg) 380 { 381 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 382 uint32_t cscr; 383 uint8_t r; 384 int ret = 0; 385 386 cscr = HD64461_PCCCSCR(ch->ch_channel); 387 r = hd64465_reg_read_1(cscr); 388 389 /* clear interrtupt (don't change power switch select) */ 390 hd64465_reg_write_1(cscr, r & ~0x40); 391 392 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 393 if (ch->ch_ih_card_func) { 394 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 395 } else { 396 DPRINTF("spurious IREQ interrupt.\n"); 397 } 398 } 399 400 if (r & HD64461_PCC0CSCR_P0CDC) 401 __queue_event(ch, __detect_card(ch->ch_channel)); 402 403 return (ret); 404 } 405 406 void 407 __queue_event(struct hd64465pcmcia_channel *ch, 408 enum hd64465pcmcia_event_type type) 409 { 410 struct hd64465pcmcia_event *pe, *pool; 411 struct hd64465pcmcia_softc *sc = ch->ch_parent; 412 int i; 413 int s = splhigh(); 414 415 if (type == EVENT_NONE) 416 goto out; 417 418 pe = 0; 419 pool = sc->sc_event_pool; 420 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 421 if (!pool[i].__queued) { 422 pe = &pool[i]; 423 break; 424 } 425 } 426 427 if (pe == 0) { 428 printf("%s: event FIFO overflow (max %d).\n", __func__, 429 EVENT_QUEUE_MAX); 430 goto out; 431 } 432 433 if ((ch->ch_attached && (type == EVENT_INSERT)) || 434 (!ch->ch_attached && (type == EVENT_REMOVE))) { 435 DPRINTF("spurious CSC interrupt.\n"); 436 goto out; 437 } 438 439 ch->ch_attached = (type == EVENT_INSERT); 440 pe->__queued = 1; 441 pe->pe_type = type; 442 pe->pe_ch = ch; 443 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 444 wakeup(sc); 445 out: 446 splx(s); 447 } 448 449 /* 450 * Interface for pcmcia driver. 451 */ 452 /* 453 * Interrupt. 454 */ 455 void * 456 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 457 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 458 { 459 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 460 int channel = ch->ch_channel; 461 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 462 uint8_t r; 463 int s = splhigh(); 464 465 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 466 ipl); 467 468 ch->ch_ih_card_func = ih_func; 469 ch->ch_ih_card_arg = ih_arg; 470 471 /* Enable card interrupt */ 472 r = hd64465_reg_read_1(cscier); 473 /* set level mode */ 474 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 475 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 476 hd64465_reg_write_1(cscier, r); 477 478 splx(s); 479 480 return (void *)ih_func; 481 } 482 483 void 484 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 485 { 486 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 487 int channel = ch->ch_channel; 488 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 489 int s = splhigh(); 490 uint8_t r; 491 492 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 493 IPL_TTY); 494 495 /* Disable card interrupt */ 496 r = hd64465_reg_read_1(cscier); 497 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 498 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 499 hd64465_reg_write_1(cscier, r); 500 501 ch->ch_ih_card_func = 0; 502 503 splx(s); 504 } 505 506 /* 507 * Bus resources. 508 */ 509 int 510 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 511 struct pcmcia_mem_handle *pcmhp) 512 { 513 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 514 515 pcmhp->memt = ch->ch_memt; 516 pcmhp->addr = ch->ch_membase_addr; 517 pcmhp->memh = ch->ch_memh; 518 pcmhp->size = size; 519 pcmhp->realsize = size; 520 521 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 522 523 return (0); 524 } 525 526 void 527 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 528 struct pcmcia_mem_handle *pcmhp) 529 { 530 /* NO-OP */ 531 } 532 533 int 534 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 535 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 536 bus_size_t *offsetp, int *windowp) 537 { 538 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 539 struct hd64465pcmcia_window_cookie *cookie; 540 bus_addr_t ofs; 541 542 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 543 M_DEVBUF, M_NOWAIT); 544 KASSERT(cookie); 545 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 546 547 /* Address */ 548 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 549 cookie->wc_tag = ch->ch_memt; 550 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 551 size, &cookie->wc_handle) != 0) 552 goto bad; 553 554 *offsetp = card_addr; 555 cookie->wc_window = -1; 556 } else { 557 int window = card_addr / ch->ch_memsize; 558 KASSERT(window < MEMWIN_16M_MAX); 559 560 cookie->wc_tag = ch->ch_cmemt[window]; 561 ofs = card_addr - window * ch->ch_memsize; 562 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 563 &cookie->wc_handle) != 0) 564 goto bad; 565 566 /* XXX bogus. check window per common memory access. */ 567 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 568 *offsetp = ofs + 0x01000000; /* skip attribute area */ 569 cookie->wc_window = window; 570 } 571 cookie->wc_size = size; 572 *windowp = (int)cookie; 573 574 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 575 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 576 577 return (0); 578 bad: 579 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 580 free(cookie, M_DEVBUF); 581 582 return (1); 583 } 584 585 void 586 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 587 { 588 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 589 590 if (cookie->wc_window != -1) 591 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 592 cookie->wc_size); 593 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 594 free(cookie, M_DEVBUF); 595 } 596 597 int 598 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 599 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 600 { 601 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 602 603 if (start) { 604 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 605 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 606 return (1); 607 } 608 pcihp->addr = pcihp->ioh; 609 DPRINTF("map %#lx+%#lx\n", start, size); 610 } else { 611 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 612 ch->ch_iobase + ch->ch_iosize - 1, 613 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 614 DPRINTF("couldn't allocate %#lx\n", size); 615 return (1); 616 } 617 pcihp->flags = PCMCIA_IO_ALLOCATED; 618 } 619 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 620 621 pcihp->iot = ch->ch_iot; 622 pcihp->size = size; 623 624 return (0); 625 } 626 627 int 628 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 629 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 630 int *windowp) 631 { 632 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 633 #ifdef HD64465PCMCIA_DEBUG 634 static const char *width_names[] = { "auto", "io8", "io16" }; 635 #endif 636 637 __sh_set_bus_width(ch->ch_channel, width); 638 639 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 640 width_names[width]); 641 642 return (0); 643 } 644 645 void 646 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 647 struct pcmcia_io_handle *pcihp) 648 { 649 650 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 651 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 652 else 653 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 654 655 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 656 } 657 658 void 659 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 660 { 661 /* nothing to do */ 662 } 663 664 /* 665 * Enable/Disable 666 */ 667 void 668 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 669 { 670 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 671 int channel = ch->ch_channel; 672 bus_addr_t gcr; 673 uint8_t r; 674 675 DPRINTF("enable channel %d\n", channel); 676 gcr = HD64461_PCCGCR(channel); 677 678 r = hd64465_reg_read_1(gcr); 679 r &= ~HD64461_PCC0GCR_P0PCCT; 680 hd64465_reg_write_1(gcr, r); 681 682 /* Set Common memory area #0. */ 683 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 684 685 DPRINTF("OK.\n"); 686 } 687 688 void 689 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 690 { 691 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 692 int channel = ch->ch_channel; 693 bus_addr_t gcr; 694 uint8_t r; 695 696 DPRINTF("settype channel %d\n", channel); 697 gcr = HD64461_PCCGCR(channel); 698 699 /* Set the card type */ 700 r = hd64465_reg_read_1(gcr); 701 if (type == PCMCIA_IFTYPE_IO) 702 r |= HD64461_PCC0GCR_P0PCCT; 703 else 704 r &= ~HD64461_PCC0GCR_P0PCCT; 705 hd64465_reg_write_1(gcr, r); 706 707 DPRINTF("OK.\n"); 708 } 709 710 void 711 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 712 { 713 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 714 int channel = ch->ch_channel; 715 716 /* dont' disable CSC interrupt */ 717 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 718 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 719 } 720 721 /* 722 * Card detect 723 */ 724 enum hd64465pcmcia_event_type 725 __detect_card(int channel) 726 { 727 uint8_t r; 728 729 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 730 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 731 732 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 733 DPRINTF("remove\n"); 734 return EVENT_REMOVE; 735 } 736 if (r == 0) { 737 DPRINTF("insert\n"); 738 return EVENT_INSERT; 739 } 740 DPRINTF("transition\n"); 741 742 return (EVENT_NONE); 743 } 744 745 /* 746 * Memory window access ops. 747 */ 748 void 749 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 750 { 751 bus_addr_t a = HD64461_PCCGCR(channel); 752 uint8_t r; 753 754 r = hd64465_reg_read_1(a); 755 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 756 757 switch (window) { 758 case MEMWIN_16M_COMMON_0: 759 break; 760 case MEMWIN_16M_COMMON_1: 761 r |= HD64461_PCCGCR_PA24; 762 break; 763 case MEMWIN_16M_COMMON_2: 764 r |= HD64461_PCCGCR_PA25; 765 break; 766 case MEMWIN_16M_COMMON_3: 767 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 768 break; 769 } 770 771 hd64465_reg_write_1(a, r); 772 } 773 774 /* 775 * SH interface. 776 */ 777 void 778 __sh_set_bus_width(int channel, int width) 779 { 780 uint16_t r16; 781 782 r16 = _reg_read_2(SH4_BCR2); 783 #ifdef HD64465PCMCIA_DEBUG 784 dbg_bit_print_msg(r16, "BCR2"); 785 #endif 786 if (channel == 0) { 787 r16 &= ~((1 << 13)|(1 << 12)); 788 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 789 } else { 790 r16 &= ~((1 << 11)|(1 << 10)); 791 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 792 } 793 _reg_write_2(SH4_BCR2, r16); 794 } 795 796 vaddr_t 797 __sh_hd64465_map_2page(paddr_t pa) 798 { 799 static const uint32_t mode[] = 800 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 801 vaddr_t va, v; 802 int i; 803 804 /* allocate kernel virtual */ 805 v = va = uvm_km_alloc(kernel_map, 0x03000000, 0, UVM_KMF_VAONLY); 806 if (va == 0) { 807 PRINTF("can't allocate virtual for paddr 0x%08x\n", 808 (unsigned)pa); 809 810 return (0); 811 } 812 813 /* map to physical addreess with specified memory type. */ 814 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 815 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 816 pmap_kremove(v, 0x03000000); 817 uvm_km_free(kernel_map, v, 0x03000000, UVM_KMF_VAONLY); 818 return (0); 819 } 820 } 821 822 return (v); 823 } 824 825 int 826 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, uint32_t flags) 827 { 828 pt_entry_t *pte; 829 paddr_t epa; 830 831 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 832 ((sz & PAGE_MASK) == 0)); 833 834 epa = pa + sz; 835 while (pa < epa) { 836 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0); 837 pte = __pmap_kpte_lookup(va); 838 KDASSERT(pte); 839 *pte |= flags; /* PTEA PCMCIA assistant bit */ 840 sh_tlb_update(0, va, *pte); 841 pa += PAGE_SIZE; 842 va += PAGE_SIZE; 843 } 844 845 return (0); 846 } 847
Indexes created Fri Oct 03 02:09:57 GMT 2025